1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017 NXP 4 * Copyright (C) 2014 Freescale Semiconductor 5 */ 6 7 #ifndef __LS2_COMMON_H 8 #define __LS2_COMMON_H 9 10 #define CONFIG_REMAKE_ELF 11 #define CONFIG_GICV3 12 13 #include <asm/arch/stream_id_lsch3.h> 14 #include <asm/arch/config.h> 15 16 /* Link Definitions */ 17 #ifdef CONFIG_TFABOOT 18 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE 19 #else 20 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 21 #endif 22 23 /* We need architecture specific misc initializations */ 24 25 /* Link Definitions */ 26 27 #define CONFIG_SKIP_LOWLEVEL_INIT 28 29 #ifndef CONFIG_SYS_FSL_DDR4 30 #define CONFIG_SYS_DDR_RAW_TIMING 31 #endif 32 33 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ 34 35 #define CONFIG_VERY_BIG_RAM 36 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 37 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 38 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 39 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL 40 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 41 42 /* 43 * SMP Definitinos 44 */ 45 #define CPU_RELEASE_ADDR secondary_boot_func 46 47 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS 48 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 49 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL 50 /* 51 * DDR controller use 0 as the base address for binding. 52 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. 53 */ 54 #define CONFIG_SYS_DP_DDR_BASE_PHY 0 55 #define CONFIG_DP_DDR_CTRL 2 56 #define CONFIG_DP_DDR_NUM_CTRLS 1 57 #endif 58 59 /* Generic Timer Definitions */ 60 /* 61 * This is not an accurate number. It is used in start.S. The frequency 62 * will be udpated later when get_bus_freq(0) is available. 63 */ 64 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 65 66 /* Size of malloc() pool */ 67 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) 68 69 /* I2C */ 70 #ifndef CONFIG_DM_I2C 71 #define CONFIG_SYS_I2C 72 #endif 73 74 /* Serial Port */ 75 #define CONFIG_SYS_NS16550_SERIAL 76 #define CONFIG_SYS_NS16550_REG_SIZE 1 77 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 78 79 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 80 81 /* IFC */ 82 #define CONFIG_FSL_IFC 83 84 /* 85 * During booting, IFC is mapped at the region of 0x30000000. 86 * But this region is limited to 256MB. To accommodate NOR, promjet 87 * and FPGA. This region is divided as below: 88 * 0x30000000 - 0x37ffffff : 128MB : NOR flash 89 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet 90 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc 91 * 92 * To accommodate bigger NOR flash and other devices, we will map IFC 93 * chip selects to as below: 94 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole 95 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) 96 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB 97 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) 98 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) 99 * 100 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. 101 * CONFIG_SYS_FLASH_BASE has the final address (core view) 102 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 103 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 104 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting 105 */ 106 107 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL 108 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 109 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 110 111 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 112 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 113 114 #ifndef __ASSEMBLY__ 115 unsigned long long get_qixis_addr(void); 116 #endif 117 #define QIXIS_BASE get_qixis_addr() 118 #define QIXIS_BASE_PHYS 0x20000000 119 #define QIXIS_BASE_PHYS_EARLY 0xC000000 120 #define QIXIS_STAT_PRES1 0xb 121 #define QIXIS_SDID_MASK 0x07 122 #define QIXIS_ESDHC_NO_ADAPTER 0x7 123 124 #define CONFIG_SYS_NAND_BASE 0x530000000ULL 125 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 126 127 /* MC firmware */ 128 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ 129 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 130 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 131 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 132 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 133 /* For LS2085A */ 134 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 135 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 136 137 /* Define phy_reset function to boot the MC based on mcinitcmd. 138 * This happens late enough to properly fixup u-boot env MAC addresses. 139 */ 140 #define CONFIG_RESET_PHY_R 141 142 /* 143 * Carve out a DDR region which will not be used by u-boot/Linux 144 * 145 * It will be used by MC and Debug Server. The MC region must be 146 * 512MB aligned, so the min size to hide is 512MB. 147 */ 148 #ifdef CONFIG_FSL_MC_ENET 149 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) 150 #endif 151 152 /* Command line configuration */ 153 154 /* Miscellaneous configurable options */ 155 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 156 157 /* Physical Memory Map */ 158 /* fixme: these need to be checked against the board */ 159 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 160 161 #define CONFIG_HWCONFIG 162 #define HWCONFIG_BUFFER_SIZE 128 163 164 /* Allow to overwrite serial and ethaddr */ 165 #define CONFIG_ENV_OVERWRITE 166 167 /* Initial environment variables */ 168 #define CONFIG_EXTRA_ENV_SETTINGS \ 169 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 170 "loadaddr=0x80100000\0" \ 171 "kernel_addr=0x100000\0" \ 172 "ramdisk_addr=0x800000\0" \ 173 "ramdisk_size=0x2000000\0" \ 174 "fdt_high=0xa0000000\0" \ 175 "initrd_high=0xffffffffffffffff\0" \ 176 "kernel_start=0x581000000\0" \ 177 "kernel_load=0xa0000000\0" \ 178 "kernel_size=0x2800000\0" \ 179 "console=ttyAMA0,38400n8\0" \ 180 "mcinitcmd=fsl_mc start mc 0x580a00000" \ 181 " 0x580e00000 \0" 182 183 #ifndef CONFIG_TFABOOT 184 #ifdef CONFIG_SD_BOOT 185 #define CONFIG_BOOTCOMMAND "mmc read 0x80200000 0x6800 0x800;"\ 186 " fsl_mc apply dpl 0x80200000 &&" \ 187 " mmc read $kernel_load $kernel_start" \ 188 " $kernel_size && bootm $kernel_load" 189 #else 190 #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \ 191 " cp.b $kernel_start $kernel_load" \ 192 " $kernel_size && bootm $kernel_load" 193 #endif 194 #endif 195 196 /* Monitor Command Prompt */ 197 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 198 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 199 200 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 201 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 202 #define CONFIG_SPL_MAX_SIZE 0x16000 203 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) 204 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 205 206 #ifdef CONFIG_NAND_BOOT 207 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 208 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 209 #endif 210 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 211 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 212 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) 213 214 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 215 216 #include <asm/arch/soc.h> 217 218 #endif /* __LS2_COMMON_H */ 219