1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Bluewater Systems Snapper 9260 and 9G20 modules 4 * 5 * (C) Copyright 2011 Bluewater Systems 6 * Author: Andre Renaud <andre@bluewatersys.com> 7 * Author: Ryan Mallon <ryan@bluewatersys.com> 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* SoC type is defined in boards.cfg */ 14 #include <asm/hardware.h> 15 #include <linux/sizes.h> 16 17 /* ARM asynchronous clock */ 18 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */ 19 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 20 21 /* CPU */ 22 23 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 24 #define CONFIG_SETUP_MEMORY_TAGS 25 #define CONFIG_INITRD_TAG 26 #define CONFIG_SKIP_LOWLEVEL_INIT 27 28 /* SDRAM */ 29 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 30 #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */ 31 #define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \ 32 GENERATED_GBL_DATA_SIZE) 33 34 /* Mem test settings */ 35 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 36 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (1024 * 1024)) 37 38 /* NAND Flash */ 39 #define CONFIG_SYS_MAX_NAND_DEVICE 1 40 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 41 #define CONFIG_SYS_NAND_DBW_8 42 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */ 43 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */ 44 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 45 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 46 47 /* Ethernet */ 48 #define CONFIG_MACB 49 #define CONFIG_RMII 50 #define CONFIG_NET_RETRY_COUNT 20 51 #define CONFIG_RESET_PHY_R 52 #define CONFIG_AT91_WANTS_COMMON_PHY 53 #define CONFIG_TFTP_PORT 54 #define CONFIG_TFTP_TSIZE 55 56 /* USB */ 57 #define CONFIG_USB_ATMEL 58 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 59 #define CONFIG_USB_OHCI_NEW 60 #define CONFIG_SYS_USB_OHCI_CPU_INIT 61 #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE 62 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" 63 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 64 65 /* GPIOs and IO expander */ 66 #define CONFIG_ATMEL_LEGACY 67 #define CONFIG_AT91_GPIO 68 #define CONFIG_AT91_GPIO_PULLUP 1 69 #define CONFIG_PCA953X 70 #define CONFIG_SYS_I2C_PCA953X_ADDR 0x28 71 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} } 72 73 /* UARTs/Serial console */ 74 #define CONFIG_ATMEL_USART 75 #ifndef CONFIG_DM_SERIAL 76 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 77 #define CONFIG_USART_ID ATMEL_ID_SYS 78 #endif 79 80 /* I2C - Bit-bashed */ 81 #define CONFIG_SYS_I2C 82 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 83 #define CONFIG_SYS_I2C_SOFT_SPEED 100000 84 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F 85 #define CONFIG_SOFT_I2C_READ_REPEATED_START 86 #define I2C_INIT do { \ 87 at91_set_gpio_output(AT91_PIN_PA23, 1); \ 88 at91_set_gpio_output(AT91_PIN_PA24, 1); \ 89 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \ 90 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \ 91 } while (0) 92 #define I2C_SOFT_DECLARATIONS 93 #define I2C_ACTIVE 94 #define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PA23, 1); 95 #define I2C_READ at91_get_gpio_value(AT91_PIN_PA23); 96 #define I2C_SDA(bit) do { \ 97 if (bit) { \ 98 at91_set_gpio_input(AT91_PIN_PA23, 1); \ 99 } else { \ 100 at91_set_gpio_output(AT91_PIN_PA23, 1); \ 101 at91_set_gpio_value(AT91_PIN_PA23, bit); \ 102 } \ 103 } while (0) 104 #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) 105 #define I2C_DELAY udelay(2) 106 107 /* Boot options */ 108 #define CONFIG_SYS_LOAD_ADDR 0x23000000 109 110 #define CONFIG_BOOTP_BOOTFILESIZE 111 112 /* Environment settings */ 113 #define CONFIG_ENV_OVERWRITE 114 115 /* Console settings */ 116 117 /* U-Boot memory settings */ 118 #define CONFIG_SYS_MALLOC_LEN (1 << 20) 119 120 #endif /* __CONFIG_H */ 121