1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2012 Altera Corporation <www.altera.com> 4 */ 5 #ifndef __CONFIG_SOCFPGA_COMMON_H__ 6 #define __CONFIG_SOCFPGA_COMMON_H__ 7 8 /* 9 * High level configuration 10 */ 11 #define CONFIG_CLOCKS 12 13 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 14 15 /* 16 * Memory configurations 17 */ 18 #define PHYS_SDRAM_1 0x0 19 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 20 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 21 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 22 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 23 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 24 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 25 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 26 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 27 /* SPL memory allocation configuration, this is for FAT implementation */ 28 #ifndef CONFIG_SYS_SPL_MALLOC_SIZE 29 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000 30 #endif 31 #define CONFIG_SYS_INIT_RAM_SIZE (0x40000 - CONFIG_SYS_SPL_MALLOC_SIZE) 32 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \ 33 CONFIG_SYS_INIT_RAM_SIZE) 34 #endif 35 36 /* 37 * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal 38 * SRAM as bootcounter storage. Make sure to not put the stack directly 39 * at this address to not overwrite the bootcounter by checking, if the 40 * bootcounter address is located in the internal SRAM. 41 */ 42 #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \ 43 (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \ 44 CONFIG_SYS_INIT_RAM_SIZE))) 45 #define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR 46 #else 47 #define CONFIG_SPL_STACK \ 48 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 49 #endif 50 51 /* 52 * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc 53 * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage 54 * in U-Boot pre-reloc is higher than in SPL. 55 */ 56 #if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR 57 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR 58 #else 59 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK 60 #endif 61 62 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 63 64 /* 65 * U-Boot general configurations 66 */ 67 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 68 /* Print buffer size */ 69 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 70 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 71 /* Boot argument buffer size */ 72 73 /* 74 * Cache 75 */ 76 #define CONFIG_SYS_L2_PL310 77 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 78 79 /* 80 * Ethernet on SoC (EMAC) 81 */ 82 #ifdef CONFIG_CMD_NET 83 #define CONFIG_DW_ALTDESCRIPTOR 84 #endif 85 86 /* 87 * FPGA Driver 88 */ 89 #ifdef CONFIG_CMD_FPGA 90 #define CONFIG_FPGA_COUNT 1 91 #endif 92 93 /* 94 * L4 OSC1 Timer 0 95 */ 96 #ifndef CONFIG_TIMER 97 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 98 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 99 #define CONFIG_SYS_TIMER_COUNTS_DOWN 100 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 101 #define CONFIG_SYS_TIMER_RATE 25000000 102 #endif 103 104 /* 105 * L4 Watchdog 106 */ 107 #ifdef CONFIG_HW_WATCHDOG 108 #define CONFIG_DESIGNWARE_WATCHDOG 109 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 110 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 111 #endif 112 113 /* 114 * MMC Driver 115 */ 116 #ifdef CONFIG_CMD_MMC 117 /* FIXME */ 118 /* using smaller max blk cnt to avoid flooding the limited stack we have */ 119 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 120 #endif 121 122 /* 123 * NAND Support 124 */ 125 #ifdef CONFIG_NAND_DENALI 126 #define CONFIG_SYS_MAX_NAND_DEVICE 1 127 #define CONFIG_SYS_NAND_ONFI_DETECTION 128 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS 129 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS 130 #endif 131 132 /* 133 * QSPI support 134 */ 135 /* QSPI reference clock */ 136 #ifndef __ASSEMBLY__ 137 unsigned int cm_get_qspi_controller_clk_hz(void); 138 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 139 #endif 140 141 /* 142 * USB 143 */ 144 145 /* 146 * USB Gadget (DFU, UMS) 147 */ 148 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 149 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) 150 #define DFU_DEFAULT_POLL_TIMEOUT 300 151 152 /* USB IDs */ 153 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 154 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 155 #endif 156 157 /* 158 * U-Boot environment 159 */ 160 161 /* Environment for SDMMC boot */ 162 #if defined(CONFIG_ENV_IS_IN_MMC) 163 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ 164 #endif 165 166 /* Environment for QSPI boot */ 167 168 /* 169 * SPL 170 * 171 * SRAM Memory layout for gen 5: 172 * 173 * 0xFFFF_0000 ...... Start of SRAM 174 * 0xFFFF_xxxx ...... Top of stack (grows down) 175 * 0xFFFF_yyyy ...... Global Data 176 * 0xFFFF_zzzz ...... Malloc area 177 * 0xFFFF_FFFF ...... End of SRAM 178 * 179 * SRAM Memory layout for Arria 10: 180 * 0xFFE0_0000 ...... Start of SRAM (bottom) 181 * 0xFFEx_xxxx ...... Top of stack (grows down to bottom) 182 * 0xFFEy_yyyy ...... Global Data 183 * 0xFFEz_zzzz ...... Malloc area (grows up to top) 184 * 0xFFE3_FFFF ...... End of SRAM (top) 185 */ 186 #ifndef CONFIG_SPL_TEXT_BASE 187 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE 188 #endif 189 190 /* SPL SDMMC boot support */ 191 #ifdef CONFIG_SPL_MMC_SUPPORT 192 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) 193 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 194 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 195 #endif 196 #else 197 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 198 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 199 #endif 200 #endif 201 202 /* SPL QSPI boot support */ 203 204 /* SPL NAND boot support */ 205 #ifdef CONFIG_SPL_NAND_SUPPORT 206 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 207 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 208 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 209 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000 210 #endif 211 #endif 212 213 /* Extra Environment */ 214 #ifndef CONFIG_SPL_BUILD 215 216 #ifdef CONFIG_CMD_DHCP 217 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) 218 #else 219 #define BOOT_TARGET_DEVICES_DHCP(func) 220 #endif 221 222 #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) 223 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) 224 #else 225 #define BOOT_TARGET_DEVICES_PXE(func) 226 #endif 227 228 #ifdef CONFIG_CMD_MMC 229 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) 230 #else 231 #define BOOT_TARGET_DEVICES_MMC(func) 232 #endif 233 234 #define BOOT_TARGET_DEVICES(func) \ 235 BOOT_TARGET_DEVICES_MMC(func) \ 236 BOOT_TARGET_DEVICES_PXE(func) \ 237 BOOT_TARGET_DEVICES_DHCP(func) 238 239 #include <config_distro_bootcmd.h> 240 241 #ifndef CONFIG_EXTRA_ENV_SETTINGS 242 #define CONFIG_EXTRA_ENV_SETTINGS \ 243 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ 244 "bootm_size=0xa000000\0" \ 245 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ 246 "fdt_addr_r=0x02000000\0" \ 247 "scriptaddr=0x02100000\0" \ 248 "pxefile_addr_r=0x02200000\0" \ 249 "ramdisk_addr_r=0x02300000\0" \ 250 "socfpga_legacy_reset_compat=1\0" \ 251 BOOTENV 252 253 #endif 254 #endif 255 256 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ 257