1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu> 4 * (C) Copyright 2013 - 2018 Xilinx, Inc. 5 * 6 * Common configuration options for all Zynq boards. 7 */ 8 9 #ifndef __CONFIG_ZYNQ_COMMON_H 10 #define __CONFIG_ZYNQ_COMMON_H 11 12 /* CPU clock */ 13 #ifndef CONFIG_CPU_FREQ_HZ 14 # define CONFIG_CPU_FREQ_HZ 800000000 15 #endif 16 17 #define CONFIG_REMAKE_ELF 18 19 /* Cache options */ 20 #define CONFIG_SYS_L2CACHE_OFF 21 #ifndef CONFIG_SYS_L2CACHE_OFF 22 # define CONFIG_SYS_L2_PL310 23 # define CONFIG_SYS_PL310_BASE 0xf8f02000 24 #endif 25 26 #define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600 27 #define CONFIG_SYS_TIMERBASE ZYNQ_SCUTIMER_BASEADDR 28 #define CONFIG_SYS_TIMER_COUNTS_DOWN 29 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 30 31 /* Serial drivers */ 32 /* The following table includes the supported baudrates */ 33 #define CONFIG_SYS_BAUDRATE_TABLE \ 34 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} 35 36 #define CONFIG_ARM_DCC 37 38 /* Ethernet driver */ 39 #if defined(CONFIG_ZYNQ_GEM) 40 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 41 # define CONFIG_BOOTP_MAY_FAIL 42 #endif 43 44 /* QSPI */ 45 46 /* NOR */ 47 #ifdef CONFIG_MTD_NOR_FLASH 48 # define CONFIG_SYS_FLASH_BASE 0xE2000000 49 # define CONFIG_SYS_FLASH_SIZE (16 * 1024 * 1024) 50 # define CONFIG_SYS_MAX_FLASH_BANKS 1 51 # define CONFIG_SYS_MAX_FLASH_SECT 512 52 # define CONFIG_SYS_FLASH_ERASE_TOUT 1000 53 # define CONFIG_SYS_FLASH_WRITE_TOUT 5000 54 # define CONFIG_FLASH_SHOW_PROGRESS 10 55 # undef CONFIG_SYS_FLASH_EMPTY_INFO 56 #endif 57 58 #ifdef CONFIG_NAND_ZYNQ 59 #define CONFIG_SYS_MAX_NAND_DEVICE 1 60 #define CONFIG_SYS_NAND_ONFI_DETECTION 61 #endif 62 63 #ifdef CONFIG_USB_EHCI_ZYNQ 64 # define CONFIG_EHCI_IS_TDI 65 66 # define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x600000 67 # define DFU_DEFAULT_POLL_TIMEOUT 300 68 # define CONFIG_THOR_RESET_OFF 69 # define DFU_ALT_INFO_RAM \ 70 "dfu_ram_info=" \ 71 "setenv dfu_alt_info " \ 72 "${kernel_image} ram 0x3000000 0x500000\\\\;" \ 73 "${devicetree_image} ram 0x2A00000 0x20000\\\\;" \ 74 "${ramdisk_image} ram 0x2000000 0x600000\0" \ 75 "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \ 76 "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" 77 78 # if defined(CONFIG_MMC_SDHCI_ZYNQ) 79 # define DFU_ALT_INFO_MMC \ 80 "dfu_mmc_info=" \ 81 "setenv dfu_alt_info " \ 82 "${kernel_image} fat 0 1\\\\;" \ 83 "${devicetree_image} fat 0 1\\\\;" \ 84 "${ramdisk_image} fat 0 1\0" \ 85 "dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \ 86 "thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0" 87 88 # define DFU_ALT_INFO \ 89 DFU_ALT_INFO_RAM \ 90 DFU_ALT_INFO_MMC 91 # else 92 # define DFU_ALT_INFO \ 93 DFU_ALT_INFO_RAM 94 # endif 95 #endif 96 97 #if !defined(DFU_ALT_INFO) 98 # define DFU_ALT_INFO 99 #endif 100 101 /* Allow to overwrite serial and ethaddr */ 102 #define CONFIG_ENV_OVERWRITE 103 104 /* enable preboot to be loaded before CONFIG_BOOTDELAY */ 105 106 /* Boot configuration */ 107 #define CONFIG_SYS_LOAD_ADDR 0 /* default? */ 108 109 #ifdef CONFIG_SPL_BUILD 110 #define BOOTENV 111 #else 112 113 #ifdef CONFIG_CMD_MMC 114 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) 115 #else 116 #define BOOT_TARGET_DEVICES_MMC(func) 117 #endif 118 119 #ifdef CONFIG_CMD_USB 120 #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) func(USB, usb, 1) 121 #else 122 #define BOOT_TARGET_DEVICES_USB(func) 123 #endif 124 125 #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) 126 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) 127 #else 128 #define BOOT_TARGET_DEVICES_PXE(func) 129 #endif 130 131 #if defined(CONFIG_CMD_DHCP) 132 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) 133 #else 134 #define BOOT_TARGET_DEVICES_DHCP(func) 135 #endif 136 137 #if defined(CONFIG_ZYNQ_QSPI) 138 # define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na) 139 #else 140 # define BOOT_TARGET_DEVICES_QSPI(func) 141 #endif 142 143 #if defined(CONFIG_NAND_ZYNQ) 144 # define BOOT_TARGET_DEVICES_NAND(func) func(NAND, nand, na) 145 #else 146 # define BOOT_TARGET_DEVICES_NAND(func) 147 #endif 148 149 #if defined(CONFIG_MTD_NOR_FLASH) 150 # define BOOT_TARGET_DEVICES_NOR(func) func(NOR, nor, na) 151 #else 152 # define BOOT_TARGET_DEVICES_NOR(func) 153 #endif 154 155 #define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ 156 "bootcmd_qspi=sf probe 0 0 0 && " \ 157 "sf read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \ 158 "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" 159 160 #define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ 161 "qspi " 162 163 #define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ 164 "bootcmd_nand=nand info && " \ 165 "nand read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \ 166 "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" 167 168 #define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ 169 "nand " 170 171 #define BOOTENV_DEV_NOR(devtypeu, devtypel, instance) \ 172 "script_offset_nor=0xE2FC0000\0" \ 173 "bootcmd_nor=cp.b ${script_offset_nor} ${scriptaddr} ${script_size_f} && " \ 174 "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" 175 176 #define BOOTENV_DEV_NAME_NOR(devtypeu, devtypel, instance) \ 177 "nor " 178 179 #define BOOT_TARGET_DEVICES(func) \ 180 BOOT_TARGET_DEVICES_MMC(func) \ 181 BOOT_TARGET_DEVICES_QSPI(func) \ 182 BOOT_TARGET_DEVICES_NAND(func) \ 183 BOOT_TARGET_DEVICES_NOR(func) \ 184 BOOT_TARGET_DEVICES_USB(func) \ 185 BOOT_TARGET_DEVICES_PXE(func) \ 186 BOOT_TARGET_DEVICES_DHCP(func) 187 188 #include <config_distro_bootcmd.h> 189 #endif /* CONFIG_SPL_BUILD */ 190 191 /* Default environment */ 192 #ifndef CONFIG_EXTRA_ENV_SETTINGS 193 #define CONFIG_EXTRA_ENV_SETTINGS \ 194 "fdt_high=0x20000000\0" \ 195 "initrd_high=0x20000000\0" \ 196 "scriptaddr=0x20000\0" \ 197 "script_offset_f=0xFC0000\0" \ 198 "script_size_f=0x40000\0" \ 199 "fdt_addr_r=0x1f00000\0" \ 200 "pxefile_addr_r=0x2000000\0" \ 201 "kernel_addr_r=0x2000000\0" \ 202 "scriptaddr=0x3000000\0" \ 203 "ramdisk_addr_r=0x3100000\0" \ 204 DFU_ALT_INFO \ 205 BOOTENV 206 #endif 207 208 /* Miscellaneous configurable options */ 209 210 #define CONFIG_CLOCKS 211 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 212 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ 213 214 #define CONFIG_SYS_MEMTEST_START 0 215 #define CONFIG_SYS_MEMTEST_END 0x1000 216 217 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 218 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 219 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 220 CONFIG_SYS_INIT_RAM_SIZE - \ 221 GENERATED_GBL_DATA_SIZE) 222 223 224 /* Extend size of kernel image for uncompression */ 225 #define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) 226 227 /* Boot FreeBSD/vxWorks from an ELF image */ 228 #define CONFIG_SYS_MMC_MAX_DEVICE 1 229 230 /* MMC support */ 231 #ifdef CONFIG_MMC_SDHCI_ZYNQ 232 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 233 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 234 #endif 235 236 /* Address in RAM where the parameters must be copied by SPL. */ 237 #define CONFIG_SYS_SPL_ARGS_ADDR 0x10000000 238 239 #define CONFIG_SPL_FS_LOAD_ARGS_NAME "system.dtb" 240 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" 241 242 /* Not using MMC raw mode - just for compilation purpose */ 243 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 244 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 245 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0 246 247 /* qspi mode is working fine */ 248 #ifdef CONFIG_ZYNQ_QSPI 249 #define CONFIG_SYS_SPI_ARGS_OFFS 0x200000 250 #define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 251 #define CONFIG_SYS_SPI_KERNEL_OFFS (CONFIG_SYS_SPI_ARGS_OFFS + \ 252 CONFIG_SYS_SPI_ARGS_SIZE) 253 #endif 254 255 /* SP location before relocation, must use scratch RAM */ 256 257 /* 3 * 64kB blocks of OCM - one is on the top because of bootrom */ 258 #define CONFIG_SPL_MAX_SIZE 0x30000 259 260 /* On the top of OCM space */ 261 #define CONFIG_SYS_SPL_MALLOC_START CONFIG_SPL_STACK_R_ADDR 262 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000000 263 264 /* 265 * SPL stack position - and stack goes down 266 * 0xfffffe00 is used for putting wfi loop. 267 * Set it up as limit for now. 268 */ 269 #define CONFIG_SPL_STACK 0xfffffe00 270 271 /* BSS setup */ 272 #define CONFIG_SPL_BSS_START_ADDR 0x100000 273 #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 274 275 #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x10000000 276 277 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE 278 279 #endif /* __CONFIG_ZYNQ_COMMON_H */ 280