1 // Copyright 2006-2009 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4
5 // CPU specific code for arm independent of OS goes here.
6 #ifdef __arm__
7 #ifdef __QNXNTO__
8 #include <sys/mman.h> // for cache flushing.
9 #undef MAP_TYPE // NOLINT
10 #elif V8_OS_FREEBSD
11 #include <machine/sysarch.h> // for cache flushing
12 #include <sys/types.h>
13 #else
14 #include <sys/syscall.h> // for cache flushing.
15 #endif
16 #endif
17
18 #if V8_TARGET_ARCH_ARM
19
20 #include "src/codegen/cpu-features.h"
21
22 namespace v8 {
23 namespace internal {
24
25 // The inlining of this seems to trigger an LTO bug that clobbers a register,
26 // see https://crbug.com/952759 and https://bugs.llvm.org/show_bug.cgi?id=41575.
FlushICache(void * start,size_t size)27 V8_NOINLINE void CpuFeatures::FlushICache(void* start, size_t size) {
28 #if !defined(USE_SIMULATOR)
29 #if V8_OS_QNX
30 msync(start, size, MS_SYNC | MS_INVALIDATE_ICACHE);
31 #elif V8_OS_FREEBSD
32 struct arm_sync_icache_args args = {
33 .addr = reinterpret_cast<uintptr_t>(start), .len = size};
34 sysarch(ARM_SYNC_ICACHE, reinterpret_cast<void*>(&args));
35 #else
36 register uint32_t beg asm("r0") = reinterpret_cast<uint32_t>(start);
37 register uint32_t end asm("r1") = beg + size;
38 register uint32_t flg asm("r2") = 0;
39
40 asm volatile(
41 // This assembly works for both ARM and Thumb targets.
42
43 // Preserve r7; it is callee-saved, and GCC uses it as a frame pointer for
44 // Thumb targets.
45 " push {r7}\n"
46 // r0 = beg
47 // r1 = end
48 // r2 = flags (0)
49 " ldr r7, =%c[scno]\n" // r7 = syscall number
50 " svc 0\n"
51
52 " pop {r7}\n"
53 :
54 : "r"(beg), "r"(end), "r"(flg), [scno] "i"(__ARM_NR_cacheflush)
55 : "memory");
56 #endif
57 #endif // !USE_SIMULATOR
58 }
59
60 } // namespace internal
61 } // namespace v8
62
63 #endif // V8_TARGET_ARCH_ARM
64