1 // Copyright 2012 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_CODEGEN_X64_SSE_INSTR_H_ 6 #define V8_CODEGEN_X64_SSE_INSTR_H_ 7 8 // SSE instructions whose AVX version has two operands. 9 #define SSE_UNOP_INSTRUCTION_LIST(V) \ 10 V(sqrtps, 0F, 51) \ 11 V(rsqrtps, 0F, 52) \ 12 V(rcpps, 0F, 53) \ 13 V(cvtdq2ps, 0F, 5B) 14 15 // SSE instructions whose AVX version has three operands. 16 #define SSE_BINOP_INSTRUCTION_LIST(V) \ 17 V(andps, 0F, 54) \ 18 V(andnps, 0F, 55) \ 19 V(orps, 0F, 56) \ 20 V(xorps, 0F, 57) \ 21 V(addps, 0F, 58) \ 22 V(mulps, 0F, 59) \ 23 V(subps, 0F, 5C) \ 24 V(minps, 0F, 5D) \ 25 V(divps, 0F, 5E) \ 26 V(maxps, 0F, 5F) 27 28 // Instructions dealing with scalar single-precision values. 29 #define SSE_INSTRUCTION_LIST_SS(V) \ 30 V(sqrtss, F3, 0F, 51) \ 31 V(addss, F3, 0F, 58) \ 32 V(mulss, F3, 0F, 59) \ 33 V(subss, F3, 0F, 5C) \ 34 V(minss, F3, 0F, 5D) \ 35 V(divss, F3, 0F, 5E) \ 36 V(maxss, F3, 0F, 5F) 37 38 #define SSE2_INSTRUCTION_LIST(V) \ 39 V(andpd, 66, 0F, 54) \ 40 V(andnpd, 66, 0F, 55) \ 41 V(orpd, 66, 0F, 56) \ 42 V(xorpd, 66, 0F, 57) \ 43 V(addpd, 66, 0F, 58) \ 44 V(mulpd, 66, 0F, 59) \ 45 V(subpd, 66, 0F, 5C) \ 46 V(minpd, 66, 0F, 5D) \ 47 V(maxpd, 66, 0F, 5F) \ 48 V(divpd, 66, 0F, 5E) \ 49 V(punpcklbw, 66, 0F, 60) \ 50 V(punpcklwd, 66, 0F, 61) \ 51 V(punpckldq, 66, 0F, 62) \ 52 V(packsswb, 66, 0F, 63) \ 53 V(packuswb, 66, 0F, 67) \ 54 V(punpckhbw, 66, 0F, 68) \ 55 V(punpckhwd, 66, 0F, 69) \ 56 V(punpckhdq, 66, 0F, 6A) \ 57 V(packssdw, 66, 0F, 6B) \ 58 V(punpcklqdq, 66, 0F, 6C) \ 59 V(punpckhqdq, 66, 0F, 6D) \ 60 V(pmaddwd, 66, 0F, F5) \ 61 V(paddb, 66, 0F, FC) \ 62 V(paddw, 66, 0F, FD) \ 63 V(paddd, 66, 0F, FE) \ 64 V(paddq, 66, 0F, D4) \ 65 V(paddsb, 66, 0F, EC) \ 66 V(paddsw, 66, 0F, ED) \ 67 V(paddusb, 66, 0F, DC) \ 68 V(paddusw, 66, 0F, DD) \ 69 V(pcmpeqb, 66, 0F, 74) \ 70 V(pcmpeqw, 66, 0F, 75) \ 71 V(pcmpeqd, 66, 0F, 76) \ 72 V(pcmpgtb, 66, 0F, 64) \ 73 V(pcmpgtw, 66, 0F, 65) \ 74 V(pcmpgtd, 66, 0F, 66) \ 75 V(pmaxsw, 66, 0F, EE) \ 76 V(pmaxub, 66, 0F, DE) \ 77 V(pminsw, 66, 0F, EA) \ 78 V(pminub, 66, 0F, DA) \ 79 V(pmullw, 66, 0F, D5) \ 80 V(pmuludq, 66, 0F, F4) \ 81 V(psllw, 66, 0F, F1) \ 82 V(pslld, 66, 0F, F2) \ 83 V(psllq, 66, 0F, F3) \ 84 V(pavgb, 66, 0F, E0) \ 85 V(psraw, 66, 0F, E1) \ 86 V(psrad, 66, 0F, E2) \ 87 V(pavgw, 66, 0F, E3) \ 88 V(psrlw, 66, 0F, D1) \ 89 V(psrld, 66, 0F, D2) \ 90 V(psrlq, 66, 0F, D3) \ 91 V(psubb, 66, 0F, F8) \ 92 V(psubw, 66, 0F, F9) \ 93 V(psubd, 66, 0F, FA) \ 94 V(psubq, 66, 0F, FB) \ 95 V(psubsb, 66, 0F, E8) \ 96 V(psubsw, 66, 0F, E9) \ 97 V(psubusb, 66, 0F, D8) \ 98 V(psubusw, 66, 0F, D9) \ 99 V(pand, 66, 0F, DB) \ 100 V(por, 66, 0F, EB) \ 101 V(pxor, 66, 0F, EF) 102 103 // SSE2 instructions whose AVX version has two operands. 104 #define SSE2_UNOP_INSTRUCTION_LIST(V) \ 105 V(sqrtpd, 66, 0F, 51) \ 106 V(cvtps2dq, 66, 0F, 5B) 107 108 // SSE2 shift instructions with an immediate operand. The last element is the 109 // extension to the opcode. 110 #define SSE2_INSTRUCTION_LIST_SHIFT_IMM(V) \ 111 V(psrlw, 66, 0F, 71, 2) \ 112 V(psrld, 66, 0F, 72, 2) \ 113 V(psrlq, 66, 0F, 73, 2) \ 114 V(psraw, 66, 0F, 71, 4) \ 115 V(psrad, 66, 0F, 72, 4) \ 116 V(psllw, 66, 0F, 71, 6) \ 117 V(pslld, 66, 0F, 72, 6) \ 118 V(psllq, 66, 0F, 73, 6) 119 120 // Instructions dealing with scalar double-precision values. 121 #define SSE2_INSTRUCTION_LIST_SD(V) \ 122 V(sqrtsd, F2, 0F, 51) \ 123 V(addsd, F2, 0F, 58) \ 124 V(mulsd, F2, 0F, 59) \ 125 V(cvtsd2ss, F2, 0F, 5A) \ 126 V(subsd, F2, 0F, 5C) \ 127 V(minsd, F2, 0F, 5D) \ 128 V(divsd, F2, 0F, 5E) \ 129 V(maxsd, F2, 0F, 5F) 130 131 #define SSSE3_INSTRUCTION_LIST(V) \ 132 V(phaddd, 66, 0F, 38, 02) \ 133 V(phaddw, 66, 0F, 38, 01) \ 134 V(pshufb, 66, 0F, 38, 00) \ 135 V(psignb, 66, 0F, 38, 08) \ 136 V(psignw, 66, 0F, 38, 09) \ 137 V(psignd, 66, 0F, 38, 0A) 138 139 // SSSE3 instructions whose AVX version has two operands. 140 #define SSSE3_UNOP_INSTRUCTION_LIST(V) \ 141 V(pabsb, 66, 0F, 38, 1C) \ 142 V(pabsw, 66, 0F, 38, 1D) \ 143 V(pabsd, 66, 0F, 38, 1E) 144 145 #define SSE4_INSTRUCTION_LIST(V) \ 146 V(pcmpeqq, 66, 0F, 38, 29) \ 147 V(packusdw, 66, 0F, 38, 2B) \ 148 V(pminsb, 66, 0F, 38, 38) \ 149 V(pminsd, 66, 0F, 38, 39) \ 150 V(pminuw, 66, 0F, 38, 3A) \ 151 V(pminud, 66, 0F, 38, 3B) \ 152 V(pmaxsb, 66, 0F, 38, 3C) \ 153 V(pmaxsd, 66, 0F, 38, 3D) \ 154 V(pmaxuw, 66, 0F, 38, 3E) \ 155 V(pmaxud, 66, 0F, 38, 3F) \ 156 V(pmulld, 66, 0F, 38, 40) 157 158 // SSE instructions whose AVX version has two operands. 159 #define SSE4_UNOP_INSTRUCTION_LIST(V) \ 160 V(ptest, 66, 0F, 38, 17) \ 161 V(pmovsxbw, 66, 0F, 38, 20) \ 162 V(pmovsxwd, 66, 0F, 38, 23) \ 163 V(pmovsxdq, 66, 0F, 38, 25) \ 164 V(pmovzxbw, 66, 0F, 38, 30) \ 165 V(pmovzxwd, 66, 0F, 38, 33) \ 166 V(pmovzxdq, 66, 0F, 38, 35) 167 168 #define SSE4_EXTRACT_INSTRUCTION_LIST(V) \ 169 V(extractps, 66, 0F, 3A, 17) \ 170 V(pextrb, 66, 0F, 3A, 14) \ 171 V(pextrw, 66, 0F, 3A, 15) \ 172 V(pextrd, 66, 0F, 3A, 16) 173 174 #define SSE4_2_INSTRUCTION_LIST(V) V(pcmpgtq, 66, 0F, 38, 37) 175 176 #endif // V8_CODEGEN_X64_SSE_INSTR_H_ 177