1 // Copyright 2014, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 #ifndef VIXL_CPU_AARCH64_H 28 #define VIXL_CPU_AARCH64_H 29 30 #include "../cpu-features.h" 31 #include "../globals-vixl.h" 32 33 #include "instructions-aarch64.h" 34 35 #ifndef VIXL_INCLUDE_TARGET_AARCH64 36 // The supporting .cc file is only compiled when the A64 target is selected. 37 // Throw an explicit error now to avoid a harder-to-debug linker error later. 38 // 39 // These helpers _could_ work on any AArch64 host, even when generating AArch32 40 // code, but we don't support this because the available features may differ 41 // between AArch32 and AArch64 on the same platform, so basing AArch32 code 42 // generation on aarch64::CPU features is probably broken. 43 #error cpu-aarch64.h requires VIXL_INCLUDE_TARGET_AARCH64 (scons target=a64). 44 #endif 45 46 namespace vixl { 47 namespace aarch64 { 48 49 // A CPU ID register, for use with CPUFeatures::kIDRegisterEmulation. Fields 50 // specific to each register are described in relevant subclasses. 51 class IDRegister { 52 protected: value_(value)53 explicit IDRegister(uint64_t value = 0) : value_(value) {} 54 55 class Field { 56 public: 57 enum Type { kUnsigned, kSigned }; 58 lsb_(lsb)59 explicit Field(int lsb, Type type = kUnsigned) : lsb_(lsb), type_(type) {} 60 61 static const int kMaxWidthInBits = 4; 62 GetWidthInBits()63 int GetWidthInBits() const { 64 // All current ID fields have four bits. 65 return kMaxWidthInBits; 66 } GetLsb()67 int GetLsb() const { return lsb_; } GetMsb()68 int GetMsb() const { return lsb_ + GetWidthInBits() - 1; } GetType()69 Type GetType() const { return type_; } 70 71 private: 72 int lsb_; 73 Type type_; 74 }; 75 76 public: 77 // Extract the specified field, performing sign-extension for signed fields. 78 // This allows us to implement the 'value >= number' detection mechanism 79 // recommended by the Arm ARM, for both signed and unsigned fields. 80 int Get(Field field) const; 81 82 private: 83 uint64_t value_; 84 }; 85 86 class AA64PFR0 : public IDRegister { 87 public: AA64PFR0(uint64_t value)88 explicit AA64PFR0(uint64_t value) : IDRegister(value) {} 89 90 CPUFeatures GetCPUFeatures() const; 91 92 private: 93 static const Field kFP; 94 static const Field kAdvSIMD; 95 static const Field kSVE; 96 static const Field kDIT; 97 }; 98 99 class AA64PFR1 : public IDRegister { 100 public: AA64PFR1(uint64_t value)101 explicit AA64PFR1(uint64_t value) : IDRegister(value) {} 102 103 CPUFeatures GetCPUFeatures() const; 104 105 private: 106 static const Field kBT; 107 }; 108 109 class AA64ISAR0 : public IDRegister { 110 public: AA64ISAR0(uint64_t value)111 explicit AA64ISAR0(uint64_t value) : IDRegister(value) {} 112 113 CPUFeatures GetCPUFeatures() const; 114 115 private: 116 static const Field kAES; 117 static const Field kSHA1; 118 static const Field kSHA2; 119 static const Field kCRC32; 120 static const Field kAtomic; 121 static const Field kRDM; 122 static const Field kSHA3; 123 static const Field kSM3; 124 static const Field kSM4; 125 static const Field kDP; 126 static const Field kFHM; 127 static const Field kTS; 128 }; 129 130 class AA64ISAR1 : public IDRegister { 131 public: AA64ISAR1(uint64_t value)132 explicit AA64ISAR1(uint64_t value) : IDRegister(value) {} 133 134 CPUFeatures GetCPUFeatures() const; 135 136 private: 137 static const Field kDPB; 138 static const Field kAPA; 139 static const Field kAPI; 140 static const Field kJSCVT; 141 static const Field kFCMA; 142 static const Field kLRCPC; 143 static const Field kGPA; 144 static const Field kGPI; 145 static const Field kFRINTTS; 146 static const Field kSB; 147 static const Field kSPECRES; 148 }; 149 150 class AA64MMFR1 : public IDRegister { 151 public: AA64MMFR1(uint64_t value)152 explicit AA64MMFR1(uint64_t value) : IDRegister(value) {} 153 154 CPUFeatures GetCPUFeatures() const; 155 156 private: 157 static const Field kLO; 158 }; 159 160 class CPU { 161 public: 162 // Initialise CPU support. 163 static void SetUp(); 164 165 // Ensures the data at a given address and with a given size is the same for 166 // the I and D caches. I and D caches are not automatically coherent on ARM 167 // so this operation is required before any dynamically generated code can 168 // safely run. 169 static void EnsureIAndDCacheCoherency(void *address, size_t length); 170 171 // Read and interpret the ID registers. This requires 172 // CPUFeatures::kIDRegisterEmulation, and therefore cannot be called on 173 // non-AArch64 platforms. 174 static CPUFeatures InferCPUFeaturesFromIDRegisters(); 175 176 // Read and interpret CPUFeatures reported by the OS. Failed queries (or 177 // unsupported platforms) return an empty list. Note that this is 178 // indistinguishable from a successful query on a platform that advertises no 179 // features. 180 // 181 // Non-AArch64 hosts are considered to be unsupported platforms, and this 182 // function returns an empty list. 183 static CPUFeatures InferCPUFeaturesFromOS( 184 CPUFeatures::QueryIDRegistersOption option = 185 CPUFeatures::kQueryIDRegistersIfAvailable); 186 187 // Handle tagged pointers. 188 template <typename T> SetPointerTag(T pointer,uint64_t tag)189 static T SetPointerTag(T pointer, uint64_t tag) { 190 VIXL_ASSERT(IsUintN(kAddressTagWidth, tag)); 191 192 // Use C-style casts to get static_cast behaviour for integral types (T), 193 // and reinterpret_cast behaviour for other types. 194 195 uint64_t raw = (uint64_t)pointer; 196 VIXL_STATIC_ASSERT(sizeof(pointer) == sizeof(raw)); 197 198 raw = (raw & ~kAddressTagMask) | (tag << kAddressTagOffset); 199 return (T)raw; 200 } 201 202 template <typename T> GetPointerTag(T pointer)203 static uint64_t GetPointerTag(T pointer) { 204 // Use C-style casts to get static_cast behaviour for integral types (T), 205 // and reinterpret_cast behaviour for other types. 206 207 uint64_t raw = (uint64_t)pointer; 208 VIXL_STATIC_ASSERT(sizeof(pointer) == sizeof(raw)); 209 210 return (raw & kAddressTagMask) >> kAddressTagOffset; 211 } 212 213 private: 214 #define VIXL_AARCH64_ID_REG_LIST(V) \ 215 V(AA64PFR0) \ 216 V(AA64PFR1) \ 217 V(AA64ISAR0) \ 218 V(AA64ISAR1) \ 219 V(AA64MMFR1) 220 221 #define VIXL_READ_ID_REG(NAME) static NAME Read##NAME(); 222 // On native AArch64 platforms, read the named CPU ID registers. These require 223 // CPUFeatures::kIDRegisterEmulation, and should not be called on non-AArch64 224 // platforms. 225 VIXL_AARCH64_ID_REG_LIST(VIXL_READ_ID_REG) 226 #undef VIXL_READ_ID_REG 227 228 // Return the content of the cache type register. 229 static uint32_t GetCacheType(); 230 231 // I and D cache line size in bytes. 232 static unsigned icache_line_size_; 233 static unsigned dcache_line_size_; 234 }; 235 236 } // namespace aarch64 237 } // namespace vixl 238 239 #endif // VIXL_CPU_AARCH64_H 240