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1 /*
2 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met:
7 *   * Redistributions of source code must retain the above copyright
8 *     notice, this list of conditions and the following disclaimer.
9 *   * Redistributions in binary form must reproduce the above
10 *     copyright notice, this list of conditions and the following
11 *     disclaimer in the documentation and/or other materials provided
12 *     with the distribution.
13 *   * Neither the name of The Linux Foundation nor the names of its
14 *     contributors may be used to endorse or promote products derived
15 *     from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
20 * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
24 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
25 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
26 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
27 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29 
30 #ifndef __DRM_INTERFACE_H__
31 #define __DRM_INTERFACE_H__
32 
33 #include <map>
34 #include <string>
35 #include <utility>
36 #include <vector>
37 #include <array>
38 
39 #include "xf86drm.h"
40 #include "xf86drmMode.h"
41 #include <drm/msm_drm.h>
42 #include <drm/msm_drm_pp.h>
43 
44 namespace sde_drm {
45 
46 typedef std::map<std::pair<uint32_t, uint64_t>, float> CompRatioMap;
47 
48 /*
49  * Drm Atomic Operation Codes
50  */
51 enum struct DRMOps {
52   /*
53    * Op: Sets plane source crop
54    * Arg: uint32_t - Plane ID
55    *      DRMRect  - Source Rectangle
56    */
57   PLANE_SET_SRC_RECT,
58   /*
59    * Op: Sets plane destination rect
60    * Arg: uint32_t - Plane ID
61    *      DRMRect - Dst Rectangle
62    */
63   PLANE_SET_DST_RECT,
64   /*
65    * Op: Sets plane exclusion rect
66    * Arg: uint32_t - Plane ID
67    *      drm_clip_rect - Exclusion Rectangle
68    */
69   PLANE_SET_EXCL_RECT,
70   /*
71    * Op: Sets plane zorder
72    * Arg: uint32_t - Plane ID
73    *      uint32_t - zorder
74    */
75   PLANE_SET_ZORDER,
76   /*
77    * Op: Sets plane rotation flags
78    * Arg: uint32_t - Plane ID
79    *      uint32_t - bit mask of rotation flags (See drm_mode.h for enums)
80    */
81   PLANE_SET_ROTATION,
82   /*
83    * Op: Sets plane alpha
84    * Arg: uint32_t - Plane ID
85    *      uint32_t - alpha value
86    */
87   PLANE_SET_ALPHA,
88   /*
89    * Op: Sets the blend type
90    * Arg: uint32_t - Plane ID
91    *      uint32_t - blend type (see DRMBlendType)
92    */
93   PLANE_SET_BLEND_TYPE,
94   /*
95    * Op: Sets horizontal decimation
96    * Arg: uint32_t - Plane ID
97    *      uint32_t - decimation factor
98    */
99   PLANE_SET_H_DECIMATION,
100   /*
101    * Op: Sets vertical decimation
102    * Arg: uint32_t - Plane ID
103    *      uint32_t - decimation factor
104    */
105   PLANE_SET_V_DECIMATION,
106   /*
107    * Op: Sets source config flags
108    * Arg: uint32_t - Plane ID
109    *      uint32_t - flags to enable or disable a specific op. E.g. deinterlacing
110    */
111   PLANE_SET_SRC_CONFIG,
112   /*
113    * Op: Sets frame buffer ID for plane. Set together with CRTC.
114    * Arg: uint32_t - Plane ID
115    *      uint32_t - Framebuffer ID
116    */
117   PLANE_SET_FB_ID,
118   /*
119    * Op: Sets the crtc for this plane. Set together with FB_ID.
120    * Arg: uint32_t - Plane ID
121    *      uint32_t - CRTC ID
122    */
123   PLANE_SET_CRTC,
124   /*
125    * Op: Sets acquire fence for this plane's buffer. Set together with FB_ID, CRTC.
126    * Arg: uint32_t - Plane ID
127    *      uint32_t - Input fence
128    */
129   PLANE_SET_INPUT_FENCE,
130   /*
131    * Op: Sets scaler config on this plane.
132    * Arg: uint32_t - Plane ID
133    *      uint64_t - Address of the scaler config object (version based)
134    */
135   PLANE_SET_SCALER_CONFIG,
136   /*
137    * Op: Sets FB Secure mode for this plane.
138    * Arg: uint32_t - Plane ID
139    *      uint32_t - Value of the FB Secure mode.
140    */
141   PLANE_SET_FB_SECURE_MODE,
142   /*
143    * Op: Sets csc config on this plane.
144    * Arg: uint32_t - Plane ID
145    *      uint32_t* - pointer to csc type
146    */
147   PLANE_SET_CSC_CONFIG,
148   /*
149    * Op: Sets multirect mode on this plane.
150    * Arg: uint32_t - Plane ID
151    *      uint32_t - multirect mode
152    */
153   PLANE_SET_MULTIRECT_MODE,
154   /*
155    * Op: Sets sspp layout on this plane.
156    * Arg: uint32_t - Plane ID
157    *      uint32_t - SSPP Layout Index
158    */
159   PLANE_SET_SSPP_LAYOUT,
160   /*
161    * Op: Sets rotator output frame buffer ID for plane.
162    * Arg: uint32_t - Plane ID
163    *      uint32_t - Framebuffer ID
164    */
165   PLANE_SET_ROT_FB_ID,
166   /*
167    * Op: Sets inverse pma mode on this plane.
168    * Arg: uint32_t - Plane ID
169    *      uint32_t - enable/disable inverse pma.
170    */
171   PLANE_SET_INVERSE_PMA,
172   /*
173    * Op: Sets csc config on this plane.
174    * Arg: uint32_t - Plane ID
175    *      uint64_t - Address of the csc config object(version based)
176    */
177   PLANE_SET_DGM_CSC_CONFIG,
178   /*
179    * Op: Sets SSPP Feature
180    * Arg: uint32_t - Plane ID
181    *      DRMPPFeatureInfo * - PP feature data pointer
182    */
183   PLANE_SET_POST_PROC,
184   /*
185    * Op: Activate or deactivate a CRTC
186    * Arg: uint32_t - CRTC ID
187    *      uint32_t - 1 to enable, 0 to disable
188    */
189   CRTC_SET_ACTIVE,
190   /*
191    * Op: Sets display mode
192    * Arg: uint32_t - CRTC ID
193    *      drmModeModeInfo* - Pointer to display mode
194    */
195   CRTC_SET_MODE,
196   /*
197    * Op: Sets an offset indicating when a release fence should be signalled.
198    * Arg: uint32_t - offset
199    *      0: non-speculative, default
200    *      1: speculative
201    */
202   CRTC_SET_OUTPUT_FENCE_OFFSET,
203   /*
204    * Op: Sets overall SDE core clock
205    * Arg: uint32_t - CRTC ID
206    *      uint32_t - core_clk
207    */
208   CRTC_SET_CORE_CLK,
209   /*
210    * Op: Sets MNOC bus average bandwidth
211    * Arg: uint32_t - CRTC ID
212    *      uint32_t - core_ab
213    */
214   CRTC_SET_CORE_AB,
215    /*
216    * Op: Sets MNOC bus instantaneous bandwidth
217    * Arg: uint32_t - CRTC ID
218    *      uint32_t - core_ib
219    */
220   CRTC_SET_CORE_IB,
221   /*
222    * Op: Sets LLCC Bus average bandwidth
223    * Arg: uint32_t - CRTC ID
224    *      uint32_t - llcc_ab
225    */
226   CRTC_SET_LLCC_AB,
227   /*
228    * Op: Sets LLCC Bus instantaneous bandwidth
229    * Arg: uint32_t - CRTC ID
230    *      uint32_t - llcc_ib
231    */
232   CRTC_SET_LLCC_IB,
233   /*
234    * Op: Sets DRAM bus average bandwidth
235    * Arg: uint32_t - CRTC ID
236    *      uint32_t - dram_ab
237    */
238   CRTC_SET_DRAM_AB,
239   /*
240    * Op: Sets DRAM bus instantaneous bandwidth
241    * Arg: uint32_t - CRTC ID
242    *      uint32_t - dram_ib
243    */
244   CRTC_SET_DRAM_IB,
245   /*
246    * Op: Sets Rotator BW for inline rotation
247    * Arg: uint32_t - CRTC ID
248    *      uint32_t - rot_bw
249    */
250   CRTC_SET_ROT_PREFILL_BW,
251   /*
252    * Op: Sets rotator clock for inline rotation
253    * Arg: uint32_t - CRTC ID
254    *      uint32_t - rot_clk
255    */
256   CRTC_SET_ROT_CLK,
257   /*
258    * Op: Sets destination scalar data
259    * Arg: uint32_t - CRTC ID
260    *      uint64_t - Pointer to destination scalar data
261    */
262   CRTC_SET_DEST_SCALER_CONFIG,
263   /*
264    * Op: Returns release fence for this frame. Should be called after Commit() on
265    * DRMAtomicReqInterface.
266    * Arg: uint32_t - CRTC ID
267    *      int * - Pointer to an integer that will hold the returned fence
268    */
269   CRTC_GET_RELEASE_FENCE,
270   /*
271    * Op: Sets PP feature
272    * Arg: uint32_t - CRTC ID
273    *      DRMPPFeatureInfo * - PP feature data pointer
274    */
275   CRTC_SET_POST_PROC,
276   /*
277    * Op: Sets CRTC ROIs.
278    * Arg: uint32_t - CRTC ID
279    *      uint32_t - number of ROIs
280    *      DRMRect * - Array of CRTC ROIs
281    */
282   CRTC_SET_ROI,
283   /*
284    * Op: Sets Security level for CRTC.
285    * Arg: uint32_t - CRTC ID
286    *      uint32_t - Security level
287    */
288   CRTC_SET_SECURITY_LEVEL,
289   /*
290    * Op: sets solid fill stages
291    * Arg: uint32_t - CRTC ID
292    *      Vector of DRMSolidfillStage
293    */
294   CRTC_SET_SOLIDFILL_STAGES,
295   /*
296    * Op: Sets idle timeout.
297    * Arg: uint32_t - CRTC ID
298    *      uint32_t - idle timeout in ms
299    */
300   CRTC_SET_IDLE_TIMEOUT,
301   /*
302    * Op: Sets Capture mode for Concurrent Writeback feature.
303    * Arg: uint32_t - CRTC ID
304    *      uint32_t - Capture mode
305    */
306   CRTC_SET_CAPTURE_MODE,
307   /*
308    * Op: Sets Idle PC state for CRTC.
309    * Arg: uint32_t - CRTC ID
310    *      uint32_t - idle pc state
311    */
312   CRTC_SET_IDLE_PC_STATE,
313   /*
314    * Op: Returns retire fence for this commit. Should be called after Commit() on
315    * DRMAtomicReqInterface.
316    * Arg: uint32_t - Connector ID
317    *      int * - Pointer to an integer that will hold the returned fence
318    */
319   CONNECTOR_GET_RETIRE_FENCE,
320   /*
321    * Op: Sets writeback connector destination rect
322    * Arg: uint32_t - Connector ID
323    *      DRMRect - Dst Rectangle
324    */
325   CONNECTOR_SET_OUTPUT_RECT,
326   /*
327    * Op: Sets frame buffer ID for writeback connector.
328    * Arg: uint32_t - Connector ID
329    *      uint32_t - Framebuffer ID
330    */
331   CONNECTOR_SET_OUTPUT_FB_ID,
332   /*
333    * Op: Sets power mode for connector.
334    * Arg: uint32_t - Connector ID
335    *      uint32_t - Power Mode
336    */
337   CONNECTOR_SET_POWER_MODE,
338   /*
339    * Op: Sets panel ROIs.
340    * Arg: uint32_t - Connector ID
341    *      uint32_t - number of ROIs
342    *      DRMRect * - Array of Connector ROIs
343    */
344   CONNECTOR_SET_ROI,
345   /*
346    * Op: Sets the connector to autorefresh mode.
347    * Arg: uint32_t - Connector ID
348    *      uint32_t - Enable-1, Disable-0
349    */
350   CONNECTOR_SET_AUTOREFRESH,
351   /*
352    * Op: Set FB secure mode for Writeback connector.
353    * Arg: uint32_t - Connector ID
354    *      uint32_t - FB Secure mode
355    */
356   CONNECTOR_SET_FB_SECURE_MODE,
357   /*
358    * Op: Sets a crtc id to this connector
359    * Arg: uint32_t - Connector ID
360    *      uint32_t - CRTC ID
361    */
362   CONNECTOR_SET_CRTC,
363   /*
364    * Op: Sets PP feature
365    * Arg: uint32_t - Connector ID
366    * DRMPPFeatureInfo * - PP feature data pointer
367    */
368   CONNECTOR_SET_POST_PROC,
369   /*
370    * Op: Sets connector hdr metadata
371    * Arg: uint32_t - Connector ID
372    *      drm_msm_ext_hdr_metadata - hdr_metadata
373    */
374   CONNECTOR_SET_HDR_METADATA,
375   /*
376    * Op: Cache Dpps features.
377    * Arg: uint32_t - Object ID
378           uint32_t - Feature ID
379    *      uint64_t - Pointer to feature config data
380    */
381   DPPS_CACHE_FEATURE,
382   /*
383    * Op: Commit Dpps features.
384    * Arg: drmModeAtomicReq - Atomic request
385    */
386   DPPS_COMMIT_FEATURE,
387   /*
388    * Op: Sets qsync mode on connector
389    * Arg: uint32_t - Connector ID
390    *     uint32_t - qsync mode
391    */
392   CONNECTOR_SET_QSYNC_MODE,
393   /*
394    * Op: Sets topology control on this connector
395    * Arg: uint32_t - Connector ID
396    *      uint32_t - Topology control bit-mask
397    */
398   CONNECTOR_SET_TOPOLOGY_CONTROL,
399   /*
400    * Op: Sets frame trigger mode on this connector
401    * Arg: uint32_t - Connector ID
402    *      uint32_t - Frame trigger mode
403    */
404   CONNECTOR_SET_FRAME_TRIGGER,
405   /*
406    * Op: Sets colorspace on DP connector
407    * Arg: uint32_t - Connector ID
408    *      uint32_t - colorspace value bit-mask
409    */
410   CONNECTOR_SET_COLORSPACE,
411 };
412 
413 enum struct DRMRotation {
414   FLIP_H = 0x1,
415   FLIP_V = 0x2,
416   ROT_180 = FLIP_H | FLIP_V,
417   ROT_90 = 0x4,
418 };
419 
420 enum struct DRMPowerMode {
421   ON,
422   DOZE,
423   DOZE_SUSPEND,
424   OFF,
425 };
426 
427 enum struct DRMBlendType {
428   UNDEFINED = 0,
429   OPAQUE = 1,
430   PREMULTIPLIED = 2,
431   COVERAGE = 3,
432 };
433 
434 enum struct DRMSrcConfig {
435   DEINTERLACE = 0,
436 };
437 
438 enum struct DRMIdlePCState {
439   NONE,
440   ENABLE,
441   DISABLE,
442 };
443 
444 
445 /* Display type to identify a suitable connector */
446 enum struct DRMDisplayType {
447   PERIPHERAL,
448   TV,
449   VIRTUAL,
450 };
451 
452 struct DRMRect {
453   uint32_t left;    // Left-most pixel coordinate.
454   uint32_t top;     // Top-most pixel coordinate.
455   uint32_t right;   // Right-most pixel coordinate.
456   uint32_t bottom;  // Bottom-most pixel coordinate.
457 };
458 
459 //------------------------------------------------------------------------
460 // DRM Info Query Types
461 //------------------------------------------------------------------------
462 
463 enum struct QSEEDVersion {
464   V1,
465   V2,
466   V3,
467   V3LITE,
468 };
469 
470 /* QSEED3 Step version */
471 enum struct QSEEDStepVersion {
472   V2,
473   V3,
474   V4,
475   V3LITE_V4,
476   V3LITE_V5,
477 };
478 
479 enum struct SmartDMARevision {
480   V1,
481   V2,
482   V2p5
483 };
484 
485 /* Inline Rotation version */
486 enum struct InlineRotationVersion {
487   kInlineRotationNone,
488   kInlineRotationV1,
489   kInlineRotationV2,
490 };
491 
492 /* Per CRTC Resource Info*/
493 struct DRMCrtcInfo {
494   bool has_src_split;
495   bool has_hdr;
496   uint32_t max_blend_stages;
497   uint32_t max_solidfill_stages;
498   QSEEDVersion qseed_version;
499   SmartDMARevision smart_dma_rev;
500   float ib_fudge_factor;
501   float clk_fudge_factor;
502   uint32_t dest_scale_prefill_lines;
503   uint32_t undersized_prefill_lines;
504   uint32_t macrotile_prefill_lines;
505   uint32_t nv12_prefill_lines;
506   uint32_t linear_prefill_lines;
507   uint32_t downscale_prefill_lines;
508   uint32_t extra_prefill_lines;
509   uint32_t amortized_threshold;
510   uint64_t max_bandwidth_low;
511   uint64_t max_bandwidth_high;
512   uint32_t max_sde_clk;
513   CompRatioMap comp_ratio_rt_map;
514   CompRatioMap comp_ratio_nrt_map;
515   uint32_t hw_version;
516   uint32_t dest_scaler_count = 0;
517   uint32_t max_dest_scaler_input_width = 0;
518   uint32_t max_dest_scaler_output_width = 0;
519   uint32_t max_dest_scale_up = 1;
520   uint32_t min_prefill_lines = 0;
521   int secure_disp_blend_stage = -1;
522   bool concurrent_writeback = false;
523   uint32_t vig_limit_index = 0;
524   uint32_t dma_limit_index = 0;
525   uint32_t scaling_limit_index = 0;
526   uint32_t rotation_limit_index = 0;
527   uint32_t line_width_constraints_count = 0;
528   std::vector< std::pair <uint32_t, uint32_t> > line_width_limits;
529   uint32_t num_mnocports;
530   uint32_t mnoc_bus_width;
531   bool use_baselayer_for_stage = false;
532   bool has_micro_idle = false;
533   uint32_t ubwc_version = 1;
534 };
535 
536 enum struct DRMPlaneType {
537   // Has CSC and scaling capability
538   VIG = 0,
539   // Has scaling capability but no CSC
540   RGB,
541   // No scaling support
542   DMA,
543   // Supports a small dimension and doesn't use a CRTC stage
544   CURSOR,
545   MAX,
546 };
547 
548 enum struct DRMTonemapLutType {
549   DMA_1D_GC,
550   DMA_1D_IGC,
551   VIG_1D_IGC,
552   VIG_3D_GAMUT,
553 };
554 
555 struct DRMPlaneTypeInfo {
556   DRMPlaneType type;
557   uint32_t master_plane_id;
558   // FourCC format enum and modifier
559   std::vector<std::pair<uint32_t, uint64_t>> formats_supported;
560   uint32_t max_linewidth;
561   uint32_t max_scaler_linewidth;
562   uint32_t max_rotation_linewidth; // inline rotation limitation
563   uint32_t max_upscale;
564   uint32_t max_downscale;
565   uint32_t max_horizontal_deci;
566   uint32_t max_vertical_deci;
567   uint64_t max_pipe_bandwidth;
568   uint64_t max_pipe_bandwidth_high;
569   uint32_t cache_size;  // cache size in bytes for inline rotation support.
570   bool has_excl_rect = false;
571   QSEEDStepVersion qseed3_version;
572   bool multirect_prop_present = false;
573   InlineRotationVersion inrot_version;  // inline rotation version
574   std::vector<std::pair<uint32_t, uint64_t>> inrot_fmts_supported;
575   float true_inline_dwnscale_rt_num = 11.0;
576   float true_inline_dwnscale_rt_denom = 5.0;
577   bool inverse_pma = false;
578   uint32_t dgm_csc_version = 0;  // csc used with DMA
579   std::map<DRMTonemapLutType, uint32_t> tonemap_lut_version_map = {};
580   bool block_sec_ui = false;
581 };
582 
583 // All DRM Planes as map<Plane_id , plane_type_info> listed from highest to lowest priority
584 typedef std::vector<std::pair<uint32_t, DRMPlaneTypeInfo>>  DRMPlanesInfo;
585 
586 enum struct DRMTopology {
587   UNKNOWN,  // To be compat with driver defs in sde_rm.h
588   SINGLE_LM,
589   SINGLE_LM_DSC,
590   DUAL_LM,
591   DUAL_LM_DSC,
592   DUAL_LM_MERGE,
593   DUAL_LM_MERGE_DSC,
594   DUAL_LM_DSCMERGE,
595   QUAD_LM_MERGE,
596   QUAD_LM_DSCMERGE,
597   QUAD_LM_MERGE_DSC,
598   PPSPLIT,
599 };
600 
601 enum struct DRMPanelMode {
602   VIDEO,
603   COMMAND,
604 };
605 
606 /* Per mode info */
607 struct DRMModeInfo {
608   drmModeModeInfo mode;
609   DRMTopology topology;
610   // Valid only if mode is command
611   int num_roi;
612   int xstart;
613   int ystart;
614   int walign;
615   int halign;
616   int wmin;
617   int hmin;
618   bool roi_merge;
619   uint64_t bit_clk_rate;
620   uint32_t transfer_time_us;
621 };
622 
623 /* Per Connector Info*/
624 struct DRMConnectorInfo {
625   uint32_t mmWidth;
626   uint32_t mmHeight;
627   uint32_t type;
628   uint32_t type_id;
629   std::vector<DRMModeInfo> modes;
630   std::string panel_name;
631   DRMPanelMode panel_mode;
632   bool is_primary;
633   // Valid only if DRMPanelMode is VIDEO
634   bool dynamic_fps;
635   // FourCC format enum and modifier
636   std::vector<std::pair<uint32_t, uint64_t>> formats_supported;
637   // Valid only if type is DRM_MODE_CONNECTOR_VIRTUAL
638   uint32_t max_linewidth;
639   DRMRotation panel_orientation;
640   drm_panel_hdr_properties panel_hdr_prop;
641   drm_msm_ext_hdr_properties ext_hdr_prop;
642   bool qsync_support;
643   // Connection status of this connector
644   bool is_connected;
645   bool is_wb_ubwc_supported;
646   uint32_t topology_control;
647   bool dyn_bitclk_support;
648   std::vector<uint8_t> edid;
649   uint32_t supported_colorspaces;
650 };
651 
652 // All DRM Connectors as map<Connector_id , connector_info>
653 typedef std::map<uint32_t, DRMConnectorInfo> DRMConnectorsInfo;
654 
655 /* Per Encoder Info */
656 struct DRMEncoderInfo {
657   uint32_t type;
658 };
659 
660 // All DRM Encoders as map<Encoder_id , encoder_info>
661 typedef std::map<uint32_t, DRMEncoderInfo> DRMEncodersInfo;
662 
663 /* Identifier token for a display */
664 struct DRMDisplayToken {
665   uint32_t conn_id;
666   uint32_t crtc_id;
667   uint32_t crtc_index;
668   uint32_t encoder_id;
669   uint8_t hw_port;
670 };
671 
672 enum DRMPPFeatureID {
673   kFeaturePcc,
674   kFeatureIgc,
675   kFeaturePgc,
676   kFeatureMixerGc,
677   kFeaturePaV2,
678   kFeatureDither,
679   kFeatureGamut,
680   kFeaturePADither,
681   kFeaturePAHsic,
682   kFeaturePASixZone,
683   kFeaturePAMemColSkin,
684   kFeaturePAMemColSky,
685   kFeaturePAMemColFoliage,
686   kFeaturePAMemColProt,
687   kFeatureDgmIgc,
688   kFeatureDgmGc,
689   kFeatureVigIgc,
690   kFeatureVigGamut,
691   kPPFeaturesMax,
692 };
693 
694 enum DRMPPPropType {
695   kPropEnum,
696   kPropRange,
697   kPropBlob,
698   kPropTypeMax,
699 };
700 
701 struct DRMPPFeatureInfo {
702   DRMPPFeatureID id;
703   DRMPPPropType type;
704   uint32_t version;
705   uint32_t payload_size;
706   void *payload;
707   uint32_t object_type;
708 };
709 
710 enum DRMDPPSFeatureID {
711   // Ad4 properties
712   kFeatureAd4Mode,
713   kFeatureAd4Init,
714   kFeatureAd4Cfg,
715   kFeatureAd4Input,
716   kFeatureAd4Roi,
717   kFeatureAd4Backlight,
718   kFeatureAd4Assertiveness,
719   kFeatureAd4ManualStrength,
720   // ABA properties
721   kFeatureAbaHistCtrl,
722   kFeatureAbaHistIRQ,
723   kFeatureAbaLut,
724   // BL scale properties
725   kFeatureSvBlScale,
726   kFeatureBacklightScale,
727   // Events
728   kFeaturePowerEvent,
729   kFeatureAbaHistEvent,
730   kFeatureBackLightEvent,
731   kFeatureAdAttBlEvent,
732   kFeatureLtmHistEvent,
733   kFeatureLtmWbPbEvent,
734   kFeatureLtmOffEvent,
735   // LTM properties
736   kFeatureLtm,
737   kFeatureLtmInit,
738   kFeatureLtmCfg,
739   kFeatureLtmNoiseThresh,
740   kFeatureLtmBufferCtrl,
741   kFeatureLtmQueueBuffer,
742   kFeatureLtmQueueBuffer2,
743   kFeatureLtmQueueBuffer3,
744   kFeatureLtmHistCtrl,
745   kFeatureLtmVlut,
746   // Insert features above
747   kDppsFeaturesMax,
748 };
749 
750 struct DppsFeaturePayload {
751   uint32_t object_type;
752   uint32_t feature_id;
753   uint64_t value;
754 };
755 
756 struct DRMDppsLtmBuffers {
757   uint32_t num_of_buffers;
758   uint32_t buffer_size;
759   std::array<int, LTM_BUFFER_SIZE> ion_buffer_fd;
760   std::array<int, LTM_BUFFER_SIZE> drm_fb_id;
761   std::array<void*, LTM_BUFFER_SIZE> uva;
762   int status;
763 };
764 
765 struct DRMDppsFeatureInfo {
766   DRMDPPSFeatureID id;
767   uint32_t obj_id;
768   uint32_t version;
769   uint32_t payload_size;
770   void *payload;
771 };
772 
773 enum AD4Modes {
774   kAd4Off,
775   kAd4AutoStrength,
776   kAd4Calibration,
777   kAd4Manual,
778   kAd4ModeMax,
779 };
780 
781 enum HistModes {
782   kHistDisabled,
783   kHistEnabled,
784 };
785 
786 struct DRMDppsEventInfo {
787   uint32_t object_type;
788   uint32_t event_type;
789   int drm_fd;
790   bool enable;
791 };
792 
793 enum DRMCscType {
794   kCscYuv2Rgb601L,
795   kCscYuv2Rgb601FR,
796   kCscYuv2Rgb709L,
797   kCscYuv2Rgb2020L,
798   kCscYuv2Rgb2020FR,
799   kCscTypeMax,
800 };
801 
802 struct DRMScalerLUTInfo {
803   uint32_t dir_lut_size = 0;
804   uint32_t cir_lut_size = 0;
805   uint32_t sep_lut_size = 0;
806   uint64_t dir_lut = 0;
807   uint64_t cir_lut = 0;
808   uint64_t sep_lut = 0;
809 };
810 
811 enum struct DRMSecureMode {
812   NON_SECURE,
813   SECURE,
814   NON_SECURE_DIR_TRANSLATION,
815   SECURE_DIR_TRANSLATION,
816 };
817 
818 enum struct DRMSecurityLevel {
819   SECURE_NON_SECURE,
820   SECURE_ONLY,
821 };
822 
823 enum struct DRMMultiRectMode {
824   NONE = 0,
825   PARALLEL = 1,
826   SERIAL = 2,
827 };
828 
829 enum struct DRMSSPPLayoutIndex {
830   NONE = 0,
831   LEFT = 1,
832   RIGHT = 2,
833 };
834 
835 enum struct DRMCWbCaptureMode {
836   MIXER_OUT = 0,
837   DSPP_OUT = 1,
838 };
839 
840 enum struct DRMQsyncMode {
841   NONE = 0,
842   CONTINUOUS,
843   ONESHOT,
844 };
845 
846 enum struct DRMTopologyControl {
847   NONE          = 0,
848   RESERVE_LOCK  = 1 << 0,
849   RESERVE_CLEAR = 1 << 1,
850   DSPP          = 1 << 2,
851   DEST_SCALER   = 1 << 3,
852 };
853 
854 struct DRMSolidfillStage {
855   DRMRect bounding_rect {};
856   bool is_exclusion_rect = false;
857   uint32_t color = 0xff000000;  // in 8bit argb
858   uint32_t red = 0;
859   uint32_t blue = 0;
860   uint32_t green = 0;
861   uint32_t alpha = 0xff;
862   uint32_t color_bit_depth = 0;
863   uint32_t z_order = 0;
864   uint32_t plane_alpha = 0xff;
865 };
866 
867 enum struct DRMFrameTriggerMode {
868   FRAME_DONE_WAIT_DEFAULT = 0,
869   FRAME_DONE_WAIT_SERIALIZE,
870   FRAME_DONE_WAIT_POSTED_START,
871 };
872 
873 /* DRM Color spaces exposed by the DP connector */
874 enum struct DRMColorspace {
875   DEFAULT = 0,
876   SMPTE_170M_YCC,
877   BT709_YCC,
878   XVYCC_601,
879   XVYCC_709,
880   SYCC_601,
881   OPYCC_601,
882   OPRGB,
883   BT2020_CYCC,
884   BT2020_RGB,
885   BT2020_YCC,
886   DCI_P3_RGB_D65,
887   DCI_P3_RGB_THEATER,
888 };
889 
890 /* DRM Atomic Request Property Set.
891  *
892  * Helper class to create and populate atomic properties of DRM components
893  * when rendered in DRM atomic mode */
894 class DRMAtomicReqInterface {
895  public:
~DRMAtomicReqInterface()896   virtual ~DRMAtomicReqInterface() {}
897   /* Perform request operation.
898    *
899    * [input]: opcode: operation code from DRMOps list.
900    *          obj_id: Relevant crtc, connector, plane id
901    *          var_arg: arguments for DRMOps's can differ in number and
902    *          data type. Refer above DRMOps to details.
903    * [return]: Error code if the API fails, 0 on success.
904    */
905   virtual int Perform(DRMOps opcode, uint32_t obj_id, ...) = 0;
906 
907   /*
908    * Commit the params set via Perform(). Also resets the properties after commit. Needs to be
909    * called every frame.
910    * [input]: synchronous: Determines if the call should block until a h/w flip
911    * [input]: retain_planes: Retains already staged planes. Useful when not explicitly programming
912    *          planes but still need the previously staged ones to not be unstaged
913    * [return]: Error code if the API fails, 0 on success.
914    */
915   virtual int Commit(bool synchronous, bool retain_planes) = 0;
916 
917   /*
918    * Validate the params set via Perform().
919    * [return]: Error code if the API fails, 0 on success.
920    */
921   virtual int Validate() = 0;
922 };
923 
924 class DRMManagerInterface;
925 
926 /* Populates a singleton instance of DRMManager */
927 typedef int (*GetDRMManager)(int fd, DRMManagerInterface **intf);
928 
929 /* Destroy DRMManager instance */
930 typedef int (*DestroyDRMManager)();
931 
932 /*
933  * DRM Manager Interface - Any class which plans to implement helper function for vendor
934  * specific DRM driver implementation must implement the below interface routines to work
935  * with SDM.
936  */
937 
938 class DRMManagerInterface {
939  public:
~DRMManagerInterface()940   virtual ~DRMManagerInterface() {}
941 
942   /*
943    * Since SDM completely manages the planes. GetPlanesInfo will provide all
944    * the plane information.
945    * [output]: DRMPlanesInfo: Resource Info for planes.
946    */
947   virtual void GetPlanesInfo(DRMPlanesInfo *info) = 0;
948 
949   /*
950    * Will provide all the information of a selected crtc.
951    * [input]: Use crtc id 0 to obtain system wide info
952    * [output]: DRMCrtcInfo: Resource Info for the given CRTC id.
953    * [return]: 0 on success, a negative error value otherwise.
954    */
955   virtual int GetCrtcInfo(uint32_t crtc_id, DRMCrtcInfo *info) = 0;
956 
957   /*
958    * Will provide all the information of a selected connector.
959    * [output]: DRMConnectorInfo: Resource Info for the given connector id
960    * [return]: 0 on success, a negative error value otherwise.
961    */
962   virtual int GetConnectorInfo(uint32_t conn_id, DRMConnectorInfo *info) = 0;
963 
964   /*
965    * Provides information on all connectors.
966    * [output]: DRMConnectorsInfo: Resource info for connectors.
967    * [return]: 0 on success, a negative error value otherwise.
968    */
969   virtual int GetConnectorsInfo(DRMConnectorsInfo *info) = 0;
970 
971   /*
972    * Provides information on a selected encoder.
973    * [output]: DRMEncoderInfo: Resource info for the given encoder id.
974    * [return]: 0 on success, a negative error value otherwise.
975    */
976   virtual int GetEncoderInfo(uint32_t encoder_id, DRMEncoderInfo *info) = 0;
977 
978   /*
979    * Provides information on all encoders.
980    * [output]: DRMEncodersInfo: Resource info for encoders.
981    * [return]: 0 on success, a negative error value otherwise.
982    */
983   virtual int GetEncodersInfo(DRMEncodersInfo *info) = 0;
984 
985   /*
986    * Will query post propcessing feature info of a CRTC.
987    * [output]: DRMPPFeatureInfo: CRTC post processing feature info
988    */
989   virtual void GetCrtcPPInfo(uint32_t crtc_id, DRMPPFeatureInfo *info) = 0;
990 
991   /*
992    * Register a logical display to receive a token.
993    * Each display pipeline in DRM is identified by its CRTC and Connector(s). On display connect
994    * (bootup or hotplug), clients should invoke this interface to establish the pipeline for the
995    * display and should get a DisplayToken populated with crtc, encoder and connnector(s) id's. Here
996    * onwards, Client should use this token to represent the display for any Perform operations if
997    * needed.
998    *
999    * [input]: disp_type - Peripheral / TV / Virtual
1000    * [output]: DRMDisplayToken - CRTC and Connector IDs for the display.
1001    * [return]: 0 on success, a negative error value otherwise.
1002    */
1003   virtual int RegisterDisplay(DRMDisplayType disp_type, DRMDisplayToken *tok) = 0;
1004 
1005   /*
1006    * Register a logical display to receive a token.
1007    * Each display pipeline in DRM is identified by its CRTC and Connector(s). On display connect
1008    * (bootup or hotplug), clients should invoke this interface to establish the pipeline for the
1009    * display and should get a DisplayToken populated with crtc, encoder and connnector(s) id's. Here
1010    * onwards, Client should use this token to represent the display for any Perform operations if
1011    * needed.
1012    *
1013    * [input]: display_id - Connector ID
1014    * [output]: DRMDisplayToken - CRTC and Connector id's for the display.
1015    * [return]: 0 on success, a negative error value otherwise.
1016    */
1017   virtual int RegisterDisplay(int32_t display_id, DRMDisplayToken *token) = 0;
1018 
1019   /* Client should invoke this interface on display disconnect.
1020    * [input]: DRMDisplayToken - identifier for the display.
1021    */
1022   virtual void UnregisterDisplay(DRMDisplayToken *token) = 0;
1023 
1024   /*
1025    * Creates and returns an instance of DRMAtomicReqInterface corresponding to a display token
1026    * returned as part of RegisterDisplay API. Needs to be called per display.
1027    * [input]: DRMDisplayToken that identifies a display pipeline
1028    * [output]: Pointer to an instance of DRMAtomicReqInterface.
1029    * [return]: Error code if the API fails, 0 on success.
1030    */
1031   virtual int CreateAtomicReq(const DRMDisplayToken &token, DRMAtomicReqInterface **intf) = 0;
1032 
1033   /*
1034    * Destroys the instance of DRMAtomicReqInterface
1035    * [input]: Pointer to a DRMAtomicReqInterface
1036    * [return]: Error code if the API fails, 0 on success.
1037    */
1038   virtual int DestroyAtomicReq(DRMAtomicReqInterface *intf) = 0;
1039 
1040   /*
1041    * Sets the global scaler LUT
1042    * [input]: LUT Info
1043    * [return]: Error code if the API fails, 0 on success.
1044    */
1045   virtual int SetScalerLUT(const DRMScalerLUTInfo &lut_info) = 0;
1046 
1047   /*
1048    * Unsets the global scaler LUT
1049    * [input]: None
1050    * [return]: Error code if the API fails, 0 on success.
1051    */
1052   virtual int UnsetScalerLUT() = 0;
1053 
1054   /*
1055    * Get the DPPS feature info
1056    * [input]: Dpps feature id, info->id
1057    * [output]: Dpps feature version, info->version
1058    */
1059   virtual void GetDppsFeatureInfo(DRMDppsFeatureInfo *info) = 0;
1060 };
1061 
1062 }  // namespace sde_drm
1063 #endif  // __DRM_INTERFACE_H__
1064