Lines Matching refs:GPR
385 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
760 let MIOperandInfo = (ops GPR, i32imm);
771 let MIOperandInfo = (ops GPR, GPR, i32imm);
782 let MIOperandInfo = (ops GPR, i32imm);
1090 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
1111 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
1167 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
1168 // the GPR is purely vestigal at this point.
1189 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
1214 let MIOperandInfo = (ops GPR, i32imm);
1232 let MIOperandInfo = (ops GPR:$base, i32imm);
1251 let MIOperandInfo = (ops GPR:$base, i32imm);
1264 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
1274 let MIOperandInfo = (ops GPR);
1284 let MIOperandInfo = (ops GPR:$addr, i32imm);
1292 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
1368 let MIOperandInfo = (ops GPR:$addr, i32imm);
1379 let MIOperandInfo = (ops GPR:$addr, i32imm);
1443 let MIOperandInfo = (ops GPR, i32imm);
1454 let MIOperandInfo = (ops GPR:$base);
1514 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1516 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1527 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1529 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1542 def rsi : AsI1<opcod, (outs GPR:$Rd),
1543 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1545 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1558 def rsr : AsI1<opcod, (outs GPR:$Rd),
1559 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1561 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1587 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1589 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>,
1600 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1614 def rsi : AsI1<opcod, (outs GPR:$Rd),
1615 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1617 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1630 def rsr : AsI1<opcod, (outs GPR:$Rd),
1631 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1633 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1657 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1659 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1662 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1664 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1668 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1669 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1671 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1675 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1676 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1678 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1690 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1692 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1695 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1696 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1698 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1699 GPR:$Rn))]>,
1702 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1703 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1705 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1706 GPR:$Rn))]>,
1719 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
1721 [(opnode GPR:$Rn, mod_imm:$imm)]>,
1733 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1735 [(opnode GPR:$Rn, GPR:$Rm)]>,
1751 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1753 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1819 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1821 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1836 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1850 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1852 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
1863 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1865 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1878 def rsi : AsI1<opcod, (outs GPR:$Rd),
1879 (ins GPR:$Rn, so_reg_imm:$shift),
1881 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1920 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1922 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>,
1933 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1946 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1948 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1961 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1963 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1985 // GPR and a constrained immediate so that we can use this to match
1987 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1989 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1997 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1999 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
2015 // GPR and a constrained immediate so that we can use this to match
2047 // GPR and a constrained immediate so that we can use this to match
2050 (ins GPR:$Rt, addrmode_imm12:$addr),
2052 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
2060 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
2062 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
2076 // GPR and a constrained immediate so that we can use this to match
2178 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
2180 [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>,
2352 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
2354 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
2358 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
2360 [(set GPR:$dst, (load addrmodepc:$addr))]>;
2362 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2364 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
2366 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2368 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
2370 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2372 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
2374 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2376 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
2379 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2380 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
2382 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2383 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
2386 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2387 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
2398 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
2414 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
2417 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
2451 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
2452 [(brind GPR:$dst)]>,
2459 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
2495 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2497 [(ARMcall GPR:$func)]>,
2504 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2506 [(ARMcall_pred GPR:$func)]>,
2562 (ins GPR:$target, i32imm:$jt),
2564 [(ARMbrjt GPR:$target, tjumptable:$jt)]>,
2577 (ins GPR:$target, GPR:$idx, i32imm:$jt),
2579 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>,
2598 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2624 (BX GPR:$dst)>, Sched<[WriteBr]>,
2700 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2781 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2793 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2795 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2798 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2800 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2802 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2804 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2808 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2821 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2823 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2825 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2831 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2842 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2854 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2872 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2899 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2911 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2932 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2945 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2964 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2984 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
3000 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
3020 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
3037 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
3061 (ins addr_offset_none:$addr, pred:$p), (outs GPR:$Rt)>;
3071 (outs GPR:$Rt)>;
3075 (outs GPR:$Rt)>;
3081 (outs GPR:$Rt)>;
3086 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
3088 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
3092 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
3110 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
3111 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
3123 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
3124 (ins GPR:$Rt, ldst_so_reg:$addr),
3136 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
3137 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
3154 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
3155 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3179 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
3181 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
3183 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
3185 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
3187 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
3189 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
3191 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
3193 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
3203 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
3204 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
3206 [(set GPR:$Rn_wb,
3207 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
3208 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
3209 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
3211 [(set GPR:$Rn_wb,
3212 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
3213 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
3214 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
3216 [(set GPR:$Rn_wb,
3217 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
3218 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
3219 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
3221 [(set GPR:$Rn_wb,
3222 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
3223 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
3224 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
3226 [(set GPR:$Rn_wb,
3227 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
3232 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
3233 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
3246 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
3247 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
3251 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
3265 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
3266 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
3279 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
3280 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
3298 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
3299 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
3318 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
3319 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3336 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3339 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3340 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
3359 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3360 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3378 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3381 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3382 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
3391 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3392 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
3406 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3408 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3410 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3422 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3431 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3442 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3451 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3462 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3471 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3482 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3491 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3520 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3523 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3541 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
3583 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3585 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3598 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi,
3599 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP,
3610 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3613 [(set GPR:$Rd, imm0_65535:$imm)]>,
3626 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p), 0>,
3629 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3635 (ins GPR:$src, imm0_65535_expr:$imm),
3639 (or (and GPR:$src, 0xffff),
3652 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3653 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3658 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3662 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3663 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3670 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3671 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3673 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3674 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3701 def : ARMV6Pat<(int_arm_sxtb16 GPR:$Src),
3702 (SXTB16 GPR:$Src, 0)>;
3703 def : ARMV6Pat<(int_arm_sxtb16 (rotr GPR:$Src, rot_imm:$rot)),
3704 (SXTB16 GPR:$Src, rot_imm:$rot)>;
3707 def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, GPR:$RHS),
3708 (SXTAB16 GPR:$LHS, GPR:$RHS, 0)>;
3709 def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, (rotr GPR:$RHS, rot_imm:$rot)),
3710 (SXTAB16 GPR:$LHS, GPR:$RHS, rot_imm:$rot)>;
3726 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3727 // (UXTB16r_rot GPR:$Src, 3)>;
3728 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3729 (UXTB16 GPR:$Src, 1)>;
3730 def : ARMV6Pat<(int_arm_uxtb16 GPR:$Src),
3731 (UXTB16 GPR:$Src, 0)>;
3732 def : ARMV6Pat<(int_arm_uxtb16 (rotr GPR:$Src, rot_imm:$rot)),
3733 (UXTB16 GPR:$Src, rot_imm:$rot)>;
3748 def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, GPR:$RHS),
3749 (UXTAB16 GPR:$LHS, GPR:$RHS, 0)>;
3750 def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, (rotr GPR:$RHS, rot_imm:$rot)),
3751 (UXTAB16 GPR:$LHS, GPR:$RHS, rot_imm:$rot)>;
3812 def : ARMPat<(ARMsubs GPR:$Rn, mod_imm:$imm), (SUBSri $Rn, mod_imm:$imm)>;
3813 def : ARMPat<(ARMsubs GPR:$Rn, GPR:$Rm), (SUBSrr $Rn, $Rm)>;
3814 def : ARMPat<(ARMsubs GPR:$Rn, so_reg_imm:$shift),
3816 def : ARMPat<(ARMsubs GPR:$Rn, so_reg_reg:$shift),
3839 def : ARMPat<(add GPR:$src, mod_imm_neg:$imm),
3840 (SUBri GPR:$src, mod_imm_neg:$imm)>;
3841 def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm),
3842 (SUBSri GPR:$src, mod_imm_neg:$imm)>;
3844 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3845 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3847 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3848 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3854 def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR),
3855 (SBCri GPR:$src, mod_imm_not:$imm)>;
3856 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3857 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,
3867 // GPR:$dst = GPR:$a op GPR:$b
3919 def : ARMV5TEPat<(saddsat GPR:$a, GPR:$b),
3920 (QADD GPR:$a, GPR:$b)>;
3921 def : ARMV5TEPat<(ssubsat GPR:$a, GPR:$b),
3922 (QSUB GPR:$a, GPR:$b)>;
3977 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3980 [(set GPR:$Rd, (int_arm_usad8 GPR:$Rn, GPR:$Rm))]>,
3992 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3995 [(set GPR:$Rd, (int_arm_usada8 GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4120 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
4123 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
4135 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
4138 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
4152 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
4154 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
4165 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
4167 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
4198 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
4200 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
4210 def : ARMPat<(and GPR:$src, mod_imm_not:$imm),
4211 (BICri GPR:$src, mod_imm_not:$imm)>;
4294 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4296 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
4312 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
4313 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
4315 [(set GPR:$RdLo, GPR:$RdHi,
4316 (smullohi GPR:$Rn, GPR:$Rm))]>,
4320 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
4321 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
4323 [(set GPR:$RdLo, GPR:$RdHi,
4324 (umullohi GPR:$Rn, GPR:$Rm))]>,
4329 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4330 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
4332 [(set GPR:$RdLo, GPR:$RdHi,
4333 (smullohi GPR:$Rn, GPR:$Rm))],
4334 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4338 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4339 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
4341 [(set GPR:$RdLo, GPR:$RdHi,
4342 (umullohi GPR:$Rn, GPR:$Rm))],
4343 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4350 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
4351 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
4355 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
4356 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
4361 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
4362 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4379 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4380 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
4382 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4386 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4387 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
4389 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4398 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4400 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
4406 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4408 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, (i32 0)))]>,
4414 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
4415 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4417 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
4421 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
4422 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4424 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4428 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
4429 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4434 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
4435 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4437 [(set GPR:$Rd, (ARMsmmlsr GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4442 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4444 [(set GPR:$Rd, (bb_mul GPR:$Rn, GPR:$Rm))]>,
4448 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4450 [(set GPR:$Rd, (bt_mul GPR:$Rn, GPR:$Rm))]>,
4454 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4456 [(set GPR:$Rd, (tb_mul GPR:$Rn, GPR:$Rm))]>,
4460 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4462 [(set GPR:$Rd, (tt_mul GPR:$Rn, GPR:$Rm))]>,
4466 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4468 [(set GPR:$Rd, (ARMsmulwb GPR:$Rn, GPR:$Rm))]>,
4472 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4474 [(set GPR:$Rd, (ARMsmulwt GPR:$Rn, GPR:$Rm))]>,
4483 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4485 [(set GPRnopc:$Rd, (add GPR:$Ra,
4491 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4493 [(set GPRnopc:$Rd, (add GPR:$Ra,
4499 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4501 [(set GPRnopc:$Rd, (add GPR:$Ra,
4507 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4509 [(set GPRnopc:$Rd, (add GPR:$Ra,
4515 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4518 (add GPR:$Ra, (ARMsmulwb GPRnopc:$Rn, GPRnopc:$Rm)))]>,
4523 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4526 (add GPR:$Ra, (ARMsmulwt GPRnopc:$Rn, GPRnopc:$Rm)))]>,
4550 def : ARMV5TEPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4552 def : ARMV5TEPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4554 def : ARMV5TEPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4556 def : ARMV5TEPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4603 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4608 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4630 def : ARMV6Pat<(int_arm_smlad GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4632 def : ARMV6Pat<(int_arm_smladx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4634 def : ARMV6Pat<(int_arm_smlsd GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4636 def : ARMV6Pat<(int_arm_smlsdx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4672 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4674 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4678 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4680 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4688 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
4690 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4693 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4695 [(set GPR:$Rd, (bitreverse GPR:$Rm))]>,
4699 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4701 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4705 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4707 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
4713 def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr),
4714 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
4717 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4719 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4723 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
4724 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
4725 (REVSH GPR:$Rm)>;
4838 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm),
4839 (CMPri GPR:$src, mod_imm:$imm)>;
4840 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4841 (CMPrr GPR:$src, GPR:$rhs)>;
4842 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4843 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4844 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4845 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4849 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi,
4851 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>,
4865 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4868 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4883 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4886 GPR:$Rn, so_reg_imm:$shift)]>,
4924 def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm),
4925 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4927 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm),
4928 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4943 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4945 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4949 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4950 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4959 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
4960 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
4962 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
4966 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4967 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4969 [(set GPR:$Rd,
4970 (ARMcmov GPR:$false, so_reg_imm:$shift,
4973 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4974 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
4976 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4983 : ARMPseudoInst<(outs GPR:$Rd),
4984 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4986 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
4992 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4993 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4995 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm,
5002 : ARMPseudoInst<(outs GPR:$Rd),
5003 (ins GPR:$false, i32imm:$src, cmovpred:$p),
5005 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
5010 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
5011 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
5013 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm,
5099 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
5104 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
5106 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
5115 (outs GPR:$newdst, GPR:$newsrc),
5116 (ins GPR:$dst, GPR:$src, i32imm:$nreg, variable_ops),
5118 [(set GPR:$newdst, GPR:$newsrc,
5119 (ARMmemcopy GPR:$dst, GPR:$src, imm:$nreg))]>;
5177 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
5179 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
5180 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
5182 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
5183 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
5185 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
5192 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
5194 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>;
5195 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
5197 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>;
5198 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
5200 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>;
5209 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5211 [(set GPR:$Rd, (strex_1 GPR:$Rt,
5213 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5215 [(set GPR:$Rd, (strex_2 GPR:$Rt,
5217 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5219 [(set GPR:$Rd, (strex_4 GPR:$Rt,
5222 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
5227 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5229 [(set GPR:$Rd,
5230 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>;
5231 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5233 [(set GPR:$Rd,
5234 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>;
5235 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5237 [(set GPR:$Rd,
5238 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>;
5240 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
5253 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
5254 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
5255 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
5256 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
5258 def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
5259 (STLEXB GPR:$Rt, addr_offset_none:$addr)>;
5260 def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
5261 (STLEXH GPR:$Rt, addr_offset_none:$addr)>;
5287 …def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offs…
5288 …def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offs…
5289 …def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offs…
5556 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5558 [(int_arm_mcr timm:$cop, timm:$opc1, GPR:$Rt, timm:$CRn,
5562 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5603 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5605 [(int_arm_mcr2 timm:$cop, timm:$opc1, GPR:$Rt, timm:$CRn,
5609 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5748 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5854 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5856 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5863 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5865 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5872 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
5874 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
5896 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
5897 4, IIC_Br, [(brind GPR:$dst)],
5898 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5902 def TAILJMPr4 : ARMPseudoExpand<(outs), (ins GPR:$dst),
5904 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5914 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
5915 [(set GPR:$dst, (arm_i32imm:$src))]>,
5918 def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i,
5919 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>,
5927 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5929 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
5932 def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5934 [(set GPR:$dst,
5939 def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5941 [(set GPR:$dst,
5946 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5948 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
6011 (SMULBB GPR:$a, GPR:$b)>;
6012 def : ARMV5TEPat<(mul sext_16_node:$a, (sext_bottom_16 GPR:$b)),
6013 (SMULBB GPR:$a, GPR:$b)>;
6014 def : ARMV5TEPat<(mul sext_16_node:$a, (sext_top_16 GPR:$b)),
6015 (SMULBT GPR:$a, GPR:$b)>;
6016 def : ARMV5TEPat<(mul (sext_top_16 GPR:$a), sext_16_node:$b),
6017 (SMULTB GPR:$a, GPR:$b)>;
6018 def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, sext_16_node:$b)),
6019 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
6020 def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, (sext_bottom_16 GPR:$b))),
6021 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
6022 def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, (sext_top_16 GPR:$b))),
6023 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
6024 def : ARMV5MOPat<(add GPR:$acc, (mul (sext_top_16 GPR:$a), sext_16_node:$b)),
6025 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
6027 def : ARMV5TEPat<(int_arm_smulbb GPR:$a, GPR:$b),
6028 (SMULBB GPR:$a, GPR:$b)>;
6029 def : ARMV5TEPat<(int_arm_smulbt GPR:$a, GPR:$b),
6030 (SMULBT GPR:$a, GPR:$b)>;
6031 def : ARMV5TEPat<(int_arm_smultb GPR:$a, GPR:$b),
6032 (SMULTB GPR:$a, GPR:$b)>;
6033 def : ARMV5TEPat<(int_arm_smultt GPR:$a, GPR:$b),
6034 (SMULTT GPR:$a, GPR:$b)>;
6035 def : ARMV5TEPat<(int_arm_smulwb GPR:$a, GPR:$b),
6036 (SMULWB GPR:$a, GPR:$b)>;
6037 def : ARMV5TEPat<(int_arm_smulwt GPR:$a, GPR:$b),
6038 (SMULWT GPR:$a, GPR:$b)>;
6040 def : ARMV5TEPat<(int_arm_smlabb GPR:$a, GPR:$b, GPR:$acc),
6041 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
6042 def : ARMV5TEPat<(int_arm_smlabt GPR:$a, GPR:$b, GPR:$acc),
6043 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
6044 def : ARMV5TEPat<(int_arm_smlatb GPR:$a, GPR:$b, GPR:$acc),
6045 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
6046 def : ARMV5TEPat<(int_arm_smlatt GPR:$a, GPR:$b, GPR:$acc),
6047 (SMLATT GPR:$a, GPR:$b, GPR:$acc)>;
6048 def : ARMV5TEPat<(int_arm_smlawb GPR:$a, GPR:$b, GPR:$acc),
6049 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
6050 def : ARMV5TEPat<(int_arm_smlawt GPR:$a, GPR:$b, GPR:$acc),
6051 (SMLAWT GPR:$a, GPR:$b, GPR:$acc)>;
6054 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
6059 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
6060 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
6061 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
6062 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
6063 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
6064 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
6065 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
6068 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
6069 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
6071 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
6072 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
6073 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
6074 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
6087 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
6088 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
6089 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
6090 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
6091 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
6092 (STRH GPR:$val, addrmode3:$ptr)>;
6093 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
6094 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
6095 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
6096 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
6181 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6183 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6185 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6194 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6196 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6198 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6252 (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
6255 (ANDri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm,
6258 (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
6261 (BICri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm,
6266 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
6268 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
6271 (ADDri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
6273 (ADDri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
6277 (SBCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
6279 (SBCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
6281 (ADCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
6283 (ADCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
6298 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
6301 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
6304 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
6307 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
6311 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
6329 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
6346 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6349 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6352 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6355 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6364 def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn),
6366 [(set GPR:$Rd, (int_arm_space timm:$size, GPR:$Rn))]>;
6384 def CMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, GPR:$temp),
6385 (ins GPR:$addr, GPR:$desired, GPR:$new),
6388 def CMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, GPR:$temp),
6389 (ins GPR:$addr, GPR:$desired, GPR:$new),
6392 def CMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, GPR:$temp),
6393 (ins GPR:$addr, GPR:$desired, GPR:$new),
6396 def CMP_SWAP_64 : PseudoInst<(outs GPRPair:$Rd, GPR:$temp),
6397 (ins GPR:$addr, GPRPair:$desired, GPRPair:$new),