1//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the ARM instructions in TableGen format. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// ARM specific DAG Nodes. 15// 16 17// Type profiles. 18def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 19 SDTCisVT<1, i32> ]>; 20def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; 21def SDT_ARMStructByVal : SDTypeProfile<0, 4, 22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 24 25def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; 26 27def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 28 29def SDT_ARMCMov : SDTypeProfile<1, 3, 30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 31 SDTCisVT<3, i32>]>; 32 33def SDT_ARMBrcond : SDTypeProfile<0, 2, 34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 35 36def SDT_ARMBrJT : SDTypeProfile<0, 2, 37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 38 39def SDT_ARMBr2JT : SDTypeProfile<0, 3, 40 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 41 SDTCisVT<2, i32>]>; 42 43def SDT_ARMBCC_i64 : SDTypeProfile<0, 6, 44 [SDTCisVT<0, i32>, 45 SDTCisVT<1, i32>, SDTCisVT<2, i32>, 46 SDTCisVT<3, i32>, SDTCisVT<4, i32>, 47 SDTCisVT<5, OtherVT>]>; 48 49def SDT_ARMAnd : SDTypeProfile<1, 2, 50 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 51 SDTCisVT<2, i32>]>; 52 53def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 54 55def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 56 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; 57 58def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 59def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>, 60 SDTCisInt<2>]>; 61def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; 62def SDT_ARMEH_SJLJ_SetupDispatch: SDTypeProfile<0, 0, []>; 63 64def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 65 66def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, 67 SDTCisInt<1>]>; 68 69def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 70 71def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 73 74def SDT_WIN__DBZCHK : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 75 76def SDT_ARMMEMCPY : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 77 SDTCisVT<2, i32>, SDTCisVT<3, i32>, 78 SDTCisVT<4, i32>]>; 79 80def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 81 [SDTCisSameAs<0, 2>, 82 SDTCisSameAs<0, 3>, 83 SDTCisInt<0>, SDTCisVT<1, i32>]>; 84 85// SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR 86def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 87 [SDTCisSameAs<0, 2>, 88 SDTCisSameAs<0, 3>, 89 SDTCisInt<0>, 90 SDTCisVT<1, i32>, 91 SDTCisVT<4, i32>]>; 92 93def SDT_LongMac : SDTypeProfile<2, 4, [SDTCisVT<0, i32>, 94 SDTCisSameAs<0, 1>, 95 SDTCisSameAs<0, 2>, 96 SDTCisSameAs<0, 3>, 97 SDTCisSameAs<0, 4>, 98 SDTCisSameAs<0, 5>]>; 99 100// ARMlsll, ARMlsrl, ARMasrl 101def SDT_ARMIntShiftParts : SDTypeProfile<2, 3, [SDTCisSameAs<0, 1>, 102 SDTCisSameAs<0, 2>, 103 SDTCisSameAs<0, 3>, 104 SDTCisInt<0>, 105 SDTCisInt<4>]>; 106 107def ARMSmlald : SDNode<"ARMISD::SMLALD", SDT_LongMac>; 108def ARMSmlaldx : SDNode<"ARMISD::SMLALDX", SDT_LongMac>; 109def ARMSmlsld : SDNode<"ARMISD::SMLSLD", SDT_LongMac>; 110def ARMSmlsldx : SDNode<"ARMISD::SMLSLDX", SDT_LongMac>; 111 112def SDT_ARMCSel : SDTypeProfile<1, 3, 113 [SDTCisSameAs<0, 1>, 114 SDTCisSameAs<0, 2>, 115 SDTCisInt<3>, 116 SDTCisVT<3, i32>]>; 117 118def ARMcsinv : SDNode<"ARMISD::CSINV", SDT_ARMCSel, [SDNPOptInGlue]>; 119def ARMcsneg : SDNode<"ARMISD::CSNEG", SDT_ARMCSel, [SDNPOptInGlue]>; 120def ARMcsinc : SDNode<"ARMISD::CSINC", SDT_ARMCSel, [SDNPOptInGlue]>; 121 122def SDT_MulHSR : SDTypeProfile<1, 3, [SDTCisVT<0,i32>, 123 SDTCisSameAs<0, 1>, 124 SDTCisSameAs<0, 2>, 125 SDTCisSameAs<0, 3>]>; 126 127def ARMsmmlar : SDNode<"ARMISD::SMMLAR", SDT_MulHSR>; 128def ARMsmmlsr : SDNode<"ARMISD::SMMLSR", SDT_MulHSR>; 129 130// Node definitions. 131def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; 132def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>; 133def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntUnaryOp>; 134 135def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, 136 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 137def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, 138 [SDNPHasChain, SDNPSideEffect, 139 SDNPOptInGlue, SDNPOutGlue]>; 140def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" , 141 SDT_ARMStructByVal, 142 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 143 SDNPMayStore, SDNPMayLoad]>; 144 145def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, 146 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 147 SDNPVariadic]>; 148def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, 149 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 150 SDNPVariadic]>; 151def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, 152 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 153 SDNPVariadic]>; 154 155def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, 156 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 157def ARMseretflag : SDNode<"ARMISD::SERET_FLAG", SDTNone, 158 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 159def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall, 160 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 161def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, 162 [SDNPInGlue]>; 163def ARMsubs : SDNode<"ARMISD::SUBS", SDTIntBinOp, [SDNPOutGlue]>; 164 165def ARMssat : SDNode<"ARMISD::SSAT", SDTIntSatNoShOp, []>; 166 167def ARMusat : SDNode<"ARMISD::USAT", SDTIntSatNoShOp, []>; 168 169def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, 170 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 171 172def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, 173 [SDNPHasChain]>; 174def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT, 175 [SDNPHasChain]>; 176 177def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64, 178 [SDNPHasChain]>; 179 180def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, 181 [SDNPOutGlue]>; 182 183def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp, 184 [SDNPOutGlue]>; 185 186def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp, 187 [SDNPOutGlue, SDNPCommutative]>; 188 189def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; 190 191def ARMasrl : SDNode<"ARMISD::ASRL", SDT_ARMIntShiftParts, []>; 192def ARMlsrl : SDNode<"ARMISD::LSRL", SDT_ARMIntShiftParts, []>; 193def ARMlsll : SDNode<"ARMISD::LSLL", SDT_ARMIntShiftParts, []>; 194 195def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 196def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 197def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>; 198 199def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags, 200 [SDNPCommutative]>; 201def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>; 202def ARMlsls : SDNode<"ARMISD::LSLS", SDTBinaryArithWithFlags>; 203def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>; 204def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>; 205 206def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; 207def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", 208 SDT_ARMEH_SJLJ_Setjmp, 209 [SDNPHasChain, SDNPSideEffect]>; 210def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP", 211 SDT_ARMEH_SJLJ_Longjmp, 212 [SDNPHasChain, SDNPSideEffect]>; 213def ARMeh_sjlj_setup_dispatch: SDNode<"ARMISD::EH_SJLJ_SETUP_DISPATCH", 214 SDT_ARMEH_SJLJ_SetupDispatch, 215 [SDNPHasChain, SDNPSideEffect]>; 216 217def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER, 218 [SDNPHasChain, SDNPSideEffect]>; 219def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH, 220 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; 221 222def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET, 223 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 224 225def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; 226 227def ARMmemcopy : SDNode<"ARMISD::MEMCPY", SDT_ARMMEMCPY, 228 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 229 SDNPMayStore, SDNPMayLoad]>; 230 231def ARMsmulwb : SDNode<"ARMISD::SMULWB", SDTIntBinOp, []>; 232def ARMsmulwt : SDNode<"ARMISD::SMULWT", SDTIntBinOp, []>; 233def ARMsmlalbb : SDNode<"ARMISD::SMLALBB", SDT_LongMac, []>; 234def ARMsmlalbt : SDNode<"ARMISD::SMLALBT", SDT_LongMac, []>; 235def ARMsmlaltb : SDNode<"ARMISD::SMLALTB", SDT_LongMac, []>; 236def ARMsmlaltt : SDNode<"ARMISD::SMLALTT", SDT_LongMac, []>; 237 238def ARMqadd8b : SDNode<"ARMISD::QADD8b", SDT_ARMAnd, []>; 239def ARMqsub8b : SDNode<"ARMISD::QSUB8b", SDT_ARMAnd, []>; 240def ARMqadd16b : SDNode<"ARMISD::QADD16b", SDT_ARMAnd, []>; 241def ARMqsub16b : SDNode<"ARMISD::QSUB16b", SDT_ARMAnd, []>; 242 243def SDT_ARMldrd : SDTypeProfile<2, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>; 244def ARMldrd : SDNode<"ARMISD::LDRD", SDT_ARMldrd, [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 245 246def SDT_ARMstrd : SDTypeProfile<0, 3, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>; 247def ARMstrd : SDNode<"ARMISD::STRD", SDT_ARMstrd, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 248 249// Vector operations shared between NEON and MVE 250 251def ARMvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>; 252 253// VDUPLANE can produce a quad-register result from a double-register source, 254// so the result is not constrained to match the source. 255def ARMvduplane : SDNode<"ARMISD::VDUPLANE", 256 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 257 SDTCisVT<2, i32>]>>; 258 259def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>; 260def ARMvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>; 261def ARMvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>; 262def ARMvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>; 263 264def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVec<1>, 265 SDTCisVT<2, i32>]>; 266def ARMvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>; 267def ARMvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>; 268 269def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>; 270def ARMvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>; 271def ARMvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>; 272def ARMvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>; 273 274def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, 275 SDTCisVT<2, i32>]>; 276def ARMvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>; 277def ARMvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>; 278 279def SDTARMVSHIMM : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 280 SDTCisVT<2, i32>]>; 281def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 282 SDTCisSameAs<0, 2>,]>; 283def ARMvshlImm : SDNode<"ARMISD::VSHLIMM", SDTARMVSHIMM>; 284def ARMvshrsImm : SDNode<"ARMISD::VSHRsIMM", SDTARMVSHIMM>; 285def ARMvshruImm : SDNode<"ARMISD::VSHRuIMM", SDTARMVSHIMM>; 286def ARMvshls : SDNode<"ARMISD::VSHLs", SDTARMVSH>; 287def ARMvshlu : SDNode<"ARMISD::VSHLu", SDTARMVSH>; 288 289def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>, 290 SDTCisSameAs<1, 2>]>; 291def ARMvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>; 292def ARMvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>; 293 294def SDTARMVCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, 295 SDTCisInt<3>]>; 296def SDTARMVCMPZ : SDTypeProfile<1, 2, [SDTCisInt<2>]>; 297 298def ARMvcmp : SDNode<"ARMISD::VCMP", SDTARMVCMP>; 299def ARMvcmpz : SDNode<"ARMISD::VCMPZ", SDTARMVCMPZ>; 300 301// 'VECTOR_REG_CAST' is an operation that reinterprets the contents of a 302// vector register as a different vector type, without changing the contents of 303// the register. It differs from 'bitconvert' in that bitconvert reinterprets 304// the _memory_ storage format of the vector, whereas VECTOR_REG_CAST 305// reinterprets the _register_ format - and in big-endian, the memory and 306// register formats are different, so they are different operations. 307// 308// For example, 'VECTOR_REG_CAST' between v8i16 and v16i8 will map the LSB of 309// the zeroth i16 lane to the zeroth i8 lane, regardless of system endianness, 310// whereas 'bitconvert' will map it to the high byte in big-endian mode, 311// because that's what (MVE) VSTRH.16 followed by VLDRB.8 would do. So the 312// bitconvert would have to emit a VREV16.8 instruction, whereas the 313// VECTOR_REG_CAST emits no code at all if the vector is already in a register. 314def ARMVectorRegCastImpl : SDNode<"ARMISD::VECTOR_REG_CAST", SDTUnaryOp>; 315 316// In little-endian, VECTOR_REG_CAST is often turned into bitconvert during 317// lowering (because in that situation they're identical). So an isel pattern 318// that needs to match something that's _logically_ a VECTOR_REG_CAST must 319// _physically_ match a different node type depending on endianness. 320// 321// This 'PatFrags' instance is a centralized facility to make that easy. It 322// matches VECTOR_REG_CAST in either endianness, and also bitconvert in the 323// endianness where it's equivalent. 324def ARMVectorRegCast: PatFrags< 325 (ops node:$x), [(ARMVectorRegCastImpl node:$x), (bitconvert node:$x)], [{ 326 // Reject a match against bitconvert (aka ISD::BITCAST) if big-endian 327 return !(CurDAG->getDataLayout().isBigEndian() && 328 N->getOpcode() == ISD::BITCAST); 329 }]>; 330 331//===----------------------------------------------------------------------===// 332// ARM Flag Definitions. 333 334class RegConstraint<string C> { 335 string Constraints = C; 336} 337 338// ARMCC condition codes. See ARMCC::CondCodes 339def ARMCCeq : PatLeaf<(i32 0)>; 340def ARMCCne : PatLeaf<(i32 1)>; 341def ARMCChs : PatLeaf<(i32 2)>; 342def ARMCClo : PatLeaf<(i32 3)>; 343def ARMCCmi : PatLeaf<(i32 4)>; 344def ARMCCpl : PatLeaf<(i32 5)>; 345def ARMCCvs : PatLeaf<(i32 6)>; 346def ARMCCvc : PatLeaf<(i32 7)>; 347def ARMCChi : PatLeaf<(i32 8)>; 348def ARMCCls : PatLeaf<(i32 9)>; 349def ARMCCge : PatLeaf<(i32 10)>; 350def ARMCClt : PatLeaf<(i32 11)>; 351def ARMCCgt : PatLeaf<(i32 12)>; 352def ARMCCle : PatLeaf<(i32 13)>; 353def ARMCCal : PatLeaf<(i32 14)>; 354 355// VCC predicates. See ARMVCC::VPTCodes 356def ARMVCCNone : PatLeaf<(i32 0)>; 357def ARMVCCThen : PatLeaf<(i32 1)>; 358def ARMVCCElse : PatLeaf<(i32 2)>; 359 360//===----------------------------------------------------------------------===// 361// ARM specific transformation functions and pattern fragments. 362// 363 364// imm_neg_XFORM - Return the negation of an i32 immediate value. 365def imm_neg_XFORM : SDNodeXForm<imm, [{ 366 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32); 367}]>; 368 369// imm_not_XFORM - Return the complement of a i32 immediate value. 370def imm_not_XFORM : SDNodeXForm<imm, [{ 371 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32); 372}]>; 373 374// asr_imm_XFORM - Returns a shift immediate with bit {5} set to 1 375def asr_imm_XFORM : SDNodeXForm<imm, [{ 376 return CurDAG->getTargetConstant(0x20 | N->getZExtValue(), SDLoc(N), MVT:: i32); 377}]>; 378 379/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. 380def imm16_31 : ImmLeaf<i32, [{ 381 return (int32_t)Imm >= 16 && (int32_t)Imm < 32; 382}]>; 383 384// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. 385def sext_16_node : PatLeaf<(i32 GPR:$a), [{ 386 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17; 387}]>; 388 389def sext_bottom_16 : PatFrag<(ops node:$a), 390 (sext_inreg node:$a, i16)>; 391def sext_top_16 : PatFrag<(ops node:$a), 392 (i32 (sra node:$a, (i32 16)))>; 393 394def bb_mul : PatFrag<(ops node:$a, node:$b), 395 (mul (sext_bottom_16 node:$a), (sext_bottom_16 node:$b))>; 396def bt_mul : PatFrag<(ops node:$a, node:$b), 397 (mul (sext_bottom_16 node:$a), (sra node:$b, (i32 16)))>; 398def tb_mul : PatFrag<(ops node:$a, node:$b), 399 (mul (sra node:$a, (i32 16)), (sext_bottom_16 node:$b))>; 400def tt_mul : PatFrag<(ops node:$a, node:$b), 401 (mul (sra node:$a, (i32 16)), (sra node:$b, (i32 16)))>; 402 403/// Split a 32-bit immediate into two 16 bit parts. 404def hi16 : SDNodeXForm<imm, [{ 405 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N), 406 MVT::i32); 407}]>; 408 409def lo16AllZero : PatLeaf<(i32 imm), [{ 410 // Returns true if all low 16-bits are 0. 411 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; 412}], hi16>; 413 414class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; 415class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; 416 417// An 'and' node with a single use. 418def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 419 return N->hasOneUse(); 420}]>; 421 422// An 'xor' node with a single use. 423def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{ 424 return N->hasOneUse(); 425}]>; 426 427// An 'fmul' node with a single use. 428def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{ 429 return N->hasOneUse(); 430}]>; 431 432// An 'fadd' node which checks for single non-hazardous use. 433def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{ 434 return hasNoVMLxHazardUse(N); 435}]>; 436 437// An 'fsub' node which checks for single non-hazardous use. 438def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{ 439 return hasNoVMLxHazardUse(N); 440}]>; 441 442def imm_even : ImmLeaf<i32, [{ return (Imm & 1) == 0; }]>; 443def imm_odd : ImmLeaf<i32, [{ return (Imm & 1) == 1; }]>; 444 445def asr_imm : ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }], asr_imm_XFORM>; 446 447//===----------------------------------------------------------------------===// 448// NEON/MVE pattern fragments 449// 450 451// Extract D sub-registers of Q registers. 452def DSubReg_i8_reg : SDNodeXForm<imm, [{ 453 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); 454 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, SDLoc(N), 455 MVT::i32); 456}]>; 457def DSubReg_i16_reg : SDNodeXForm<imm, [{ 458 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); 459 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, SDLoc(N), 460 MVT::i32); 461}]>; 462def DSubReg_i32_reg : SDNodeXForm<imm, [{ 463 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); 464 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, SDLoc(N), 465 MVT::i32); 466}]>; 467def DSubReg_f64_reg : SDNodeXForm<imm, [{ 468 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); 469 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), SDLoc(N), 470 MVT::i32); 471}]>; 472 473// Extract S sub-registers of Q/D registers. 474def SSubReg_f32_reg : SDNodeXForm<imm, [{ 475 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering"); 476 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), SDLoc(N), 477 MVT::i32); 478}]>; 479 480// Extract S sub-registers of Q/D registers containing a given f16/bf16 lane. 481def SSubReg_f16_reg : SDNodeXForm<imm, [{ 482 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering"); 483 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue()/2, SDLoc(N), 484 MVT::i32); 485}]>; 486 487// Translate lane numbers from Q registers to D subregs. 488def SubReg_i8_lane : SDNodeXForm<imm, [{ 489 return CurDAG->getTargetConstant(N->getZExtValue() & 7, SDLoc(N), MVT::i32); 490}]>; 491def SubReg_i16_lane : SDNodeXForm<imm, [{ 492 return CurDAG->getTargetConstant(N->getZExtValue() & 3, SDLoc(N), MVT::i32); 493}]>; 494def SubReg_i32_lane : SDNodeXForm<imm, [{ 495 return CurDAG->getTargetConstant(N->getZExtValue() & 1, SDLoc(N), MVT::i32); 496}]>; 497 498 499def ARMimmAllZerosV: PatLeaf<(bitconvert (v4i32 (ARMvmovImm (i32 0))))>; 500def ARMimmAllZerosD: PatLeaf<(bitconvert (v2i32 (ARMvmovImm (i32 0))))>; 501def ARMimmAllOnesV: PatLeaf<(bitconvert (v16i8 (ARMvmovImm (i32 0xEFF))))>; 502def ARMimmAllOnesD: PatLeaf<(bitconvert (v8i8 (ARMvmovImm (i32 0xEFF))))>; 503 504def ARMimmOneV: PatLeaf<(ARMvmovImm (i32 timm)), [{ 505 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0)); 506 unsigned EltBits = 0; 507 uint64_t EltVal = ARM_AM::decodeVMOVModImm(ConstVal->getZExtValue(), EltBits); 508 return (EltBits == N->getValueType(0).getScalarSizeInBits() && EltVal == 0x01); 509}]>; 510 511 512//===----------------------------------------------------------------------===// 513// Operand Definitions. 514// 515 516// Immediate operands with a shared generic asm render method. 517class ImmAsmOperand<int Low, int High> : AsmOperandClass { 518 let RenderMethod = "addImmOperands"; 519 let PredicateMethod = "isImmediate<" # Low # "," # High # ">"; 520 let DiagnosticString = "operand must be an immediate in the range [" # Low # "," # High # "]"; 521} 522 523class ImmAsmOperandMinusOne<int Low, int High> : AsmOperandClass { 524 let PredicateMethod = "isImmediate<" # Low # "," # High # ">"; 525 let DiagnosticType = "ImmRange" # Low # "_" # High; 526 let DiagnosticString = "operand must be an immediate in the range [" # Low # "," # High # "]"; 527} 528 529// Operands that are part of a memory addressing mode. 530class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; } 531 532// Branch target. 533// FIXME: rename brtarget to t2_brtarget 534def brtarget : Operand<OtherVT> { 535 let EncoderMethod = "getBranchTargetOpValue"; 536 let OperandType = "OPERAND_PCREL"; 537 let DecoderMethod = "DecodeT2BROperand"; 538} 539 540// Branches targeting ARM-mode must be divisible by 4 if they're a raw 541// immediate. 542def ARMBranchTarget : AsmOperandClass { 543 let Name = "ARMBranchTarget"; 544} 545 546// Branches targeting Thumb-mode must be divisible by 2 if they're a raw 547// immediate. 548def ThumbBranchTarget : AsmOperandClass { 549 let Name = "ThumbBranchTarget"; 550} 551 552def arm_br_target : Operand<OtherVT> { 553 let ParserMatchClass = ARMBranchTarget; 554 let EncoderMethod = "getARMBranchTargetOpValue"; 555 let OperandType = "OPERAND_PCREL"; 556} 557 558// Call target for ARM. Handles conditional/unconditional 559// FIXME: rename bl_target to t2_bltarget? 560def arm_bl_target : Operand<i32> { 561 let ParserMatchClass = ARMBranchTarget; 562 let EncoderMethod = "getARMBLTargetOpValue"; 563 let OperandType = "OPERAND_PCREL"; 564} 565 566// Target for BLX *from* ARM mode. 567def arm_blx_target : Operand<i32> { 568 let ParserMatchClass = ThumbBranchTarget; 569 let EncoderMethod = "getARMBLXTargetOpValue"; 570 let OperandType = "OPERAND_PCREL"; 571} 572 573// A list of registers separated by comma. Used by load/store multiple. 574def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; } 575def reglist : Operand<i32> { 576 let EncoderMethod = "getRegisterListOpValue"; 577 let ParserMatchClass = RegListAsmOperand; 578 let PrintMethod = "printRegisterList"; 579 let DecoderMethod = "DecodeRegListOperand"; 580} 581 582// A list of general purpose registers and APSR separated by comma. 583// Used by CLRM 584def RegListWithAPSRAsmOperand : AsmOperandClass { let Name = "RegListWithAPSR"; } 585def reglist_with_apsr : Operand<i32> { 586 let EncoderMethod = "getRegisterListOpValue"; 587 let ParserMatchClass = RegListWithAPSRAsmOperand; 588 let PrintMethod = "printRegisterList"; 589 let DecoderMethod = "DecodeRegListOperand"; 590} 591 592def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">; 593 594def DPRRegListAsmOperand : AsmOperandClass { 595 let Name = "DPRRegList"; 596 let DiagnosticType = "DPR_RegList"; 597} 598def dpr_reglist : Operand<i32> { 599 let EncoderMethod = "getRegisterListOpValue"; 600 let ParserMatchClass = DPRRegListAsmOperand; 601 let PrintMethod = "printRegisterList"; 602 let DecoderMethod = "DecodeDPRRegListOperand"; 603} 604 605def SPRRegListAsmOperand : AsmOperandClass { 606 let Name = "SPRRegList"; 607 let DiagnosticString = "operand must be a list of registers in range [s0, s31]"; 608} 609def spr_reglist : Operand<i32> { 610 let EncoderMethod = "getRegisterListOpValue"; 611 let ParserMatchClass = SPRRegListAsmOperand; 612 let PrintMethod = "printRegisterList"; 613 let DecoderMethod = "DecodeSPRRegListOperand"; 614} 615 616def FPSRegListWithVPRAsmOperand : AsmOperandClass { let Name = 617 "FPSRegListWithVPR"; } 618def fp_sreglist_with_vpr : Operand<i32> { 619 let EncoderMethod = "getRegisterListOpValue"; 620 let ParserMatchClass = FPSRegListWithVPRAsmOperand; 621 let PrintMethod = "printRegisterList"; 622} 623def FPDRegListWithVPRAsmOperand : AsmOperandClass { let Name = 624 "FPDRegListWithVPR"; } 625def fp_dreglist_with_vpr : Operand<i32> { 626 let EncoderMethod = "getRegisterListOpValue"; 627 let ParserMatchClass = FPDRegListWithVPRAsmOperand; 628 let PrintMethod = "printRegisterList"; 629} 630 631// An operand for the CONSTPOOL_ENTRY pseudo-instruction. 632def cpinst_operand : Operand<i32> { 633 let PrintMethod = "printCPInstOperand"; 634} 635 636// Local PC labels. 637def pclabel : Operand<i32> { 638 let PrintMethod = "printPCLabel"; 639} 640 641// ADR instruction labels. 642def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; } 643def adrlabel : Operand<i32> { 644 let EncoderMethod = "getAdrLabelOpValue"; 645 let ParserMatchClass = AdrLabelAsmOperand; 646 let PrintMethod = "printAdrLabelOperand<0>"; 647} 648 649def neon_vcvt_imm32 : Operand<i32> { 650 let EncoderMethod = "getNEONVcvtImm32OpValue"; 651 let DecoderMethod = "DecodeVCVTImmOperand"; 652} 653 654// rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24. 655def rot_imm_XFORM: SDNodeXForm<imm, [{ 656 switch (N->getZExtValue()){ 657 default: llvm_unreachable(nullptr); 658 case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32); 659 case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32); 660 case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32); 661 case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32); 662 } 663}]>; 664def RotImmAsmOperand : AsmOperandClass { 665 let Name = "RotImm"; 666 let ParserMethod = "parseRotImm"; 667} 668def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{ 669 int32_t v = N->getZExtValue(); 670 return v == 8 || v == 16 || v == 24; }], 671 rot_imm_XFORM> { 672 let PrintMethod = "printRotImmOperand"; 673 let ParserMatchClass = RotImmAsmOperand; 674} 675 676// Power-of-two operand for MVE VIDUP and friends, which encode 677// {1,2,4,8} as its log to base 2, i.e. as {0,1,2,3} respectively 678def MVE_VIDUP_imm_asmoperand : AsmOperandClass { 679 let Name = "VIDUP_imm"; 680 let PredicateMethod = "isPowerTwoInRange<1,8>"; 681 let RenderMethod = "addPowerTwoOperands"; 682 let DiagnosticString = "vector increment immediate must be 1, 2, 4 or 8"; 683} 684def MVE_VIDUP_imm : Operand<i32> { 685 let EncoderMethod = "getPowerTwoOpValue"; 686 let DecoderMethod = "DecodePowerTwoOperand<0,3>"; 687 let ParserMatchClass = MVE_VIDUP_imm_asmoperand; 688} 689 690// Pair vector indexing 691class MVEPairVectorIndexOperand<string start, string end> : AsmOperandClass { 692 let Name = "MVEPairVectorIndex"#start; 693 let RenderMethod = "addMVEPairVectorIndexOperands"; 694 let PredicateMethod = "isMVEPairVectorIndex<"#start#", "#end#">"; 695} 696 697class MVEPairVectorIndex<string opval> : Operand<i32> { 698 let PrintMethod = "printVectorIndex"; 699 let EncoderMethod = "getMVEPairVectorIndexOpValue<"#opval#">"; 700 let DecoderMethod = "DecodeMVEPairVectorIndexOperand<"#opval#">"; 701 let MIOperandInfo = (ops i32imm); 702} 703 704def MVEPairVectorIndex0 : MVEPairVectorIndex<"0"> { 705 let ParserMatchClass = MVEPairVectorIndexOperand<"0", "1">; 706} 707 708def MVEPairVectorIndex2 : MVEPairVectorIndex<"2"> { 709 let ParserMatchClass = MVEPairVectorIndexOperand<"2", "3">; 710} 711 712// Vector indexing 713class MVEVectorIndexOperand<int NumLanes> : AsmOperandClass { 714 let Name = "MVEVectorIndex"#NumLanes; 715 let RenderMethod = "addMVEVectorIndexOperands"; 716 let PredicateMethod = "isVectorIndexInRange<"#NumLanes#">"; 717} 718 719class MVEVectorIndex<int NumLanes> : Operand<i32> { 720 let PrintMethod = "printVectorIndex"; 721 let ParserMatchClass = MVEVectorIndexOperand<NumLanes>; 722 let MIOperandInfo = (ops i32imm); 723} 724 725// shift_imm: An integer that encodes a shift amount and the type of shift 726// (asr or lsl). The 6-bit immediate encodes as: 727// {5} 0 ==> lsl 728// 1 asr 729// {4-0} imm5 shift amount. 730// asr #32 encoded as imm5 == 0. 731def ShifterImmAsmOperand : AsmOperandClass { 732 let Name = "ShifterImm"; 733 let ParserMethod = "parseShifterImm"; 734} 735def shift_imm : Operand<i32> { 736 let PrintMethod = "printShiftImmOperand"; 737 let ParserMatchClass = ShifterImmAsmOperand; 738} 739 740// shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm. 741def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; } 742def so_reg_reg : Operand<i32>, // reg reg imm 743 ComplexPattern<i32, 3, "SelectRegShifterOperand", 744 [shl, srl, sra, rotr]> { 745 let EncoderMethod = "getSORegRegOpValue"; 746 let PrintMethod = "printSORegRegOperand"; 747 let DecoderMethod = "DecodeSORegRegOperand"; 748 let ParserMatchClass = ShiftedRegAsmOperand; 749 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm); 750} 751 752def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; } 753def so_reg_imm : Operand<i32>, // reg imm 754 ComplexPattern<i32, 2, "SelectImmShifterOperand", 755 [shl, srl, sra, rotr]> { 756 let EncoderMethod = "getSORegImmOpValue"; 757 let PrintMethod = "printSORegImmOperand"; 758 let DecoderMethod = "DecodeSORegImmOperand"; 759 let ParserMatchClass = ShiftedImmAsmOperand; 760 let MIOperandInfo = (ops GPR, i32imm); 761} 762 763// FIXME: Does this need to be distinct from so_reg? 764def shift_so_reg_reg : Operand<i32>, // reg reg imm 765 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand", 766 [shl,srl,sra,rotr]> { 767 let EncoderMethod = "getSORegRegOpValue"; 768 let PrintMethod = "printSORegRegOperand"; 769 let DecoderMethod = "DecodeSORegRegOperand"; 770 let ParserMatchClass = ShiftedRegAsmOperand; 771 let MIOperandInfo = (ops GPR, GPR, i32imm); 772} 773 774// FIXME: Does this need to be distinct from so_reg? 775def shift_so_reg_imm : Operand<i32>, // reg reg imm 776 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand", 777 [shl,srl,sra,rotr]> { 778 let EncoderMethod = "getSORegImmOpValue"; 779 let PrintMethod = "printSORegImmOperand"; 780 let DecoderMethod = "DecodeSORegImmOperand"; 781 let ParserMatchClass = ShiftedImmAsmOperand; 782 let MIOperandInfo = (ops GPR, i32imm); 783} 784 785// mod_imm: match a 32-bit immediate operand, which can be encoded into 786// a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM 787// - "Modified Immediate Constants"). Within the MC layer we keep this 788// immediate in its encoded form. 789def ModImmAsmOperand: AsmOperandClass { 790 let Name = "ModImm"; 791 let ParserMethod = "parseModImm"; 792} 793def mod_imm : Operand<i32>, ImmLeaf<i32, [{ 794 return ARM_AM::getSOImmVal(Imm) != -1; 795 }]> { 796 let EncoderMethod = "getModImmOpValue"; 797 let PrintMethod = "printModImmOperand"; 798 let ParserMatchClass = ModImmAsmOperand; 799} 800 801// Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder 802// method and such, as they are only used on aliases (Pat<> and InstAlias<>). 803// The actual parsing, encoding, decoding are handled by the destination 804// instructions, which use mod_imm. 805 806def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; } 807def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{ 808 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1; 809 }], imm_not_XFORM> { 810 let ParserMatchClass = ModImmNotAsmOperand; 811} 812 813def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; } 814def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{ 815 unsigned Value = -(unsigned)N->getZExtValue(); 816 return Value && ARM_AM::getSOImmVal(Value) != -1; 817 }], imm_neg_XFORM> { 818 let ParserMatchClass = ModImmNegAsmOperand; 819} 820 821/// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal() 822def arm_i32imm : IntImmLeaf<i32, [{ 823 if (Subtarget->useMovt()) 824 return true; 825 if (ARM_AM::isSOImmTwoPartVal(Imm.getZExtValue())) 826 return true; 827 return ARM_AM::isSOImmTwoPartValNeg(Imm.getZExtValue()); 828}]>; 829 830/// imm0_1 predicate - Immediate in the range [0,1]. 831def Imm0_1AsmOperand: ImmAsmOperand<0,1> { let Name = "Imm0_1"; } 832def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; } 833 834/// imm0_3 predicate - Immediate in the range [0,3]. 835def Imm0_3AsmOperand: ImmAsmOperand<0,3> { let Name = "Imm0_3"; } 836def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; } 837 838/// imm0_7 predicate - Immediate in the range [0,7]. 839def Imm0_7AsmOperand: ImmAsmOperand<0,7> { 840 let Name = "Imm0_7"; 841} 842def imm0_7 : Operand<i32>, ImmLeaf<i32, [{ 843 return Imm >= 0 && Imm < 8; 844}]> { 845 let ParserMatchClass = Imm0_7AsmOperand; 846} 847 848/// imm8_255 predicate - Immediate in the range [8,255]. 849def Imm8_255AsmOperand: ImmAsmOperand<8,255> { let Name = "Imm8_255"; } 850def imm8_255 : Operand<i32>, ImmLeaf<i32, [{ 851 return Imm >= 8 && Imm < 256; 852}]> { 853 let ParserMatchClass = Imm8_255AsmOperand; 854} 855 856/// imm8 predicate - Immediate is exactly 8. 857def Imm8AsmOperand: ImmAsmOperand<8,8> { let Name = "Imm8"; } 858def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> { 859 let ParserMatchClass = Imm8AsmOperand; 860} 861 862/// imm16 predicate - Immediate is exactly 16. 863def Imm16AsmOperand: ImmAsmOperand<16,16> { let Name = "Imm16"; } 864def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> { 865 let ParserMatchClass = Imm16AsmOperand; 866} 867 868/// imm32 predicate - Immediate is exactly 32. 869def Imm32AsmOperand: ImmAsmOperand<32,32> { let Name = "Imm32"; } 870def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> { 871 let ParserMatchClass = Imm32AsmOperand; 872} 873 874def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>; 875 876/// imm1_7 predicate - Immediate in the range [1,7]. 877def Imm1_7AsmOperand: ImmAsmOperand<1,7> { let Name = "Imm1_7"; } 878def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> { 879 let ParserMatchClass = Imm1_7AsmOperand; 880} 881 882/// imm1_15 predicate - Immediate in the range [1,15]. 883def Imm1_15AsmOperand: ImmAsmOperand<1,15> { let Name = "Imm1_15"; } 884def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> { 885 let ParserMatchClass = Imm1_15AsmOperand; 886} 887 888/// imm1_31 predicate - Immediate in the range [1,31]. 889def Imm1_31AsmOperand: ImmAsmOperand<1,31> { let Name = "Imm1_31"; } 890def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> { 891 let ParserMatchClass = Imm1_31AsmOperand; 892} 893 894/// imm0_15 predicate - Immediate in the range [0,15]. 895def Imm0_15AsmOperand: ImmAsmOperand<0,15> { 896 let Name = "Imm0_15"; 897} 898def imm0_15 : Operand<i32>, ImmLeaf<i32, [{ 899 return Imm >= 0 && Imm < 16; 900}]> { 901 let ParserMatchClass = Imm0_15AsmOperand; 902} 903 904/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31]. 905def Imm0_31AsmOperand: ImmAsmOperand<0,31> { let Name = "Imm0_31"; } 906def imm0_31 : Operand<i32>, ImmLeaf<i32, [{ 907 return Imm >= 0 && Imm < 32; 908}]> { 909 let ParserMatchClass = Imm0_31AsmOperand; 910} 911 912/// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32]. 913def Imm0_32AsmOperand: ImmAsmOperand<0,32> { let Name = "Imm0_32"; } 914def imm0_32 : Operand<i32>, ImmLeaf<i32, [{ 915 return Imm >= 0 && Imm < 33; 916}]> { 917 let ParserMatchClass = Imm0_32AsmOperand; 918} 919 920/// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63]. 921def Imm0_63AsmOperand: ImmAsmOperand<0,63> { let Name = "Imm0_63"; } 922def imm0_63 : Operand<i32>, ImmLeaf<i32, [{ 923 return Imm >= 0 && Imm < 64; 924}]> { 925 let ParserMatchClass = Imm0_63AsmOperand; 926} 927 928/// imm0_239 predicate - Immediate in the range [0,239]. 929def Imm0_239AsmOperand : ImmAsmOperand<0,239> { 930 let Name = "Imm0_239"; 931} 932def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> { 933 let ParserMatchClass = Imm0_239AsmOperand; 934} 935 936/// imm0_255 predicate - Immediate in the range [0,255]. 937def Imm0_255AsmOperand : ImmAsmOperand<0,255> { let Name = "Imm0_255"; } 938def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> { 939 let ParserMatchClass = Imm0_255AsmOperand; 940} 941 942/// imm0_65535 - An immediate is in the range [0,65535]. 943def Imm0_65535AsmOperand: ImmAsmOperand<0,65535> { let Name = "Imm0_65535"; } 944def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{ 945 return Imm >= 0 && Imm < 65536; 946}]> { 947 let ParserMatchClass = Imm0_65535AsmOperand; 948} 949 950// imm0_65535_neg - An immediate whose negative value is in the range [0.65535]. 951def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{ 952 return -Imm >= 0 && -Imm < 65536; 953}]>; 954 955// imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference 956// a relocatable expression. 957// 958// FIXME: This really needs a Thumb version separate from the ARM version. 959// While the range is the same, and can thus use the same match class, 960// the encoding is different so it should have a different encoder method. 961def Imm0_65535ExprAsmOperand: AsmOperandClass { 962 let Name = "Imm0_65535Expr"; 963 let RenderMethod = "addImmOperands"; 964 let DiagnosticString = "operand must be an immediate in the range [0,0xffff] or a relocatable expression"; 965} 966 967def imm0_65535_expr : Operand<i32> { 968 let EncoderMethod = "getHiLo16ImmOpValue"; 969 let ParserMatchClass = Imm0_65535ExprAsmOperand; 970} 971 972def Imm256_65535ExprAsmOperand: ImmAsmOperand<256,65535> { let Name = "Imm256_65535Expr"; } 973def imm256_65535_expr : Operand<i32> { 974 let ParserMatchClass = Imm256_65535ExprAsmOperand; 975} 976 977/// imm24b - True if the 32-bit immediate is encodable in 24 bits. 978def Imm24bitAsmOperand: ImmAsmOperand<0,0xffffff> { 979 let Name = "Imm24bit"; 980 let DiagnosticString = "operand must be an immediate in the range [0,0xffffff]"; 981} 982def imm24b : Operand<i32>, ImmLeaf<i32, [{ 983 return Imm >= 0 && Imm <= 0xffffff; 984}]> { 985 let ParserMatchClass = Imm24bitAsmOperand; 986} 987 988 989/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield 990/// e.g., 0xf000ffff 991def BitfieldAsmOperand : AsmOperandClass { 992 let Name = "Bitfield"; 993 let ParserMethod = "parseBitfield"; 994} 995 996def bf_inv_mask_imm : Operand<i32>, 997 PatLeaf<(imm), [{ 998 return ARM::isBitFieldInvertedMask(N->getZExtValue()); 999}] > { 1000 let EncoderMethod = "getBitfieldInvertedMaskOpValue"; 1001 let PrintMethod = "printBitfieldInvMaskImmOperand"; 1002 let DecoderMethod = "DecodeBitfieldMaskOperand"; 1003 let ParserMatchClass = BitfieldAsmOperand; 1004 let GISelPredicateCode = [{ 1005 // There's better methods of implementing this check. IntImmLeaf<> would be 1006 // equivalent and have less boilerplate but we need a test for C++ 1007 // predicates and this one causes new rules to be imported into GlobalISel 1008 // without requiring additional features first. 1009 const auto &MO = MI.getOperand(1); 1010 if (!MO.isCImm()) 1011 return false; 1012 return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue()); 1013 }]; 1014} 1015 1016def imm1_32_XFORM: SDNodeXForm<imm, [{ 1017 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), 1018 MVT::i32); 1019}]>; 1020def Imm1_32AsmOperand: ImmAsmOperandMinusOne<1,32> { 1021 let Name = "Imm1_32"; 1022} 1023def imm1_32 : Operand<i32>, PatLeaf<(imm), [{ 1024 uint64_t Imm = N->getZExtValue(); 1025 return Imm > 0 && Imm <= 32; 1026 }], 1027 imm1_32_XFORM> { 1028 let PrintMethod = "printImmPlusOneOperand"; 1029 let ParserMatchClass = Imm1_32AsmOperand; 1030} 1031 1032def imm1_16_XFORM: SDNodeXForm<imm, [{ 1033 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), 1034 MVT::i32); 1035}]>; 1036def Imm1_16AsmOperand: ImmAsmOperandMinusOne<1,16> { let Name = "Imm1_16"; } 1037def imm1_16 : Operand<i32>, ImmLeaf<i32, [{ 1038 return Imm > 0 && Imm <= 16; 1039 }], 1040 imm1_16_XFORM> { 1041 let PrintMethod = "printImmPlusOneOperand"; 1042 let ParserMatchClass = Imm1_16AsmOperand; 1043} 1044 1045def MVEShiftImm1_7AsmOperand: ImmAsmOperand<1,7> { 1046 let Name = "MVEShiftImm1_7"; 1047 // Reason we're doing this is because instruction vshll.s8 t1 encoding 1048 // accepts 1,7 but the t2 encoding accepts 8. By doing this we can get a 1049 // better diagnostic message if someone uses bigger immediate than the t1/t2 1050 // encodings allow. 1051 let DiagnosticString = "operand must be an immediate in the range [1,8]"; 1052} 1053def mve_shift_imm1_7 : Operand<i32>, 1054 // SelectImmediateInRange / isScaledConstantInRange uses a 1055 // half-open interval, so the parameters <1,8> mean 1-7 inclusive 1056 ComplexPattern<i32, 1, "SelectImmediateInRange<1,8>", [], []> { 1057 let ParserMatchClass = MVEShiftImm1_7AsmOperand; 1058 let EncoderMethod = "getMVEShiftImmOpValue"; 1059} 1060 1061def MVEShiftImm1_15AsmOperand: ImmAsmOperand<1,15> { 1062 let Name = "MVEShiftImm1_15"; 1063 // Reason we're doing this is because instruction vshll.s16 t1 encoding 1064 // accepts 1,15 but the t2 encoding accepts 16. By doing this we can get a 1065 // better diagnostic message if someone uses bigger immediate than the t1/t2 1066 // encodings allow. 1067 let DiagnosticString = "operand must be an immediate in the range [1,16]"; 1068} 1069def mve_shift_imm1_15 : Operand<i32>, 1070 // SelectImmediateInRange / isScaledConstantInRange uses a 1071 // half-open interval, so the parameters <1,16> mean 1-15 inclusive 1072 ComplexPattern<i32, 1, "SelectImmediateInRange<1,16>", [], []> { 1073 let ParserMatchClass = MVEShiftImm1_15AsmOperand; 1074 let EncoderMethod = "getMVEShiftImmOpValue"; 1075} 1076 1077// Define ARM specific addressing modes. 1078// addrmode_imm12 := reg +/- imm12 1079// 1080def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; } 1081class AddrMode_Imm12 : MemOperand, 1082 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> { 1083 // 12-bit immediate operand. Note that instructions using this encode 1084 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other 1085 // immediate values are as normal. 1086 1087 let EncoderMethod = "getAddrModeImm12OpValue"; 1088 let DecoderMethod = "DecodeAddrModeImm12Operand"; 1089 let ParserMatchClass = MemImm12OffsetAsmOperand; 1090 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 1091} 1092 1093def addrmode_imm12 : AddrMode_Imm12 { 1094 let PrintMethod = "printAddrModeImm12Operand<false>"; 1095} 1096 1097def addrmode_imm12_pre : AddrMode_Imm12 { 1098 let PrintMethod = "printAddrModeImm12Operand<true>"; 1099} 1100 1101// ldst_so_reg := reg +/- reg shop imm 1102// 1103def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; } 1104def ldst_so_reg : MemOperand, 1105 ComplexPattern<i32, 3, "SelectLdStSOReg", []> { 1106 let EncoderMethod = "getLdStSORegOpValue"; 1107 // FIXME: Simplify the printer 1108 let PrintMethod = "printAddrMode2Operand"; 1109 let DecoderMethod = "DecodeSORegMemOperand"; 1110 let ParserMatchClass = MemRegOffsetAsmOperand; 1111 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift); 1112} 1113 1114// postidx_imm8 := +/- [0,255] 1115// 1116// 9 bit value: 1117// {8} 1 is imm8 is non-negative. 0 otherwise. 1118// {7-0} [0,255] imm8 value. 1119def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; } 1120def postidx_imm8 : MemOperand { 1121 let PrintMethod = "printPostIdxImm8Operand"; 1122 let ParserMatchClass = PostIdxImm8AsmOperand; 1123 let MIOperandInfo = (ops i32imm); 1124} 1125 1126// postidx_imm8s4 := +/- [0,1020] 1127// 1128// 9 bit value: 1129// {8} 1 is imm8 is non-negative. 0 otherwise. 1130// {7-0} [0,255] imm8 value, scaled by 4. 1131def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; } 1132def postidx_imm8s4 : MemOperand { 1133 let PrintMethod = "printPostIdxImm8s4Operand"; 1134 let ParserMatchClass = PostIdxImm8s4AsmOperand; 1135 let MIOperandInfo = (ops i32imm); 1136} 1137 1138 1139// postidx_reg := +/- reg 1140// 1141def PostIdxRegAsmOperand : AsmOperandClass { 1142 let Name = "PostIdxReg"; 1143 let ParserMethod = "parsePostIdxReg"; 1144} 1145def postidx_reg : MemOperand { 1146 let EncoderMethod = "getPostIdxRegOpValue"; 1147 let DecoderMethod = "DecodePostIdxReg"; 1148 let PrintMethod = "printPostIdxRegOperand"; 1149 let ParserMatchClass = PostIdxRegAsmOperand; 1150 let MIOperandInfo = (ops GPRnopc, i32imm); 1151} 1152 1153def PostIdxRegShiftedAsmOperand : AsmOperandClass { 1154 let Name = "PostIdxRegShifted"; 1155 let ParserMethod = "parsePostIdxReg"; 1156} 1157def am2offset_reg : MemOperand, 1158 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg", 1159 [], [SDNPWantRoot]> { 1160 let EncoderMethod = "getAddrMode2OffsetOpValue"; 1161 let PrintMethod = "printAddrMode2OffsetOperand"; 1162 // When using this for assembly, it's always as a post-index offset. 1163 let ParserMatchClass = PostIdxRegShiftedAsmOperand; 1164 let MIOperandInfo = (ops GPRnopc, i32imm); 1165} 1166 1167// FIXME: am2offset_imm should only need the immediate, not the GPR. Having 1168// the GPR is purely vestigal at this point. 1169def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; } 1170def am2offset_imm : MemOperand, 1171 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm", 1172 [], [SDNPWantRoot]> { 1173 let EncoderMethod = "getAddrMode2OffsetOpValue"; 1174 let PrintMethod = "printAddrMode2OffsetOperand"; 1175 let ParserMatchClass = AM2OffsetImmAsmOperand; 1176 let MIOperandInfo = (ops GPRnopc, i32imm); 1177} 1178 1179 1180// addrmode3 := reg +/- reg 1181// addrmode3 := reg +/- imm8 1182// 1183// FIXME: split into imm vs. reg versions. 1184def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; } 1185class AddrMode3 : MemOperand, 1186 ComplexPattern<i32, 3, "SelectAddrMode3", []> { 1187 let EncoderMethod = "getAddrMode3OpValue"; 1188 let ParserMatchClass = AddrMode3AsmOperand; 1189 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 1190} 1191 1192def addrmode3 : AddrMode3 1193{ 1194 let PrintMethod = "printAddrMode3Operand<false>"; 1195} 1196 1197def addrmode3_pre : AddrMode3 1198{ 1199 let PrintMethod = "printAddrMode3Operand<true>"; 1200} 1201 1202// FIXME: split into imm vs. reg versions. 1203// FIXME: parser method to handle +/- register. 1204def AM3OffsetAsmOperand : AsmOperandClass { 1205 let Name = "AM3Offset"; 1206 let ParserMethod = "parseAM3Offset"; 1207} 1208def am3offset : MemOperand, 1209 ComplexPattern<i32, 2, "SelectAddrMode3Offset", 1210 [], [SDNPWantRoot]> { 1211 let EncoderMethod = "getAddrMode3OffsetOpValue"; 1212 let PrintMethod = "printAddrMode3OffsetOperand"; 1213 let ParserMatchClass = AM3OffsetAsmOperand; 1214 let MIOperandInfo = (ops GPR, i32imm); 1215} 1216 1217// ldstm_mode := {ia, ib, da, db} 1218// 1219def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> { 1220 let EncoderMethod = "getLdStmModeOpValue"; 1221 let PrintMethod = "printLdStmModeOperand"; 1222} 1223 1224// addrmode5 := reg +/- imm8*4 1225// 1226def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; } 1227class AddrMode5 : MemOperand, 1228 ComplexPattern<i32, 2, "SelectAddrMode5", []> { 1229 let EncoderMethod = "getAddrMode5OpValue"; 1230 let DecoderMethod = "DecodeAddrMode5Operand"; 1231 let ParserMatchClass = AddrMode5AsmOperand; 1232 let MIOperandInfo = (ops GPR:$base, i32imm); 1233} 1234 1235def addrmode5 : AddrMode5 { 1236 let PrintMethod = "printAddrMode5Operand<false>"; 1237} 1238 1239def addrmode5_pre : AddrMode5 { 1240 let PrintMethod = "printAddrMode5Operand<true>"; 1241} 1242 1243// addrmode5fp16 := reg +/- imm8*2 1244// 1245def AddrMode5FP16AsmOperand : AsmOperandClass { let Name = "AddrMode5FP16"; } 1246class AddrMode5FP16 : Operand<i32>, 1247 ComplexPattern<i32, 2, "SelectAddrMode5FP16", []> { 1248 let EncoderMethod = "getAddrMode5FP16OpValue"; 1249 let DecoderMethod = "DecodeAddrMode5FP16Operand"; 1250 let ParserMatchClass = AddrMode5FP16AsmOperand; 1251 let MIOperandInfo = (ops GPR:$base, i32imm); 1252} 1253 1254def addrmode5fp16 : AddrMode5FP16 { 1255 let PrintMethod = "printAddrMode5FP16Operand<false>"; 1256} 1257 1258// addrmode6 := reg with optional alignment 1259// 1260def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; } 1261def addrmode6 : MemOperand, 1262 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1263 let PrintMethod = "printAddrMode6Operand"; 1264 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 1265 let EncoderMethod = "getAddrMode6AddressOpValue"; 1266 let DecoderMethod = "DecodeAddrMode6Operand"; 1267 let ParserMatchClass = AddrMode6AsmOperand; 1268} 1269 1270def am6offset : MemOperand, 1271 ComplexPattern<i32, 1, "SelectAddrMode6Offset", 1272 [], [SDNPWantRoot]> { 1273 let PrintMethod = "printAddrMode6OffsetOperand"; 1274 let MIOperandInfo = (ops GPR); 1275 let EncoderMethod = "getAddrMode6OffsetOpValue"; 1276 let DecoderMethod = "DecodeGPRRegisterClass"; 1277} 1278 1279// Special version of addrmode6 to handle alignment encoding for VST1/VLD1 1280// (single element from one lane) for size 32. 1281def addrmode6oneL32 : MemOperand, 1282 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1283 let PrintMethod = "printAddrMode6Operand"; 1284 let MIOperandInfo = (ops GPR:$addr, i32imm); 1285 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue"; 1286} 1287 1288// Base class for addrmode6 with specific alignment restrictions. 1289class AddrMode6Align : MemOperand, 1290 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1291 let PrintMethod = "printAddrMode6Operand"; 1292 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 1293 let EncoderMethod = "getAddrMode6AddressOpValue"; 1294 let DecoderMethod = "DecodeAddrMode6Operand"; 1295} 1296 1297// Special version of addrmode6 to handle no allowed alignment encoding for 1298// VLD/VST instructions and checking the alignment is not specified. 1299def AddrMode6AlignNoneAsmOperand : AsmOperandClass { 1300 let Name = "AlignedMemoryNone"; 1301 let DiagnosticString = "alignment must be omitted"; 1302} 1303def addrmode6alignNone : AddrMode6Align { 1304 // The alignment specifier can only be omitted. 1305 let ParserMatchClass = AddrMode6AlignNoneAsmOperand; 1306} 1307 1308// Special version of addrmode6 to handle 16-bit alignment encoding for 1309// VLD/VST instructions and checking the alignment value. 1310def AddrMode6Align16AsmOperand : AsmOperandClass { 1311 let Name = "AlignedMemory16"; 1312 let DiagnosticString = "alignment must be 16 or omitted"; 1313} 1314def addrmode6align16 : AddrMode6Align { 1315 // The alignment specifier can only be 16 or omitted. 1316 let ParserMatchClass = AddrMode6Align16AsmOperand; 1317} 1318 1319// Special version of addrmode6 to handle 32-bit alignment encoding for 1320// VLD/VST instructions and checking the alignment value. 1321def AddrMode6Align32AsmOperand : AsmOperandClass { 1322 let Name = "AlignedMemory32"; 1323 let DiagnosticString = "alignment must be 32 or omitted"; 1324} 1325def addrmode6align32 : AddrMode6Align { 1326 // The alignment specifier can only be 32 or omitted. 1327 let ParserMatchClass = AddrMode6Align32AsmOperand; 1328} 1329 1330// Special version of addrmode6 to handle 64-bit alignment encoding for 1331// VLD/VST instructions and checking the alignment value. 1332def AddrMode6Align64AsmOperand : AsmOperandClass { 1333 let Name = "AlignedMemory64"; 1334 let DiagnosticString = "alignment must be 64 or omitted"; 1335} 1336def addrmode6align64 : AddrMode6Align { 1337 // The alignment specifier can only be 64 or omitted. 1338 let ParserMatchClass = AddrMode6Align64AsmOperand; 1339} 1340 1341// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1342// for VLD/VST instructions and checking the alignment value. 1343def AddrMode6Align64or128AsmOperand : AsmOperandClass { 1344 let Name = "AlignedMemory64or128"; 1345 let DiagnosticString = "alignment must be 64, 128 or omitted"; 1346} 1347def addrmode6align64or128 : AddrMode6Align { 1348 // The alignment specifier can only be 64, 128 or omitted. 1349 let ParserMatchClass = AddrMode6Align64or128AsmOperand; 1350} 1351 1352// Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment 1353// encoding for VLD/VST instructions and checking the alignment value. 1354def AddrMode6Align64or128or256AsmOperand : AsmOperandClass { 1355 let Name = "AlignedMemory64or128or256"; 1356 let DiagnosticString = "alignment must be 64, 128, 256 or omitted"; 1357} 1358def addrmode6align64or128or256 : AddrMode6Align { 1359 // The alignment specifier can only be 64, 128, 256 or omitted. 1360 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand; 1361} 1362 1363// Special version of addrmode6 to handle alignment encoding for VLD-dup 1364// instructions, specifically VLD4-dup. 1365def addrmode6dup : MemOperand, 1366 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1367 let PrintMethod = "printAddrMode6Operand"; 1368 let MIOperandInfo = (ops GPR:$addr, i32imm); 1369 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1370 // FIXME: This is close, but not quite right. The alignment specifier is 1371 // different. 1372 let ParserMatchClass = AddrMode6AsmOperand; 1373} 1374 1375// Base class for addrmode6dup with specific alignment restrictions. 1376class AddrMode6DupAlign : MemOperand, 1377 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1378 let PrintMethod = "printAddrMode6Operand"; 1379 let MIOperandInfo = (ops GPR:$addr, i32imm); 1380 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1381} 1382 1383// Special version of addrmode6 to handle no allowed alignment encoding for 1384// VLD-dup instruction and checking the alignment is not specified. 1385def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass { 1386 let Name = "DupAlignedMemoryNone"; 1387 let DiagnosticString = "alignment must be omitted"; 1388} 1389def addrmode6dupalignNone : AddrMode6DupAlign { 1390 // The alignment specifier can only be omitted. 1391 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand; 1392} 1393 1394// Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup 1395// instruction and checking the alignment value. 1396def AddrMode6dupAlign16AsmOperand : AsmOperandClass { 1397 let Name = "DupAlignedMemory16"; 1398 let DiagnosticString = "alignment must be 16 or omitted"; 1399} 1400def addrmode6dupalign16 : AddrMode6DupAlign { 1401 // The alignment specifier can only be 16 or omitted. 1402 let ParserMatchClass = AddrMode6dupAlign16AsmOperand; 1403} 1404 1405// Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup 1406// instruction and checking the alignment value. 1407def AddrMode6dupAlign32AsmOperand : AsmOperandClass { 1408 let Name = "DupAlignedMemory32"; 1409 let DiagnosticString = "alignment must be 32 or omitted"; 1410} 1411def addrmode6dupalign32 : AddrMode6DupAlign { 1412 // The alignment specifier can only be 32 or omitted. 1413 let ParserMatchClass = AddrMode6dupAlign32AsmOperand; 1414} 1415 1416// Special version of addrmode6 to handle 64-bit alignment encoding for VLD 1417// instructions and checking the alignment value. 1418def AddrMode6dupAlign64AsmOperand : AsmOperandClass { 1419 let Name = "DupAlignedMemory64"; 1420 let DiagnosticString = "alignment must be 64 or omitted"; 1421} 1422def addrmode6dupalign64 : AddrMode6DupAlign { 1423 // The alignment specifier can only be 64 or omitted. 1424 let ParserMatchClass = AddrMode6dupAlign64AsmOperand; 1425} 1426 1427// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1428// for VLD instructions and checking the alignment value. 1429def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass { 1430 let Name = "DupAlignedMemory64or128"; 1431 let DiagnosticString = "alignment must be 64, 128 or omitted"; 1432} 1433def addrmode6dupalign64or128 : AddrMode6DupAlign { 1434 // The alignment specifier can only be 64, 128 or omitted. 1435 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand; 1436} 1437 1438// addrmodepc := pc + reg 1439// 1440def addrmodepc : MemOperand, 1441 ComplexPattern<i32, 2, "SelectAddrModePC", []> { 1442 let PrintMethod = "printAddrModePCOperand"; 1443 let MIOperandInfo = (ops GPR, i32imm); 1444} 1445 1446// addr_offset_none := reg 1447// 1448def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; } 1449def addr_offset_none : MemOperand, 1450 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> { 1451 let PrintMethod = "printAddrMode7Operand"; 1452 let DecoderMethod = "DecodeAddrMode7Operand"; 1453 let ParserMatchClass = MemNoOffsetAsmOperand; 1454 let MIOperandInfo = (ops GPR:$base); 1455} 1456 1457// t_addr_offset_none := reg [r0-r7] 1458def MemNoOffsetTAsmOperand : AsmOperandClass { let Name = "MemNoOffsetT"; } 1459def t_addr_offset_none : MemOperand { 1460 let PrintMethod = "printAddrMode7Operand"; 1461 let DecoderMethod = "DecodetGPRRegisterClass"; 1462 let ParserMatchClass = MemNoOffsetTAsmOperand; 1463 let MIOperandInfo = (ops tGPR:$base); 1464} 1465 1466def nohash_imm : Operand<i32> { 1467 let PrintMethod = "printNoHashImmediate"; 1468} 1469 1470def CoprocNumAsmOperand : AsmOperandClass { 1471 let Name = "CoprocNum"; 1472 let ParserMethod = "parseCoprocNumOperand"; 1473} 1474def p_imm : Operand<i32> { 1475 let PrintMethod = "printPImmediate"; 1476 let ParserMatchClass = CoprocNumAsmOperand; 1477 let DecoderMethod = "DecodeCoprocessor"; 1478} 1479 1480def CoprocRegAsmOperand : AsmOperandClass { 1481 let Name = "CoprocReg"; 1482 let ParserMethod = "parseCoprocRegOperand"; 1483} 1484def c_imm : Operand<i32> { 1485 let PrintMethod = "printCImmediate"; 1486 let ParserMatchClass = CoprocRegAsmOperand; 1487} 1488def CoprocOptionAsmOperand : AsmOperandClass { 1489 let Name = "CoprocOption"; 1490 let ParserMethod = "parseCoprocOptionOperand"; 1491} 1492def coproc_option_imm : Operand<i32> { 1493 let PrintMethod = "printCoprocOptionImm"; 1494 let ParserMatchClass = CoprocOptionAsmOperand; 1495} 1496 1497//===----------------------------------------------------------------------===// 1498 1499include "ARMInstrFormats.td" 1500 1501//===----------------------------------------------------------------------===// 1502// Multiclass helpers... 1503// 1504 1505/// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a 1506/// binop that produces a value. 1507let TwoOperandAliasConstraint = "$Rn = $Rd" in 1508multiclass AsI1_bin_irs<bits<4> opcod, string opc, 1509 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1510 SDPatternOperator opnode, bit Commutable = 0> { 1511 // The register-immediate version is re-materializable. This is useful 1512 // in particular for taking the address of a local. 1513 let isReMaterializable = 1 in { 1514 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm, 1515 iii, opc, "\t$Rd, $Rn, $imm", 1516 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>, 1517 Sched<[WriteALU, ReadALU]> { 1518 bits<4> Rd; 1519 bits<4> Rn; 1520 bits<12> imm; 1521 let Inst{25} = 1; 1522 let Inst{19-16} = Rn; 1523 let Inst{15-12} = Rd; 1524 let Inst{11-0} = imm; 1525 } 1526 } 1527 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1528 iir, opc, "\t$Rd, $Rn, $Rm", 1529 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, 1530 Sched<[WriteALU, ReadALU, ReadALU]> { 1531 bits<4> Rd; 1532 bits<4> Rn; 1533 bits<4> Rm; 1534 let Inst{25} = 0; 1535 let isCommutable = Commutable; 1536 let Inst{19-16} = Rn; 1537 let Inst{15-12} = Rd; 1538 let Inst{11-4} = 0b00000000; 1539 let Inst{3-0} = Rm; 1540 } 1541 1542 def rsi : AsI1<opcod, (outs GPR:$Rd), 1543 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1544 iis, opc, "\t$Rd, $Rn, $shift", 1545 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>, 1546 Sched<[WriteALUsi, ReadALU]> { 1547 bits<4> Rd; 1548 bits<4> Rn; 1549 bits<12> shift; 1550 let Inst{25} = 0; 1551 let Inst{19-16} = Rn; 1552 let Inst{15-12} = Rd; 1553 let Inst{11-5} = shift{11-5}; 1554 let Inst{4} = 0; 1555 let Inst{3-0} = shift{3-0}; 1556 } 1557 1558 def rsr : AsI1<opcod, (outs GPR:$Rd), 1559 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1560 iis, opc, "\t$Rd, $Rn, $shift", 1561 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>, 1562 Sched<[WriteALUsr, ReadALUsr]> { 1563 bits<4> Rd; 1564 bits<4> Rn; 1565 bits<12> shift; 1566 let Inst{25} = 0; 1567 let Inst{19-16} = Rn; 1568 let Inst{15-12} = Rd; 1569 let Inst{11-8} = shift{11-8}; 1570 let Inst{7} = 0; 1571 let Inst{6-5} = shift{6-5}; 1572 let Inst{4} = 1; 1573 let Inst{3-0} = shift{3-0}; 1574 } 1575} 1576 1577/// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are 1578/// reversed. The 'rr' form is only defined for the disassembler; for codegen 1579/// it is equivalent to the AsI1_bin_irs counterpart. 1580let TwoOperandAliasConstraint = "$Rn = $Rd" in 1581multiclass AsI1_rbin_irs<bits<4> opcod, string opc, 1582 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1583 SDNode opnode, bit Commutable = 0> { 1584 // The register-immediate version is re-materializable. This is useful 1585 // in particular for taking the address of a local. 1586 let isReMaterializable = 1 in { 1587 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm, 1588 iii, opc, "\t$Rd, $Rn, $imm", 1589 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>, 1590 Sched<[WriteALU, ReadALU]> { 1591 bits<4> Rd; 1592 bits<4> Rn; 1593 bits<12> imm; 1594 let Inst{25} = 1; 1595 let Inst{19-16} = Rn; 1596 let Inst{15-12} = Rd; 1597 let Inst{11-0} = imm; 1598 } 1599 } 1600 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1601 iir, opc, "\t$Rd, $Rn, $Rm", 1602 [/* pattern left blank */]>, 1603 Sched<[WriteALU, ReadALU, ReadALU]> { 1604 bits<4> Rd; 1605 bits<4> Rn; 1606 bits<4> Rm; 1607 let Inst{11-4} = 0b00000000; 1608 let Inst{25} = 0; 1609 let Inst{3-0} = Rm; 1610 let Inst{15-12} = Rd; 1611 let Inst{19-16} = Rn; 1612 } 1613 1614 def rsi : AsI1<opcod, (outs GPR:$Rd), 1615 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1616 iis, opc, "\t$Rd, $Rn, $shift", 1617 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>, 1618 Sched<[WriteALUsi, ReadALU]> { 1619 bits<4> Rd; 1620 bits<4> Rn; 1621 bits<12> shift; 1622 let Inst{25} = 0; 1623 let Inst{19-16} = Rn; 1624 let Inst{15-12} = Rd; 1625 let Inst{11-5} = shift{11-5}; 1626 let Inst{4} = 0; 1627 let Inst{3-0} = shift{3-0}; 1628 } 1629 1630 def rsr : AsI1<opcod, (outs GPR:$Rd), 1631 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1632 iis, opc, "\t$Rd, $Rn, $shift", 1633 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>, 1634 Sched<[WriteALUsr, ReadALUsr]> { 1635 bits<4> Rd; 1636 bits<4> Rn; 1637 bits<12> shift; 1638 let Inst{25} = 0; 1639 let Inst{19-16} = Rn; 1640 let Inst{15-12} = Rd; 1641 let Inst{11-8} = shift{11-8}; 1642 let Inst{7} = 0; 1643 let Inst{6-5} = shift{6-5}; 1644 let Inst{4} = 1; 1645 let Inst{3-0} = shift{3-0}; 1646 } 1647} 1648 1649/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default. 1650/// 1651/// These opcodes will be converted to the real non-S opcodes by 1652/// AdjustInstrPostInstrSelection after giving them an optional CPSR operand. 1653let hasPostISelHook = 1, Defs = [CPSR] in { 1654multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir, 1655 InstrItinClass iis, SDNode opnode, 1656 bit Commutable = 0> { 1657 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 1658 4, iii, 1659 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>, 1660 Sched<[WriteALU, ReadALU]>; 1661 1662 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p), 1663 4, iir, 1664 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>, 1665 Sched<[WriteALU, ReadALU, ReadALU]> { 1666 let isCommutable = Commutable; 1667 } 1668 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1669 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1670 4, iis, 1671 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1672 so_reg_imm:$shift))]>, 1673 Sched<[WriteALUsi, ReadALU]>; 1674 1675 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1676 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1677 4, iis, 1678 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1679 so_reg_reg:$shift))]>, 1680 Sched<[WriteALUSsr, ReadALUsr]>; 1681} 1682} 1683 1684/// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG 1685/// operands are reversed. 1686let hasPostISelHook = 1, Defs = [CPSR] in { 1687multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir, 1688 InstrItinClass iis, SDNode opnode, 1689 bit Commutable = 0> { 1690 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 1691 4, iii, 1692 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>, 1693 Sched<[WriteALU, ReadALU]>; 1694 1695 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1696 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1697 4, iis, 1698 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, 1699 GPR:$Rn))]>, 1700 Sched<[WriteALUsi, ReadALU]>; 1701 1702 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1703 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1704 4, iis, 1705 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, 1706 GPR:$Rn))]>, 1707 Sched<[WriteALUSsr, ReadALUsr]>; 1708} 1709} 1710 1711/// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test 1712/// patterns. Similar to AsI1_bin_irs except the instruction does not produce 1713/// a explicit result, only implicitly set CPSR. 1714let isCompare = 1, Defs = [CPSR] in { 1715multiclass AI1_cmp_irs<bits<4> opcod, string opc, 1716 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1717 SDPatternOperator opnode, bit Commutable = 0, 1718 string rrDecoderMethod = ""> { 1719 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii, 1720 opc, "\t$Rn, $imm", 1721 [(opnode GPR:$Rn, mod_imm:$imm)]>, 1722 Sched<[WriteCMP, ReadALU]> { 1723 bits<4> Rn; 1724 bits<12> imm; 1725 let Inst{25} = 1; 1726 let Inst{20} = 1; 1727 let Inst{19-16} = Rn; 1728 let Inst{15-12} = 0b0000; 1729 let Inst{11-0} = imm; 1730 1731 let Unpredictable{15-12} = 0b1111; 1732 } 1733 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir, 1734 opc, "\t$Rn, $Rm", 1735 [(opnode GPR:$Rn, GPR:$Rm)]>, 1736 Sched<[WriteCMP, ReadALU, ReadALU]> { 1737 bits<4> Rn; 1738 bits<4> Rm; 1739 let isCommutable = Commutable; 1740 let Inst{25} = 0; 1741 let Inst{20} = 1; 1742 let Inst{19-16} = Rn; 1743 let Inst{15-12} = 0b0000; 1744 let Inst{11-4} = 0b00000000; 1745 let Inst{3-0} = Rm; 1746 let DecoderMethod = rrDecoderMethod; 1747 1748 let Unpredictable{15-12} = 0b1111; 1749 } 1750 def rsi : AI1<opcod, (outs), 1751 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis, 1752 opc, "\t$Rn, $shift", 1753 [(opnode GPR:$Rn, so_reg_imm:$shift)]>, 1754 Sched<[WriteCMPsi, ReadALU]> { 1755 bits<4> Rn; 1756 bits<12> shift; 1757 let Inst{25} = 0; 1758 let Inst{20} = 1; 1759 let Inst{19-16} = Rn; 1760 let Inst{15-12} = 0b0000; 1761 let Inst{11-5} = shift{11-5}; 1762 let Inst{4} = 0; 1763 let Inst{3-0} = shift{3-0}; 1764 1765 let Unpredictable{15-12} = 0b1111; 1766 } 1767 def rsr : AI1<opcod, (outs), 1768 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis, 1769 opc, "\t$Rn, $shift", 1770 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>, 1771 Sched<[WriteCMPsr, ReadALU]> { 1772 bits<4> Rn; 1773 bits<12> shift; 1774 let Inst{25} = 0; 1775 let Inst{20} = 1; 1776 let Inst{19-16} = Rn; 1777 let Inst{15-12} = 0b0000; 1778 let Inst{11-8} = shift{11-8}; 1779 let Inst{7} = 0; 1780 let Inst{6-5} = shift{6-5}; 1781 let Inst{4} = 1; 1782 let Inst{3-0} = shift{3-0}; 1783 1784 let Unpredictable{15-12} = 0b1111; 1785 } 1786 1787} 1788} 1789 1790/// AI_ext_rrot - A unary operation with two forms: one whose operand is a 1791/// register and one whose operand is a register rotated by 8/16/24. 1792/// FIXME: Remove the 'r' variant. Its rot_imm is zero. 1793class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> 1794 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1795 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", 1796 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1797 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1798 bits<4> Rd; 1799 bits<4> Rm; 1800 bits<2> rot; 1801 let Inst{19-16} = 0b1111; 1802 let Inst{15-12} = Rd; 1803 let Inst{11-10} = rot; 1804 let Inst{3-0} = Rm; 1805} 1806 1807class AI_ext_rrot_np<bits<8> opcod, string opc> 1808 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1809 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>, 1810 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1811 bits<2> rot; 1812 let Inst{19-16} = 0b1111; 1813 let Inst{11-10} = rot; 1814 } 1815 1816/// AI_exta_rrot - A binary operation with two forms: one whose operand is a 1817/// register and one whose operand is a register rotated by 8/16/24. 1818class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> 1819 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1820 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", 1821 [(set GPRnopc:$Rd, (opnode GPR:$Rn, 1822 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1823 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1824 bits<4> Rd; 1825 bits<4> Rm; 1826 bits<4> Rn; 1827 bits<2> rot; 1828 let Inst{19-16} = Rn; 1829 let Inst{15-12} = Rd; 1830 let Inst{11-10} = rot; 1831 let Inst{9-4} = 0b000111; 1832 let Inst{3-0} = Rm; 1833} 1834 1835class AI_exta_rrot_np<bits<8> opcod, string opc> 1836 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1837 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>, 1838 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1839 bits<4> Rn; 1840 bits<2> rot; 1841 let Inst{19-16} = Rn; 1842 let Inst{11-10} = rot; 1843} 1844 1845/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. 1846let TwoOperandAliasConstraint = "$Rn = $Rd" in 1847multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, SDNode opnode, 1848 bit Commutable = 0> { 1849 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1850 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), 1851 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1852 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>, 1853 Requires<[IsARM]>, 1854 Sched<[WriteALU, ReadALU]> { 1855 bits<4> Rd; 1856 bits<4> Rn; 1857 bits<12> imm; 1858 let Inst{25} = 1; 1859 let Inst{15-12} = Rd; 1860 let Inst{19-16} = Rn; 1861 let Inst{11-0} = imm; 1862 } 1863 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1864 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1865 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>, 1866 Requires<[IsARM]>, 1867 Sched<[WriteALU, ReadALU, ReadALU]> { 1868 bits<4> Rd; 1869 bits<4> Rn; 1870 bits<4> Rm; 1871 let Inst{11-4} = 0b00000000; 1872 let Inst{25} = 0; 1873 let isCommutable = Commutable; 1874 let Inst{3-0} = Rm; 1875 let Inst{15-12} = Rd; 1876 let Inst{19-16} = Rn; 1877 } 1878 def rsi : AsI1<opcod, (outs GPR:$Rd), 1879 (ins GPR:$Rn, so_reg_imm:$shift), 1880 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1881 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>, 1882 Requires<[IsARM]>, 1883 Sched<[WriteALUsi, ReadALU]> { 1884 bits<4> Rd; 1885 bits<4> Rn; 1886 bits<12> shift; 1887 let Inst{25} = 0; 1888 let Inst{19-16} = Rn; 1889 let Inst{15-12} = Rd; 1890 let Inst{11-5} = shift{11-5}; 1891 let Inst{4} = 0; 1892 let Inst{3-0} = shift{3-0}; 1893 } 1894 def rsr : AsI1<opcod, (outs GPRnopc:$Rd), 1895 (ins GPRnopc:$Rn, so_reg_reg:$shift), 1896 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1897 [(set GPRnopc:$Rd, CPSR, 1898 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>, 1899 Requires<[IsARM]>, 1900 Sched<[WriteALUsr, ReadALUsr]> { 1901 bits<4> Rd; 1902 bits<4> Rn; 1903 bits<12> shift; 1904 let Inst{25} = 0; 1905 let Inst{19-16} = Rn; 1906 let Inst{15-12} = Rd; 1907 let Inst{11-8} = shift{11-8}; 1908 let Inst{7} = 0; 1909 let Inst{6-5} = shift{6-5}; 1910 let Inst{4} = 1; 1911 let Inst{3-0} = shift{3-0}; 1912 } 1913 } 1914} 1915 1916/// AI1_rsc_irs - Define instructions and patterns for rsc 1917let TwoOperandAliasConstraint = "$Rn = $Rd" in 1918multiclass AI1_rsc_irs<bits<4> opcod, string opc, SDNode opnode> { 1919 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1920 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), 1921 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1922 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>, 1923 Requires<[IsARM]>, 1924 Sched<[WriteALU, ReadALU]> { 1925 bits<4> Rd; 1926 bits<4> Rn; 1927 bits<12> imm; 1928 let Inst{25} = 1; 1929 let Inst{15-12} = Rd; 1930 let Inst{19-16} = Rn; 1931 let Inst{11-0} = imm; 1932 } 1933 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1934 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1935 [/* pattern left blank */]>, 1936 Sched<[WriteALU, ReadALU, ReadALU]> { 1937 bits<4> Rd; 1938 bits<4> Rn; 1939 bits<4> Rm; 1940 let Inst{11-4} = 0b00000000; 1941 let Inst{25} = 0; 1942 let Inst{3-0} = Rm; 1943 let Inst{15-12} = Rd; 1944 let Inst{19-16} = Rn; 1945 } 1946 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), 1947 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1948 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>, 1949 Requires<[IsARM]>, 1950 Sched<[WriteALUsi, ReadALU]> { 1951 bits<4> Rd; 1952 bits<4> Rn; 1953 bits<12> shift; 1954 let Inst{25} = 0; 1955 let Inst{19-16} = Rn; 1956 let Inst{15-12} = Rd; 1957 let Inst{11-5} = shift{11-5}; 1958 let Inst{4} = 0; 1959 let Inst{3-0} = shift{3-0}; 1960 } 1961 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), 1962 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1963 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>, 1964 Requires<[IsARM]>, 1965 Sched<[WriteALUsr, ReadALUsr]> { 1966 bits<4> Rd; 1967 bits<4> Rn; 1968 bits<12> shift; 1969 let Inst{25} = 0; 1970 let Inst{19-16} = Rn; 1971 let Inst{15-12} = Rd; 1972 let Inst{11-8} = shift{11-8}; 1973 let Inst{7} = 0; 1974 let Inst{6-5} = shift{6-5}; 1975 let Inst{4} = 1; 1976 let Inst{3-0} = shift{3-0}; 1977 } 1978 } 1979} 1980 1981let canFoldAsLoad = 1, isReMaterializable = 1 in { 1982multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii, 1983 InstrItinClass iir, PatFrag opnode> { 1984 // Note: We use the complex addrmode_imm12 rather than just an input 1985 // GPR and a constrained immediate so that we can use this to match 1986 // frame index references and avoid matching constant pool references. 1987 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 1988 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1989 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { 1990 bits<4> Rt; 1991 bits<17> addr; 1992 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1993 let Inst{19-16} = addr{16-13}; // Rn 1994 let Inst{15-12} = Rt; 1995 let Inst{11-0} = addr{11-0}; // imm12 1996 } 1997 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift), 1998 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1999 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { 2000 bits<4> Rt; 2001 bits<17> shift; 2002 let shift{4} = 0; // Inst{4} = 0 2003 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 2004 let Inst{19-16} = shift{16-13}; // Rn 2005 let Inst{15-12} = Rt; 2006 let Inst{11-0} = shift{11-0}; 2007 } 2008} 2009} 2010 2011let canFoldAsLoad = 1, isReMaterializable = 1 in { 2012multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii, 2013 InstrItinClass iir, PatFrag opnode> { 2014 // Note: We use the complex addrmode_imm12 rather than just an input 2015 // GPR and a constrained immediate so that we can use this to match 2016 // frame index references and avoid matching constant pool references. 2017 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), 2018 (ins addrmode_imm12:$addr), 2019 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 2020 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> { 2021 bits<4> Rt; 2022 bits<17> addr; 2023 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2024 let Inst{19-16} = addr{16-13}; // Rn 2025 let Inst{15-12} = Rt; 2026 let Inst{11-0} = addr{11-0}; // imm12 2027 } 2028 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), 2029 (ins ldst_so_reg:$shift), 2030 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 2031 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> { 2032 bits<4> Rt; 2033 bits<17> shift; 2034 let shift{4} = 0; // Inst{4} = 0 2035 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 2036 let Inst{19-16} = shift{16-13}; // Rn 2037 let Inst{15-12} = Rt; 2038 let Inst{11-0} = shift{11-0}; 2039 } 2040} 2041} 2042 2043 2044multiclass AI_str1<bit isByte, string opc, InstrItinClass iii, 2045 InstrItinClass iir, PatFrag opnode> { 2046 // Note: We use the complex addrmode_imm12 rather than just an input 2047 // GPR and a constrained immediate so that we can use this to match 2048 // frame index references and avoid matching constant pool references. 2049 def i12 : AI2ldst<0b010, 0, isByte, (outs), 2050 (ins GPR:$Rt, addrmode_imm12:$addr), 2051 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 2052 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> { 2053 bits<4> Rt; 2054 bits<17> addr; 2055 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2056 let Inst{19-16} = addr{16-13}; // Rn 2057 let Inst{15-12} = Rt; 2058 let Inst{11-0} = addr{11-0}; // imm12 2059 } 2060 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift), 2061 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 2062 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> { 2063 bits<4> Rt; 2064 bits<17> shift; 2065 let shift{4} = 0; // Inst{4} = 0 2066 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 2067 let Inst{19-16} = shift{16-13}; // Rn 2068 let Inst{15-12} = Rt; 2069 let Inst{11-0} = shift{11-0}; 2070 } 2071} 2072 2073multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii, 2074 InstrItinClass iir, PatFrag opnode> { 2075 // Note: We use the complex addrmode_imm12 rather than just an input 2076 // GPR and a constrained immediate so that we can use this to match 2077 // frame index references and avoid matching constant pool references. 2078 def i12 : AI2ldst<0b010, 0, isByte, (outs), 2079 (ins GPRnopc:$Rt, addrmode_imm12:$addr), 2080 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 2081 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> { 2082 bits<4> Rt; 2083 bits<17> addr; 2084 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2085 let Inst{19-16} = addr{16-13}; // Rn 2086 let Inst{15-12} = Rt; 2087 let Inst{11-0} = addr{11-0}; // imm12 2088 } 2089 def rs : AI2ldst<0b011, 0, isByte, (outs), 2090 (ins GPRnopc:$Rt, ldst_so_reg:$shift), 2091 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 2092 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> { 2093 bits<4> Rt; 2094 bits<17> shift; 2095 let shift{4} = 0; // Inst{4} = 0 2096 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 2097 let Inst{19-16} = shift{16-13}; // Rn 2098 let Inst{15-12} = Rt; 2099 let Inst{11-0} = shift{11-0}; 2100 } 2101} 2102 2103 2104//===----------------------------------------------------------------------===// 2105// Instructions 2106//===----------------------------------------------------------------------===// 2107 2108//===----------------------------------------------------------------------===// 2109// Miscellaneous Instructions. 2110// 2111 2112/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in 2113/// the function. The first operand is the ID# for this instruction, the second 2114/// is the index into the MachineConstantPool that this is, the third is the 2115/// size in bytes of this constant pool entry. 2116let hasSideEffects = 0, isNotDuplicable = 1, hasNoSchedulingInfo = 1 in 2117def CONSTPOOL_ENTRY : 2118PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 2119 i32imm:$size), NoItinerary, []>; 2120 2121/// A jumptable consisting of direct 32-bit addresses of the destination basic 2122/// blocks (either absolute, or relative to the start of the jump-table in PIC 2123/// mode). Used mostly in ARM and Thumb-1 modes. 2124def JUMPTABLE_ADDRS : 2125PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 2126 i32imm:$size), NoItinerary, []>; 2127 2128/// A jumptable consisting of 32-bit jump instructions. Used for Thumb-2 tables 2129/// that cannot be optimised to use TBB or TBH. 2130def JUMPTABLE_INSTS : 2131PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 2132 i32imm:$size), NoItinerary, []>; 2133 2134/// A jumptable consisting of 8-bit unsigned integers representing offsets from 2135/// a TBB instruction. 2136def JUMPTABLE_TBB : 2137PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 2138 i32imm:$size), NoItinerary, []>; 2139 2140/// A jumptable consisting of 16-bit unsigned integers representing offsets from 2141/// a TBH instruction. 2142def JUMPTABLE_TBH : 2143PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 2144 i32imm:$size), NoItinerary, []>; 2145 2146 2147// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 2148// from removing one half of the matched pairs. That breaks PEI, which assumes 2149// these will always be in pairs, and asserts if it finds otherwise. Better way? 2150let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 2151def ADJCALLSTACKUP : 2152PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, 2153 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>; 2154 2155def ADJCALLSTACKDOWN : 2156PseudoInst<(outs), (ins i32imm:$amt, i32imm:$amt2, pred:$p), NoItinerary, 2157 [(ARMcallseq_start timm:$amt, timm:$amt2)]>; 2158} 2159 2160def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary, 2161 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>, 2162 Requires<[IsARM, HasV6]> { 2163 bits<8> imm; 2164 let Inst{27-8} = 0b00110010000011110000; 2165 let Inst{7-0} = imm; 2166 let DecoderMethod = "DecodeHINTInstruction"; 2167} 2168 2169def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>; 2170def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>; 2171def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>; 2172def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>; 2173def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>; 2174def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>; 2175def : InstAlias<"esb$p", (HINT 16, pred:$p)>, Requires<[IsARM, HasRAS]>; 2176def : InstAlias<"csdb$p", (HINT 20, pred:$p)>, Requires<[IsARM, HasV6K]>; 2177 2178def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel", 2179 "\t$Rd, $Rn, $Rm", 2180 [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>, 2181 Requires<[IsARM, HasV6]> { 2182 bits<4> Rd; 2183 bits<4> Rn; 2184 bits<4> Rm; 2185 let Inst{3-0} = Rm; 2186 let Inst{15-12} = Rd; 2187 let Inst{19-16} = Rn; 2188 let Inst{27-20} = 0b01101000; 2189 let Inst{7-4} = 0b1011; 2190 let Inst{11-8} = 0b1111; 2191 let Unpredictable{11-8} = 0b1111; 2192} 2193 2194// The 16-bit operand $val can be used by a debugger to store more information 2195// about the breakpoint. 2196def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 2197 "bkpt", "\t$val", []>, Requires<[IsARM]> { 2198 bits<16> val; 2199 let Inst{3-0} = val{3-0}; 2200 let Inst{19-8} = val{15-4}; 2201 let Inst{27-20} = 0b00010010; 2202 let Inst{31-28} = 0xe; // AL 2203 let Inst{7-4} = 0b0111; 2204} 2205// default immediate for breakpoint mnemonic 2206def : InstAlias<"bkpt", (BKPT 0), 0>, Requires<[IsARM]>; 2207 2208def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 2209 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> { 2210 bits<16> val; 2211 let Inst{3-0} = val{3-0}; 2212 let Inst{19-8} = val{15-4}; 2213 let Inst{27-20} = 0b00010000; 2214 let Inst{31-28} = 0xe; // AL 2215 let Inst{7-4} = 0b0111; 2216} 2217 2218// Change Processor State 2219// FIXME: We should use InstAlias to handle the optional operands. 2220class CPS<dag iops, string asm_ops> 2221 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops), 2222 []>, Requires<[IsARM]> { 2223 bits<2> imod; 2224 bits<3> iflags; 2225 bits<5> mode; 2226 bit M; 2227 2228 let Inst{31-28} = 0b1111; 2229 let Inst{27-20} = 0b00010000; 2230 let Inst{19-18} = imod; 2231 let Inst{17} = M; // Enabled if mode is set; 2232 let Inst{16-9} = 0b00000000; 2233 let Inst{8-6} = iflags; 2234 let Inst{5} = 0; 2235 let Inst{4-0} = mode; 2236} 2237 2238let DecoderMethod = "DecodeCPSInstruction" in { 2239let M = 1 in 2240 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode), 2241 "$imod\t$iflags, $mode">; 2242let mode = 0, M = 0 in 2243 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">; 2244 2245let imod = 0, iflags = 0, M = 1 in 2246 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">; 2247} 2248 2249// Preload signals the memory system of possible future data/instruction access. 2250multiclass APreLoad<bits<1> read, bits<1> data, string opc> { 2251 2252 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm, 2253 IIC_Preload, !strconcat(opc, "\t$addr"), 2254 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>, 2255 Sched<[WritePreLd]> { 2256 bits<4> Rt; 2257 bits<17> addr; 2258 let Inst{31-26} = 0b111101; 2259 let Inst{25} = 0; // 0 for immediate form 2260 let Inst{24} = data; 2261 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2262 let Inst{22} = read; 2263 let Inst{21-20} = 0b01; 2264 let Inst{19-16} = addr{16-13}; // Rn 2265 let Inst{15-12} = 0b1111; 2266 let Inst{11-0} = addr{11-0}; // imm12 2267 } 2268 2269 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload, 2270 !strconcat(opc, "\t$shift"), 2271 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>, 2272 Sched<[WritePreLd]> { 2273 bits<17> shift; 2274 let Inst{31-26} = 0b111101; 2275 let Inst{25} = 1; // 1 for register form 2276 let Inst{24} = data; 2277 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 2278 let Inst{22} = read; 2279 let Inst{21-20} = 0b01; 2280 let Inst{19-16} = shift{16-13}; // Rn 2281 let Inst{15-12} = 0b1111; 2282 let Inst{11-0} = shift{11-0}; 2283 let Inst{4} = 0; 2284 } 2285} 2286 2287defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>; 2288defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>; 2289defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>; 2290 2291def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary, 2292 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> { 2293 bits<1> end; 2294 let Inst{31-10} = 0b1111000100000001000000; 2295 let Inst{9} = end; 2296 let Inst{8-0} = 0; 2297} 2298 2299def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", 2300 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> { 2301 bits<4> opt; 2302 let Inst{27-4} = 0b001100100000111100001111; 2303 let Inst{3-0} = opt; 2304} 2305 2306// A8.8.247 UDF - Undefined (Encoding A1) 2307def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary, 2308 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> { 2309 bits<16> imm16; 2310 let Inst{31-28} = 0b1110; // AL 2311 let Inst{27-25} = 0b011; 2312 let Inst{24-20} = 0b11111; 2313 let Inst{19-8} = imm16{15-4}; 2314 let Inst{7-4} = 0b1111; 2315 let Inst{3-0} = imm16{3-0}; 2316} 2317 2318/* 2319 * A5.4 Permanently UNDEFINED instructions. 2320 * 2321 * For most targets use UDF #65006, for which the OS will generate SIGTRAP. 2322 * Other UDF encodings generate SIGILL. 2323 * 2324 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb. 2325 * Encoding A1: 2326 * 1110 0111 1111 iiii iiii iiii 1111 iiii 2327 * Encoding T1: 2328 * 1101 1110 iiii iiii 2329 * It uses the following encoding: 2330 * 1110 0111 1111 1110 1101 1110 1111 0000 2331 * - In ARM: UDF #60896; 2332 * - In Thumb: UDF #254 followed by a branch-to-self. 2333 */ 2334let isBarrier = 1, isTerminator = 1 in 2335def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary, 2336 "trap", [(trap)]>, 2337 Requires<[IsARM,UseNaClTrap]> { 2338 let Inst = 0xe7fedef0; 2339} 2340let isBarrier = 1, isTerminator = 1 in 2341def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary, 2342 "trap", [(trap)]>, 2343 Requires<[IsARM,DontUseNaClTrap]> { 2344 let Inst = 0xe7ffdefe; 2345} 2346 2347def : Pat<(debugtrap), (BKPT 0)>, Requires<[IsARM, HasV5T]>; 2348def : Pat<(debugtrap), (UDF 254)>, Requires<[IsARM, NoV5T]>; 2349 2350// Address computation and loads and stores in PIC mode. 2351let isNotDuplicable = 1 in { 2352def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), 2353 4, IIC_iALUr, 2354 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>, 2355 Sched<[WriteALU, ReadALU]>; 2356 2357let AddedComplexity = 10 in { 2358def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 2359 4, IIC_iLoad_r, 2360 [(set GPR:$dst, (load addrmodepc:$addr))]>; 2361 2362def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2363 4, IIC_iLoad_bh_r, 2364 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>; 2365 2366def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2367 4, IIC_iLoad_bh_r, 2368 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>; 2369 2370def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2371 4, IIC_iLoad_bh_r, 2372 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>; 2373 2374def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2375 4, IIC_iLoad_bh_r, 2376 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>; 2377} 2378let AddedComplexity = 10 in { 2379def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2380 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>; 2381 2382def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2383 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, 2384 addrmodepc:$addr)]>; 2385 2386def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2387 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; 2388} 2389} // isNotDuplicable = 1 2390 2391 2392// LEApcrel - Load a pc-relative address into a register without offending the 2393// assembler. 2394let hasSideEffects = 0, isReMaterializable = 1 in 2395// The 'adr' mnemonic encodes differently if the label is before or after 2396// the instruction. The {24-21} opcode bits are set by the fixup, as we don't 2397// know until then which form of the instruction will be used. 2398def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label), 2399 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>, 2400 Sched<[WriteALU, ReadALU]> { 2401 bits<4> Rd; 2402 bits<14> label; 2403 let Inst{27-25} = 0b001; 2404 let Inst{24} = 0; 2405 let Inst{23-22} = label{13-12}; 2406 let Inst{21} = 0; 2407 let Inst{20} = 0; 2408 let Inst{19-16} = 0b1111; 2409 let Inst{15-12} = Rd; 2410 let Inst{11-0} = label{11-0}; 2411} 2412 2413let hasSideEffects = 1 in { 2414def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p), 2415 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2416 2417def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd), 2418 (ins i32imm:$label, pred:$p), 2419 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2420} 2421 2422//===----------------------------------------------------------------------===// 2423// Control Flow Instructions. 2424// 2425 2426let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 2427 // ARMV4T and above 2428 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2429 "bx", "\tlr", [(ARMretflag)]>, 2430 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2431 let Inst{27-0} = 0b0001001011111111111100011110; 2432 } 2433 2434 // ARMV4 only 2435 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2436 "mov", "\tpc, lr", [(ARMretflag)]>, 2437 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> { 2438 let Inst{27-0} = 0b0001101000001111000000001110; 2439 } 2440 2441 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets 2442 // the user-space one). 2443 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p), 2444 4, IIC_Br, 2445 [(ARMintretflag imm:$offset)]>; 2446} 2447 2448// Indirect branches 2449let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 2450 // ARMV4T and above 2451 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst", 2452 [(brind GPR:$dst)]>, 2453 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2454 bits<4> dst; 2455 let Inst{31-4} = 0b1110000100101111111111110001; 2456 let Inst{3-0} = dst; 2457 } 2458 2459 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, 2460 "bx", "\t$dst", [/* pattern left blank */]>, 2461 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2462 bits<4> dst; 2463 let Inst{27-4} = 0b000100101111111111110001; 2464 let Inst{3-0} = dst; 2465 } 2466} 2467 2468// SP is marked as a use to prevent stack-pointer assignments that appear 2469// immediately before calls from potentially appearing dead. 2470let isCall = 1, 2471 // FIXME: Do we really need a non-predicated version? If so, it should 2472 // at least be a pseudo instruction expanding to the predicated version 2473 // at MC lowering time. 2474 Defs = [LR], Uses = [SP] in { 2475 def BL : ABXI<0b1011, (outs), (ins arm_bl_target:$func), 2476 IIC_Br, "bl\t$func", 2477 [(ARMcall tglobaladdr:$func)]>, 2478 Requires<[IsARM]>, Sched<[WriteBrL]> { 2479 let Inst{31-28} = 0b1110; 2480 bits<24> func; 2481 let Inst{23-0} = func; 2482 let DecoderMethod = "DecodeBranchImmInstruction"; 2483 } 2484 2485 def BL_pred : ABI<0b1011, (outs), (ins arm_bl_target:$func), 2486 IIC_Br, "bl", "\t$func", 2487 [(ARMcall_pred tglobaladdr:$func)]>, 2488 Requires<[IsARM]>, Sched<[WriteBrL]> { 2489 bits<24> func; 2490 let Inst{23-0} = func; 2491 let DecoderMethod = "DecodeBranchImmInstruction"; 2492 } 2493 2494 // ARMv5T and above 2495 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm, 2496 IIC_Br, "blx\t$func", 2497 [(ARMcall GPR:$func)]>, 2498 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2499 bits<4> func; 2500 let Inst{31-4} = 0b1110000100101111111111110011; 2501 let Inst{3-0} = func; 2502 } 2503 2504 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm, 2505 IIC_Br, "blx", "\t$func", 2506 [(ARMcall_pred GPR:$func)]>, 2507 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2508 bits<4> func; 2509 let Inst{27-4} = 0b000100101111111111110011; 2510 let Inst{3-0} = func; 2511 } 2512 2513 // ARMv4T 2514 // Note: Restrict $func to the tGPR regclass to prevent it being in LR. 2515 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2516 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2517 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>; 2518 2519 // ARMv4 2520 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2521 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2522 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 2523 2524 // mov lr, pc; b if callee is marked noreturn to avoid confusing the 2525 // return stack predictor. 2526 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins arm_bl_target:$func), 2527 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>, 2528 Requires<[IsARM]>, Sched<[WriteBr]>; 2529 2530 // push lr before the call 2531 def BL_PUSHLR : ARMPseudoInst<(outs), (ins GPRlr:$ra, arm_bl_target:$func), 2532 4, IIC_Br, 2533 []>, 2534 Requires<[IsARM]>, Sched<[WriteBr]>; 2535} 2536 2537let isBranch = 1, isTerminator = 1 in { 2538 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 2539 // a two-value operand where a dag node expects two operands. :( 2540 def Bcc : ABI<0b1010, (outs), (ins arm_br_target:$target), 2541 IIC_Br, "b", "\t$target", 2542 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>, 2543 Sched<[WriteBr]> { 2544 bits<24> target; 2545 let Inst{23-0} = target; 2546 let DecoderMethod = "DecodeBranchImmInstruction"; 2547 } 2548 2549 let isBarrier = 1 in { 2550 // B is "predicable" since it's just a Bcc with an 'always' condition. 2551 let isPredicable = 1 in 2552 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly 2553 // should be sufficient. 2554 // FIXME: Is B really a Barrier? That doesn't seem right. 2555 def B : ARMPseudoExpand<(outs), (ins arm_br_target:$target), 4, IIC_Br, 2556 [(br bb:$target)], (Bcc arm_br_target:$target, 2557 (ops 14, zero_reg))>, 2558 Sched<[WriteBr]>; 2559 2560 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in { 2561 def BR_JTr : ARMPseudoInst<(outs), 2562 (ins GPR:$target, i32imm:$jt), 2563 0, IIC_Br, 2564 [(ARMbrjt GPR:$target, tjumptable:$jt)]>, 2565 Sched<[WriteBr]>; 2566 def BR_JTm_i12 : ARMPseudoInst<(outs), 2567 (ins addrmode_imm12:$target, i32imm:$jt), 2568 0, IIC_Br, 2569 [(ARMbrjt (i32 (load addrmode_imm12:$target)), 2570 tjumptable:$jt)]>, Sched<[WriteBrTbl]>; 2571 def BR_JTm_rs : ARMPseudoInst<(outs), 2572 (ins ldst_so_reg:$target, i32imm:$jt), 2573 0, IIC_Br, 2574 [(ARMbrjt (i32 (load ldst_so_reg:$target)), 2575 tjumptable:$jt)]>, Sched<[WriteBrTbl]>; 2576 def BR_JTadd : ARMPseudoInst<(outs), 2577 (ins GPR:$target, GPR:$idx, i32imm:$jt), 2578 0, IIC_Br, 2579 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>, 2580 Sched<[WriteBrTbl]>; 2581 } // isNotDuplicable = 1, isIndirectBranch = 1 2582 } // isBarrier = 1 2583 2584} 2585 2586// BLX (immediate) 2587def BLXi : AXI<(outs), (ins arm_blx_target:$target), BrMiscFrm, NoItinerary, 2588 "blx\t$target", []>, 2589 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2590 let Inst{31-25} = 0b1111101; 2591 bits<25> target; 2592 let Inst{23-0} = target{24-1}; 2593 let Inst{24} = target{0}; 2594 let isCall = 1; 2595} 2596 2597// Branch and Exchange Jazelle 2598def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", 2599 [/* pattern left blank */]>, Sched<[WriteBr]> { 2600 bits<4> func; 2601 let Inst{23-20} = 0b0010; 2602 let Inst{19-8} = 0xfff; 2603 let Inst{7-4} = 0b0010; 2604 let Inst{3-0} = func; 2605 let isBranch = 1; 2606} 2607 2608// Tail calls. 2609 2610let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in { 2611 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>, 2612 Sched<[WriteBr]>; 2613 2614 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>, 2615 Sched<[WriteBr]>; 2616 2617 def TAILJMPd : ARMPseudoExpand<(outs), (ins arm_br_target:$dst), 2618 4, IIC_Br, [], 2619 (Bcc arm_br_target:$dst, (ops 14, zero_reg))>, 2620 Requires<[IsARM]>, Sched<[WriteBr]>; 2621 2622 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst), 2623 4, IIC_Br, [], 2624 (BX GPR:$dst)>, Sched<[WriteBr]>, 2625 Requires<[IsARM, HasV4T]>; 2626} 2627 2628// Secure Monitor Call is a system instruction. 2629def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", 2630 []>, Requires<[IsARM, HasTrustZone]> { 2631 bits<4> opt; 2632 let Inst{23-4} = 0b01100000000000000111; 2633 let Inst{3-0} = opt; 2634} 2635def : MnemonicAlias<"smi", "smc">; 2636 2637// Supervisor Call (Software Interrupt) 2638let isCall = 1, Uses = [SP] in { 2639def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>, 2640 Sched<[WriteBr]> { 2641 bits<24> svc; 2642 let Inst{23-0} = svc; 2643} 2644} 2645 2646// Store Return State 2647class SRSI<bit wb, string asm> 2648 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm, 2649 NoItinerary, asm, "", []> { 2650 bits<5> mode; 2651 let Inst{31-28} = 0b1111; 2652 let Inst{27-25} = 0b100; 2653 let Inst{22} = 1; 2654 let Inst{21} = wb; 2655 let Inst{20} = 0; 2656 let Inst{19-16} = 0b1101; // SP 2657 let Inst{15-5} = 0b00000101000; 2658 let Inst{4-0} = mode; 2659} 2660 2661def SRSDA : SRSI<0, "srsda\tsp, $mode"> { 2662 let Inst{24-23} = 0; 2663} 2664def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> { 2665 let Inst{24-23} = 0; 2666} 2667def SRSDB : SRSI<0, "srsdb\tsp, $mode"> { 2668 let Inst{24-23} = 0b10; 2669} 2670def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> { 2671 let Inst{24-23} = 0b10; 2672} 2673def SRSIA : SRSI<0, "srsia\tsp, $mode"> { 2674 let Inst{24-23} = 0b01; 2675} 2676def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> { 2677 let Inst{24-23} = 0b01; 2678} 2679def SRSIB : SRSI<0, "srsib\tsp, $mode"> { 2680 let Inst{24-23} = 0b11; 2681} 2682def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> { 2683 let Inst{24-23} = 0b11; 2684} 2685 2686def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>; 2687def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>; 2688 2689def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>; 2690def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>; 2691 2692def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>; 2693def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>; 2694 2695def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>; 2696def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>; 2697 2698// Return From Exception 2699class RFEI<bit wb, string asm> 2700 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm, 2701 NoItinerary, asm, "", []> { 2702 bits<4> Rn; 2703 let Inst{31-28} = 0b1111; 2704 let Inst{27-25} = 0b100; 2705 let Inst{22} = 0; 2706 let Inst{21} = wb; 2707 let Inst{20} = 1; 2708 let Inst{19-16} = Rn; 2709 let Inst{15-0} = 0xa00; 2710} 2711 2712def RFEDA : RFEI<0, "rfeda\t$Rn"> { 2713 let Inst{24-23} = 0; 2714} 2715def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> { 2716 let Inst{24-23} = 0; 2717} 2718def RFEDB : RFEI<0, "rfedb\t$Rn"> { 2719 let Inst{24-23} = 0b10; 2720} 2721def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> { 2722 let Inst{24-23} = 0b10; 2723} 2724def RFEIA : RFEI<0, "rfeia\t$Rn"> { 2725 let Inst{24-23} = 0b01; 2726} 2727def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> { 2728 let Inst{24-23} = 0b01; 2729} 2730def RFEIB : RFEI<0, "rfeib\t$Rn"> { 2731 let Inst{24-23} = 0b11; 2732} 2733def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> { 2734 let Inst{24-23} = 0b11; 2735} 2736 2737// Hypervisor Call is a system instruction 2738let isCall = 1 in { 2739def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary, 2740 "hvc", "\t$imm", []>, 2741 Requires<[IsARM, HasVirtualization]> { 2742 bits<16> imm; 2743 2744 // Even though HVC isn't predicable, it's encoding includes a condition field. 2745 // The instruction is undefined if the condition field is 0xf otherwise it is 2746 // unpredictable if it isn't condition AL (0xe). 2747 let Inst{31-28} = 0b1110; 2748 let Unpredictable{31-28} = 0b1111; 2749 let Inst{27-24} = 0b0001; 2750 let Inst{23-20} = 0b0100; 2751 let Inst{19-8} = imm{15-4}; 2752 let Inst{7-4} = 0b0111; 2753 let Inst{3-0} = imm{3-0}; 2754} 2755} 2756 2757// Return from exception in Hypervisor mode. 2758let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in 2759def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>, 2760 Requires<[IsARM, HasVirtualization]> { 2761 let Inst{23-0} = 0b011000000000000001101110; 2762} 2763 2764//===----------------------------------------------------------------------===// 2765// Load / Store Instructions. 2766// 2767 2768// Load 2769 2770 2771defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si, load>; 2772defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si, 2773 zextloadi8>; 2774defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si, store>; 2775defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si, 2776 truncstorei8>; 2777 2778// Special LDR for loads from non-pc-relative constpools. 2779let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0, 2780 isReMaterializable = 1, isCodeGenOnly = 1 in 2781def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 2782 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", 2783 []> { 2784 bits<4> Rt; 2785 bits<17> addr; 2786 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2787 let Inst{19-16} = 0b1111; 2788 let Inst{15-12} = Rt; 2789 let Inst{11-0} = addr{11-0}; // imm12 2790} 2791 2792// Loads with zero extension 2793def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2794 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr", 2795 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>; 2796 2797// Loads with sign extension 2798def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2799 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr", 2800 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>; 2801 2802def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2803 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr", 2804 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>; 2805 2806let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in { 2807 // Load doubleword 2808 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr), 2809 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>, 2810 Requires<[IsARM, HasV5TE]>; 2811} 2812 2813let mayLoad = 1, hasSideEffects = 0, hasNoSchedulingInfo = 1 in { 2814def LOADDUAL : ARMPseudoInst<(outs GPRPairOp:$Rt), (ins addrmode3:$addr), 2815 64, IIC_iLoad_d_r, []>, 2816 Requires<[IsARM, HasV5TE]> { 2817 let AM = AddrMode3; 2818} 2819} 2820 2821def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2822 NoItinerary, "lda", "\t$Rt, $addr", []>; 2823def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2824 NoItinerary, "ldab", "\t$Rt, $addr", []>; 2825def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2826 NoItinerary, "ldah", "\t$Rt, $addr", []>; 2827 2828// Indexed loads 2829multiclass AI2_ldridx<bit isByte, string opc, 2830 InstrItinClass iii, InstrItinClass iir> { 2831 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2832 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii, 2833 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2834 bits<17> addr; 2835 let Inst{25} = 0; 2836 let Inst{23} = addr{12}; 2837 let Inst{19-16} = addr{16-13}; 2838 let Inst{11-0} = addr{11-0}; 2839 let DecoderMethod = "DecodeLDRPreImm"; 2840 } 2841 2842 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2843 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir, 2844 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2845 bits<17> addr; 2846 let Inst{25} = 1; 2847 let Inst{23} = addr{12}; 2848 let Inst{19-16} = addr{16-13}; 2849 let Inst{11-0} = addr{11-0}; 2850 let Inst{4} = 0; 2851 let DecoderMethod = "DecodeLDRPreReg"; 2852 } 2853 2854 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2855 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2856 IndexModePost, LdFrm, iir, 2857 opc, "\t$Rt, $addr, $offset", 2858 "$addr.base = $Rn_wb", []> { 2859 // {12} isAdd 2860 // {11-0} imm12/Rm 2861 bits<14> offset; 2862 bits<4> addr; 2863 let Inst{25} = 1; 2864 let Inst{23} = offset{12}; 2865 let Inst{19-16} = addr; 2866 let Inst{11-0} = offset{11-0}; 2867 let Inst{4} = 0; 2868 2869 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2870 } 2871 2872 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2873 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2874 IndexModePost, LdFrm, iii, 2875 opc, "\t$Rt, $addr, $offset", 2876 "$addr.base = $Rn_wb", []> { 2877 // {12} isAdd 2878 // {11-0} imm12/Rm 2879 bits<14> offset; 2880 bits<4> addr; 2881 let Inst{25} = 0; 2882 let Inst{23} = offset{12}; 2883 let Inst{19-16} = addr; 2884 let Inst{11-0} = offset{11-0}; 2885 2886 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2887 } 2888 2889} 2890 2891let mayLoad = 1, hasSideEffects = 0 in { 2892// FIXME: for LDR_PRE_REG etc. the itinerary should be either IIC_iLoad_ru or 2893// IIC_iLoad_siu depending on whether it the offset register is shifted. 2894defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>; 2895defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>; 2896} 2897 2898multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> { 2899 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2900 (ins addrmode3_pre:$addr), IndexModePre, 2901 LdMiscFrm, itin, 2902 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2903 bits<14> addr; 2904 let Inst{23} = addr{8}; // U bit 2905 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2906 let Inst{19-16} = addr{12-9}; // Rn 2907 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2908 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2909 let DecoderMethod = "DecodeAddrMode3Instruction"; 2910 } 2911 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2912 (ins addr_offset_none:$addr, am3offset:$offset), 2913 IndexModePost, LdMiscFrm, itin, 2914 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", 2915 []> { 2916 bits<10> offset; 2917 bits<4> addr; 2918 let Inst{23} = offset{8}; // U bit 2919 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2920 let Inst{19-16} = addr; 2921 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2922 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2923 let DecoderMethod = "DecodeAddrMode3Instruction"; 2924 } 2925} 2926 2927let mayLoad = 1, hasSideEffects = 0 in { 2928defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>; 2929defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>; 2930defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>; 2931let hasExtraDefRegAllocReq = 1 in { 2932def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2933 (ins addrmode3_pre:$addr), IndexModePre, 2934 LdMiscFrm, IIC_iLoad_d_ru, 2935 "ldrd", "\t$Rt, $Rt2, $addr!", 2936 "$addr.base = $Rn_wb", []> { 2937 bits<14> addr; 2938 let Inst{23} = addr{8}; // U bit 2939 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2940 let Inst{19-16} = addr{12-9}; // Rn 2941 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2942 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2943 let DecoderMethod = "DecodeAddrMode3Instruction"; 2944} 2945def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2946 (ins addr_offset_none:$addr, am3offset:$offset), 2947 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru, 2948 "ldrd", "\t$Rt, $Rt2, $addr, $offset", 2949 "$addr.base = $Rn_wb", []> { 2950 bits<10> offset; 2951 bits<4> addr; 2952 let Inst{23} = offset{8}; // U bit 2953 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2954 let Inst{19-16} = addr; 2955 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2956 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2957 let DecoderMethod = "DecodeAddrMode3Instruction"; 2958} 2959} // hasExtraDefRegAllocReq = 1 2960} // mayLoad = 1, hasSideEffects = 0 2961 2962// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT. 2963let mayLoad = 1, hasSideEffects = 0 in { 2964def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2965 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2966 IndexModePost, LdFrm, IIC_iLoad_ru, 2967 "ldrt", "\t$Rt, $addr, $offset", 2968 "$addr.base = $Rn_wb", []> { 2969 // {12} isAdd 2970 // {11-0} imm12/Rm 2971 bits<14> offset; 2972 bits<4> addr; 2973 let Inst{25} = 1; 2974 let Inst{23} = offset{12}; 2975 let Inst{21} = 1; // overwrite 2976 let Inst{19-16} = addr; 2977 let Inst{11-5} = offset{11-5}; 2978 let Inst{4} = 0; 2979 let Inst{3-0} = offset{3-0}; 2980 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2981} 2982 2983def LDRT_POST_IMM 2984 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2985 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2986 IndexModePost, LdFrm, IIC_iLoad_ru, 2987 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2988 // {12} isAdd 2989 // {11-0} imm12/Rm 2990 bits<14> offset; 2991 bits<4> addr; 2992 let Inst{25} = 0; 2993 let Inst{23} = offset{12}; 2994 let Inst{21} = 1; // overwrite 2995 let Inst{19-16} = addr; 2996 let Inst{11-0} = offset{11-0}; 2997 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2998} 2999 3000def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 3001 (ins addr_offset_none:$addr, am2offset_reg:$offset), 3002 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 3003 "ldrbt", "\t$Rt, $addr, $offset", 3004 "$addr.base = $Rn_wb", []> { 3005 // {12} isAdd 3006 // {11-0} imm12/Rm 3007 bits<14> offset; 3008 bits<4> addr; 3009 let Inst{25} = 1; 3010 let Inst{23} = offset{12}; 3011 let Inst{21} = 1; // overwrite 3012 let Inst{19-16} = addr; 3013 let Inst{11-5} = offset{11-5}; 3014 let Inst{4} = 0; 3015 let Inst{3-0} = offset{3-0}; 3016 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3017} 3018 3019def LDRBT_POST_IMM 3020 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 3021 (ins addr_offset_none:$addr, am2offset_imm:$offset), 3022 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 3023 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3024 // {12} isAdd 3025 // {11-0} imm12/Rm 3026 bits<14> offset; 3027 bits<4> addr; 3028 let Inst{25} = 0; 3029 let Inst{23} = offset{12}; 3030 let Inst{21} = 1; // overwrite 3031 let Inst{19-16} = addr; 3032 let Inst{11-0} = offset{11-0}; 3033 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3034} 3035 3036multiclass AI3ldrT<bits<4> op, string opc> { 3037 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb), 3038 (ins addr_offset_none:$addr, postidx_imm8:$offset), 3039 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 3040 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 3041 bits<9> offset; 3042 let Inst{23} = offset{8}; 3043 let Inst{22} = 1; 3044 let Inst{11-8} = offset{7-4}; 3045 let Inst{3-0} = offset{3-0}; 3046 } 3047 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb), 3048 (ins addr_offset_none:$addr, postidx_reg:$Rm), 3049 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 3050 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 3051 bits<5> Rm; 3052 let Inst{23} = Rm{4}; 3053 let Inst{22} = 0; 3054 let Inst{11-8} = 0; 3055 let Unpredictable{11-8} = 0b1111; 3056 let Inst{3-0} = Rm{3-0}; 3057 let DecoderMethod = "DecodeLDR"; 3058 } 3059 3060 def ii : ARMAsmPseudo<!strconcat(opc, "${p} $Rt, $addr"), 3061 (ins addr_offset_none:$addr, pred:$p), (outs GPR:$Rt)>; 3062} 3063 3064defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">; 3065defm LDRHT : AI3ldrT<0b1011, "ldrht">; 3066defm LDRSHT : AI3ldrT<0b1111, "ldrsht">; 3067} 3068 3069def LDRT_POST 3070 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 3071 (outs GPR:$Rt)>; 3072 3073def LDRBT_POST 3074 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 3075 (outs GPR:$Rt)>; 3076 3077// Pseudo instruction ldr Rt, =immediate 3078def LDRConstPool 3079 : ARMAsmPseudo<"ldr${q} $Rt, $immediate", 3080 (ins const_pool_asm_imm:$immediate, pred:$q), 3081 (outs GPR:$Rt)>; 3082 3083// Store 3084 3085// Stores with truncate 3086def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm, 3087 IIC_iStore_bh_r, "strh", "\t$Rt, $addr", 3088 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>; 3089 3090// Store doubleword 3091let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { 3092 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr), 3093 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>, 3094 Requires<[IsARM, HasV5TE]> { 3095 let Inst{21} = 0; 3096 } 3097} 3098 3099let mayStore = 1, hasSideEffects = 0, hasNoSchedulingInfo = 1 in { 3100def STOREDUAL : ARMPseudoInst<(outs), (ins GPRPairOp:$Rt, addrmode3:$addr), 3101 64, IIC_iStore_d_r, []>, 3102 Requires<[IsARM, HasV5TE]> { 3103 let AM = AddrMode3; 3104} 3105} 3106 3107// Indexed stores 3108multiclass AI2_stridx<bit isByte, string opc, 3109 InstrItinClass iii, InstrItinClass iir> { 3110 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 3111 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre, 3112 StFrm, iii, 3113 opc, "\t$Rt, $addr!", 3114 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3115 bits<17> addr; 3116 let Inst{25} = 0; 3117 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 3118 let Inst{19-16} = addr{16-13}; // Rn 3119 let Inst{11-0} = addr{11-0}; // imm12 3120 let DecoderMethod = "DecodeSTRPreImm"; 3121 } 3122 3123 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 3124 (ins GPR:$Rt, ldst_so_reg:$addr), 3125 IndexModePre, StFrm, iir, 3126 opc, "\t$Rt, $addr!", 3127 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3128 bits<17> addr; 3129 let Inst{25} = 1; 3130 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 3131 let Inst{19-16} = addr{16-13}; // Rn 3132 let Inst{11-0} = addr{11-0}; 3133 let Inst{4} = 0; // Inst{4} = 0 3134 let DecoderMethod = "DecodeSTRPreReg"; 3135 } 3136 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 3137 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3138 IndexModePost, StFrm, iir, 3139 opc, "\t$Rt, $addr, $offset", 3140 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3141 // {12} isAdd 3142 // {11-0} imm12/Rm 3143 bits<14> offset; 3144 bits<4> addr; 3145 let Inst{25} = 1; 3146 let Inst{23} = offset{12}; 3147 let Inst{19-16} = addr; 3148 let Inst{11-0} = offset{11-0}; 3149 let Inst{4} = 0; 3150 3151 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3152 } 3153 3154 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 3155 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3156 IndexModePost, StFrm, iii, 3157 opc, "\t$Rt, $addr, $offset", 3158 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3159 // {12} isAdd 3160 // {11-0} imm12/Rm 3161 bits<14> offset; 3162 bits<4> addr; 3163 let Inst{25} = 0; 3164 let Inst{23} = offset{12}; 3165 let Inst{19-16} = addr; 3166 let Inst{11-0} = offset{11-0}; 3167 3168 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3169 } 3170} 3171 3172let mayStore = 1, hasSideEffects = 0 in { 3173// FIXME: for STR_PRE_REG etc. the itinerary should be either IIC_iStore_ru or 3174// IIC_iStore_siu depending on whether it the offset register is shifted. 3175defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>; 3176defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>; 3177} 3178 3179def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 3180 am2offset_reg:$offset), 3181 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr, 3182 am2offset_reg:$offset)>; 3183def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 3184 am2offset_imm:$offset), 3185 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr, 3186 am2offset_imm:$offset)>; 3187def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 3188 am2offset_reg:$offset), 3189 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr, 3190 am2offset_reg:$offset)>; 3191def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 3192 am2offset_imm:$offset), 3193 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr, 3194 am2offset_imm:$offset)>; 3195 3196// Pseudo-instructions for pattern matching the pre-indexed stores. We can't 3197// put the patterns on the instruction definitions directly as ISel wants 3198// the address base and offset to be separate operands, not a single 3199// complex operand like we represent the instructions themselves. The 3200// pseudos map between the two. 3201let usesCustomInserter = 1, 3202 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in { 3203def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3204 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 3205 4, IIC_iStore_ru, 3206 [(set GPR:$Rn_wb, 3207 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 3208def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3209 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 3210 4, IIC_iStore_ru, 3211 [(set GPR:$Rn_wb, 3212 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 3213def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3214 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 3215 4, IIC_iStore_ru, 3216 [(set GPR:$Rn_wb, 3217 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 3218def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3219 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 3220 4, IIC_iStore_ru, 3221 [(set GPR:$Rn_wb, 3222 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 3223def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3224 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p), 3225 4, IIC_iStore_ru, 3226 [(set GPR:$Rn_wb, 3227 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>; 3228} 3229 3230 3231 3232def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb), 3233 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre, 3234 StMiscFrm, IIC_iStore_bh_ru, 3235 "strh", "\t$Rt, $addr!", 3236 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3237 bits<14> addr; 3238 let Inst{23} = addr{8}; // U bit 3239 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 3240 let Inst{19-16} = addr{12-9}; // Rn 3241 let Inst{11-8} = addr{7-4}; // imm7_4/zero 3242 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 3243 let DecoderMethod = "DecodeAddrMode3Instruction"; 3244} 3245 3246def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb), 3247 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset), 3248 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, 3249 "strh", "\t$Rt, $addr, $offset", 3250 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", 3251 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt, 3252 addr_offset_none:$addr, 3253 am3offset:$offset))]> { 3254 bits<10> offset; 3255 bits<4> addr; 3256 let Inst{23} = offset{8}; // U bit 3257 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 3258 let Inst{19-16} = addr; 3259 let Inst{11-8} = offset{7-4}; // imm7_4/zero 3260 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 3261 let DecoderMethod = "DecodeAddrMode3Instruction"; 3262} 3263 3264let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { 3265def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb), 3266 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr), 3267 IndexModePre, StMiscFrm, IIC_iStore_d_ru, 3268 "strd", "\t$Rt, $Rt2, $addr!", 3269 "$addr.base = $Rn_wb", []> { 3270 bits<14> addr; 3271 let Inst{23} = addr{8}; // U bit 3272 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 3273 let Inst{19-16} = addr{12-9}; // Rn 3274 let Inst{11-8} = addr{7-4}; // imm7_4/zero 3275 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 3276 let DecoderMethod = "DecodeAddrMode3Instruction"; 3277} 3278 3279def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb), 3280 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr, 3281 am3offset:$offset), 3282 IndexModePost, StMiscFrm, IIC_iStore_d_ru, 3283 "strd", "\t$Rt, $Rt2, $addr, $offset", 3284 "$addr.base = $Rn_wb", []> { 3285 bits<10> offset; 3286 bits<4> addr; 3287 let Inst{23} = offset{8}; // U bit 3288 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 3289 let Inst{19-16} = addr; 3290 let Inst{11-8} = offset{7-4}; // imm7_4/zero 3291 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 3292 let DecoderMethod = "DecodeAddrMode3Instruction"; 3293} 3294} // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 3295 3296// STRT, STRBT, and STRHT 3297 3298def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 3299 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3300 IndexModePost, StFrm, IIC_iStore_bh_ru, 3301 "strbt", "\t$Rt, $addr, $offset", 3302 "$addr.base = $Rn_wb", []> { 3303 // {12} isAdd 3304 // {11-0} imm12/Rm 3305 bits<14> offset; 3306 bits<4> addr; 3307 let Inst{25} = 1; 3308 let Inst{23} = offset{12}; 3309 let Inst{21} = 1; // overwrite 3310 let Inst{19-16} = addr; 3311 let Inst{11-5} = offset{11-5}; 3312 let Inst{4} = 0; 3313 let Inst{3-0} = offset{3-0}; 3314 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3315} 3316 3317def STRBT_POST_IMM 3318 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 3319 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3320 IndexModePost, StFrm, IIC_iStore_bh_ru, 3321 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3322 // {12} isAdd 3323 // {11-0} imm12/Rm 3324 bits<14> offset; 3325 bits<4> addr; 3326 let Inst{25} = 0; 3327 let Inst{23} = offset{12}; 3328 let Inst{21} = 1; // overwrite 3329 let Inst{19-16} = addr; 3330 let Inst{11-0} = offset{11-0}; 3331 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3332} 3333 3334def STRBT_POST 3335 : ARMAsmPseudo<"strbt${q} $Rt, $addr", 3336 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 3337 3338let mayStore = 1, hasSideEffects = 0 in { 3339def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 3340 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3341 IndexModePost, StFrm, IIC_iStore_ru, 3342 "strt", "\t$Rt, $addr, $offset", 3343 "$addr.base = $Rn_wb", []> { 3344 // {12} isAdd 3345 // {11-0} imm12/Rm 3346 bits<14> offset; 3347 bits<4> addr; 3348 let Inst{25} = 1; 3349 let Inst{23} = offset{12}; 3350 let Inst{21} = 1; // overwrite 3351 let Inst{19-16} = addr; 3352 let Inst{11-5} = offset{11-5}; 3353 let Inst{4} = 0; 3354 let Inst{3-0} = offset{3-0}; 3355 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3356} 3357 3358def STRT_POST_IMM 3359 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 3360 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3361 IndexModePost, StFrm, IIC_iStore_ru, 3362 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3363 // {12} isAdd 3364 // {11-0} imm12/Rm 3365 bits<14> offset; 3366 bits<4> addr; 3367 let Inst{25} = 0; 3368 let Inst{23} = offset{12}; 3369 let Inst{21} = 1; // overwrite 3370 let Inst{19-16} = addr; 3371 let Inst{11-0} = offset{11-0}; 3372 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3373} 3374} 3375 3376def STRT_POST 3377 : ARMAsmPseudo<"strt${q} $Rt, $addr", 3378 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 3379 3380multiclass AI3strT<bits<4> op, string opc> { 3381 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 3382 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset), 3383 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 3384 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 3385 bits<9> offset; 3386 let Inst{23} = offset{8}; 3387 let Inst{22} = 1; 3388 let Inst{11-8} = offset{7-4}; 3389 let Inst{3-0} = offset{3-0}; 3390 } 3391 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 3392 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm), 3393 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 3394 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 3395 bits<5> Rm; 3396 let Inst{23} = Rm{4}; 3397 let Inst{22} = 0; 3398 let Inst{11-8} = 0; 3399 let Inst{3-0} = Rm{3-0}; 3400 } 3401} 3402 3403 3404defm STRHT : AI3strT<0b1011, "strht">; 3405 3406def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3407 NoItinerary, "stl", "\t$Rt, $addr", []>; 3408def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3409 NoItinerary, "stlb", "\t$Rt, $addr", []>; 3410def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3411 NoItinerary, "stlh", "\t$Rt, $addr", []>; 3412 3413//===----------------------------------------------------------------------===// 3414// Load / store multiple Instructions. 3415// 3416 3417multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f, 3418 InstrItinClass itin, InstrItinClass itin_upd> { 3419 // IA is the default, so no need for an explicit suffix on the 3420 // mnemonic here. Without it is the canonical spelling. 3421 def IA : 3422 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3423 IndexModeNone, f, itin, 3424 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> { 3425 let Inst{24-23} = 0b01; // Increment After 3426 let Inst{22} = P_bit; 3427 let Inst{21} = 0; // No writeback 3428 let Inst{20} = L_bit; 3429 } 3430 def IA_UPD : 3431 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3432 IndexModeUpd, f, itin_upd, 3433 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3434 let Inst{24-23} = 0b01; // Increment After 3435 let Inst{22} = P_bit; 3436 let Inst{21} = 1; // Writeback 3437 let Inst{20} = L_bit; 3438 3439 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3440 } 3441 def DA : 3442 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3443 IndexModeNone, f, itin, 3444 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> { 3445 let Inst{24-23} = 0b00; // Decrement After 3446 let Inst{22} = P_bit; 3447 let Inst{21} = 0; // No writeback 3448 let Inst{20} = L_bit; 3449 } 3450 def DA_UPD : 3451 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3452 IndexModeUpd, f, itin_upd, 3453 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3454 let Inst{24-23} = 0b00; // Decrement After 3455 let Inst{22} = P_bit; 3456 let Inst{21} = 1; // Writeback 3457 let Inst{20} = L_bit; 3458 3459 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3460 } 3461 def DB : 3462 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3463 IndexModeNone, f, itin, 3464 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> { 3465 let Inst{24-23} = 0b10; // Decrement Before 3466 let Inst{22} = P_bit; 3467 let Inst{21} = 0; // No writeback 3468 let Inst{20} = L_bit; 3469 } 3470 def DB_UPD : 3471 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3472 IndexModeUpd, f, itin_upd, 3473 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3474 let Inst{24-23} = 0b10; // Decrement Before 3475 let Inst{22} = P_bit; 3476 let Inst{21} = 1; // Writeback 3477 let Inst{20} = L_bit; 3478 3479 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3480 } 3481 def IB : 3482 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3483 IndexModeNone, f, itin, 3484 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> { 3485 let Inst{24-23} = 0b11; // Increment Before 3486 let Inst{22} = P_bit; 3487 let Inst{21} = 0; // No writeback 3488 let Inst{20} = L_bit; 3489 } 3490 def IB_UPD : 3491 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3492 IndexModeUpd, f, itin_upd, 3493 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3494 let Inst{24-23} = 0b11; // Increment Before 3495 let Inst{22} = P_bit; 3496 let Inst{21} = 1; // Writeback 3497 let Inst{20} = L_bit; 3498 3499 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3500 } 3501} 3502 3503let hasSideEffects = 0 in { 3504 3505let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in 3506defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m, 3507 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">; 3508 3509let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3510defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m, 3511 IIC_iStore_mu>, 3512 ComplexDeprecationPredicate<"ARMStore">; 3513 3514} // hasSideEffects 3515 3516// FIXME: remove when we have a way to marking a MI with these properties. 3517// FIXME: Should pc be an implicit operand like PICADD, etc? 3518let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 3519 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in 3520def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, 3521 reglist:$regs, variable_ops), 3522 4, IIC_iLoad_mBr, [], 3523 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, 3524 RegConstraint<"$Rn = $wb">; 3525 3526let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 3527defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m, 3528 IIC_iLoad_mu>; 3529 3530let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3531defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m, 3532 IIC_iStore_mu>; 3533 3534 3535 3536//===----------------------------------------------------------------------===// 3537// Move Instructions. 3538// 3539 3540let hasSideEffects = 0, isMoveReg = 1 in 3541def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr, 3542 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3543 bits<4> Rd; 3544 bits<4> Rm; 3545 3546 let Inst{19-16} = 0b0000; 3547 let Inst{11-4} = 0b00000000; 3548 let Inst{25} = 0; 3549 let Inst{3-0} = Rm; 3550 let Inst{15-12} = Rd; 3551} 3552 3553// A version for the smaller set of tail call registers. 3554let hasSideEffects = 0 in 3555def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm, 3556 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3557 bits<4> Rd; 3558 bits<4> Rm; 3559 3560 let Inst{11-4} = 0b00000000; 3561 let Inst{25} = 0; 3562 let Inst{3-0} = Rm; 3563 let Inst{15-12} = Rd; 3564} 3565 3566def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src), 3567 DPSoRegRegFrm, IIC_iMOVsr, 3568 "mov", "\t$Rd, $src", 3569 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP, 3570 Sched<[WriteALU]> { 3571 bits<4> Rd; 3572 bits<12> src; 3573 let Inst{15-12} = Rd; 3574 let Inst{19-16} = 0b0000; 3575 let Inst{11-8} = src{11-8}; 3576 let Inst{7} = 0; 3577 let Inst{6-5} = src{6-5}; 3578 let Inst{4} = 1; 3579 let Inst{3-0} = src{3-0}; 3580 let Inst{25} = 0; 3581} 3582 3583def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src), 3584 DPSoRegImmFrm, IIC_iMOVsr, 3585 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>, 3586 UnaryDP, Sched<[WriteALU]> { 3587 bits<4> Rd; 3588 bits<12> src; 3589 let Inst{15-12} = Rd; 3590 let Inst{19-16} = 0b0000; 3591 let Inst{11-5} = src{11-5}; 3592 let Inst{4} = 0; 3593 let Inst{3-0} = src{3-0}; 3594 let Inst{25} = 0; 3595} 3596 3597let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3598def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi, 3599 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP, 3600 Sched<[WriteALU]> { 3601 bits<4> Rd; 3602 bits<12> imm; 3603 let Inst{25} = 1; 3604 let Inst{15-12} = Rd; 3605 let Inst{19-16} = 0b0000; 3606 let Inst{11-0} = imm; 3607} 3608 3609let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3610def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm), 3611 DPFrm, IIC_iMOVi, 3612 "movw", "\t$Rd, $imm", 3613 [(set GPR:$Rd, imm0_65535:$imm)]>, 3614 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> { 3615 bits<4> Rd; 3616 bits<16> imm; 3617 let Inst{15-12} = Rd; 3618 let Inst{11-0} = imm{11-0}; 3619 let Inst{19-16} = imm{15-12}; 3620 let Inst{20} = 0; 3621 let Inst{25} = 1; 3622 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3623} 3624 3625def : InstAlias<"mov${p} $Rd, $imm", 3626 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p), 0>, 3627 Requires<[IsARM, HasV6T2]>; 3628 3629def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3630 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3631 Sched<[WriteALU]>; 3632 3633let Constraints = "$src = $Rd" in { 3634def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd), 3635 (ins GPR:$src, imm0_65535_expr:$imm), 3636 DPFrm, IIC_iMOVi, 3637 "movt", "\t$Rd, $imm", 3638 [(set GPRnopc:$Rd, 3639 (or (and GPR:$src, 0xffff), 3640 lo16AllZero:$imm))]>, UnaryDP, 3641 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> { 3642 bits<4> Rd; 3643 bits<16> imm; 3644 let Inst{15-12} = Rd; 3645 let Inst{11-0} = imm{11-0}; 3646 let Inst{19-16} = imm{15-12}; 3647 let Inst{20} = 0; 3648 let Inst{25} = 1; 3649 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3650} 3651 3652def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3653 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3654 Sched<[WriteALU]>; 3655 3656} // Constraints 3657 3658def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>, 3659 Requires<[IsARM, HasV6T2]>; 3660 3661let Uses = [CPSR] in 3662def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, 3663 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP, 3664 Requires<[IsARM]>, Sched<[WriteALU]>; 3665 3666// These aren't really mov instructions, but we have to define them this way 3667// due to flag operands. 3668 3669let Defs = [CPSR] in { 3670def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3671 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP, 3672 Sched<[WriteALU]>, Requires<[IsARM]>; 3673def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3674 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP, 3675 Sched<[WriteALU]>, Requires<[IsARM]>; 3676} 3677 3678//===----------------------------------------------------------------------===// 3679// Extend Instructions. 3680// 3681 3682// Sign extenders 3683 3684def SXTB : AI_ext_rrot<0b01101010, 3685 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 3686def SXTH : AI_ext_rrot<0b01101011, 3687 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 3688 3689def SXTAB : AI_exta_rrot<0b01101010, 3690 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 3691def SXTAH : AI_exta_rrot<0b01101011, 3692 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 3693 3694def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, rot_imm:$rot), i8)), 3695 (SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3696def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, imm8_or_16:$rot), 3697 i16)), 3698 (SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3699 3700def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">; 3701def : ARMV6Pat<(int_arm_sxtb16 GPR:$Src), 3702 (SXTB16 GPR:$Src, 0)>; 3703def : ARMV6Pat<(int_arm_sxtb16 (rotr GPR:$Src, rot_imm:$rot)), 3704 (SXTB16 GPR:$Src, rot_imm:$rot)>; 3705 3706def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; 3707def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, GPR:$RHS), 3708 (SXTAB16 GPR:$LHS, GPR:$RHS, 0)>; 3709def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, (rotr GPR:$RHS, rot_imm:$rot)), 3710 (SXTAB16 GPR:$LHS, GPR:$RHS, rot_imm:$rot)>; 3711 3712// Zero extenders 3713 3714let AddedComplexity = 16 in { 3715def UXTB : AI_ext_rrot<0b01101110, 3716 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 3717def UXTH : AI_ext_rrot<0b01101111, 3718 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 3719def UXTB16 : AI_ext_rrot<0b01101100, 3720 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 3721 3722// FIXME: This pattern incorrectly assumes the shl operator is a rotate. 3723// The transformation should probably be done as a combiner action 3724// instead so we can include a check for masking back in the upper 3725// eight bits of the source into the lower eight bits of the result. 3726//def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 3727// (UXTB16r_rot GPR:$Src, 3)>; 3728def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 3729 (UXTB16 GPR:$Src, 1)>; 3730def : ARMV6Pat<(int_arm_uxtb16 GPR:$Src), 3731 (UXTB16 GPR:$Src, 0)>; 3732def : ARMV6Pat<(int_arm_uxtb16 (rotr GPR:$Src, rot_imm:$rot)), 3733 (UXTB16 GPR:$Src, rot_imm:$rot)>; 3734 3735def UXTAB : AI_exta_rrot<0b01101110, "uxtab", 3736 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 3737def UXTAH : AI_exta_rrot<0b01101111, "uxtah", 3738 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 3739 3740def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), 0xFF)), 3741 (UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3742def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), 0xFFFF)), 3743 (UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3744} 3745 3746// This isn't safe in general, the add is two 16-bit units, not a 32-bit add. 3747def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">; 3748def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, GPR:$RHS), 3749 (UXTAB16 GPR:$LHS, GPR:$RHS, 0)>; 3750def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, (rotr GPR:$RHS, rot_imm:$rot)), 3751 (UXTAB16 GPR:$LHS, GPR:$RHS, rot_imm:$rot)>; 3752 3753 3754def SBFX : I<(outs GPRnopc:$Rd), 3755 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3756 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3757 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3758 Requires<[IsARM, HasV6T2]> { 3759 bits<4> Rd; 3760 bits<4> Rn; 3761 bits<5> lsb; 3762 bits<5> width; 3763 let Inst{27-21} = 0b0111101; 3764 let Inst{6-4} = 0b101; 3765 let Inst{20-16} = width; 3766 let Inst{15-12} = Rd; 3767 let Inst{11-7} = lsb; 3768 let Inst{3-0} = Rn; 3769} 3770 3771def UBFX : I<(outs GPRnopc:$Rd), 3772 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3773 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3774 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3775 Requires<[IsARM, HasV6T2]> { 3776 bits<4> Rd; 3777 bits<4> Rn; 3778 bits<5> lsb; 3779 bits<5> width; 3780 let Inst{27-21} = 0b0111111; 3781 let Inst{6-4} = 0b101; 3782 let Inst{20-16} = width; 3783 let Inst{15-12} = Rd; 3784 let Inst{11-7} = lsb; 3785 let Inst{3-0} = Rn; 3786} 3787 3788//===----------------------------------------------------------------------===// 3789// Arithmetic Instructions. 3790// 3791 3792let isAdd = 1 in 3793defm ADD : AsI1_bin_irs<0b0100, "add", 3794 IIC_iALUi, IIC_iALUr, IIC_iALUsr, add, 1>; 3795defm SUB : AsI1_bin_irs<0b0010, "sub", 3796 IIC_iALUi, IIC_iALUr, IIC_iALUsr, sub>; 3797 3798// ADD and SUB with 's' bit set. 3799// 3800// Currently, ADDS/SUBS are pseudo opcodes that exist only in the 3801// selection DAG. They are "lowered" to real ADD/SUB opcodes by 3802// AdjustInstrPostInstrSelection where we determine whether or not to 3803// set the "s" bit based on CPSR liveness. 3804// 3805// FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen 3806// support for an optional CPSR definition that corresponds to the DAG 3807// node's second value. We can then eliminate the implicit def of CPSR. 3808let isAdd = 1 in 3809defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMaddc, 1>; 3810defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>; 3811 3812def : ARMPat<(ARMsubs GPR:$Rn, mod_imm:$imm), (SUBSri $Rn, mod_imm:$imm)>; 3813def : ARMPat<(ARMsubs GPR:$Rn, GPR:$Rm), (SUBSrr $Rn, $Rm)>; 3814def : ARMPat<(ARMsubs GPR:$Rn, so_reg_imm:$shift), 3815 (SUBSrsi $Rn, so_reg_imm:$shift)>; 3816def : ARMPat<(ARMsubs GPR:$Rn, so_reg_reg:$shift), 3817 (SUBSrsr $Rn, so_reg_reg:$shift)>; 3818 3819 3820let isAdd = 1 in 3821defm ADC : AI1_adde_sube_irs<0b0101, "adc", ARMadde, 1>; 3822defm SBC : AI1_adde_sube_irs<0b0110, "sbc", ARMsube>; 3823 3824defm RSB : AsI1_rbin_irs<0b0011, "rsb", 3825 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3826 sub>; 3827 3828// FIXME: Eliminate them if we can write def : Pat patterns which defines 3829// CPSR and the implicit def of CPSR is not needed. 3830defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>; 3831 3832defm RSC : AI1_rsc_irs<0b0111, "rsc", ARMsube>; 3833 3834// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 3835// The assume-no-carry-in form uses the negation of the input since add/sub 3836// assume opposite meanings of the carry flag (i.e., carry == !borrow). 3837// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 3838// details. 3839def : ARMPat<(add GPR:$src, mod_imm_neg:$imm), 3840 (SUBri GPR:$src, mod_imm_neg:$imm)>; 3841def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm), 3842 (SUBSri GPR:$src, mod_imm_neg:$imm)>; 3843 3844def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm), 3845 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3846 Requires<[IsARM, HasV6T2]>; 3847def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm), 3848 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3849 Requires<[IsARM, HasV6T2]>; 3850 3851// The with-carry-in form matches bitwise not instead of the negation. 3852// Effectively, the inverse interpretation of the carry flag already accounts 3853// for part of the negation. 3854def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR), 3855 (SBCri GPR:$src, mod_imm_not:$imm)>; 3856def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR), 3857 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>, 3858 Requires<[IsARM, HasV6T2]>; 3859 3860// Note: These are implemented in C++ code, because they have to generate 3861// ADD/SUBrs instructions, which use a complex pattern that a xform function 3862// cannot produce. 3863// (mul X, 2^n+1) -> (add (X << n), X) 3864// (mul X, 2^n-1) -> (rsb X, (X << n)) 3865 3866// ARM Arithmetic Instruction 3867// GPR:$dst = GPR:$a op GPR:$b 3868class AAI<bits<8> op27_20, bits<8> op11_4, string opc, 3869 list<dag> pattern = [], 3870 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm), 3871 string asm = "\t$Rd, $Rn, $Rm"> 3872 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>, 3873 Sched<[WriteALU, ReadALU, ReadALU]> { 3874 bits<4> Rn; 3875 bits<4> Rd; 3876 bits<4> Rm; 3877 let Inst{27-20} = op27_20; 3878 let Inst{11-4} = op11_4; 3879 let Inst{19-16} = Rn; 3880 let Inst{15-12} = Rd; 3881 let Inst{3-0} = Rm; 3882 3883 let Unpredictable{11-8} = 0b1111; 3884} 3885 3886// Wrappers around the AAI class 3887class AAIRevOpr<bits<8> op27_20, bits<8> op11_4, string opc, 3888 list<dag> pattern = []> 3889 : AAI<op27_20, op11_4, opc, 3890 pattern, 3891 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3892 "\t$Rd, $Rm, $Rn">; 3893 3894class AAIIntrinsic<bits<8> op27_20, bits<8> op11_4, string opc, 3895 Intrinsic intrinsic> 3896 : AAI<op27_20, op11_4, opc, 3897 [(set GPRnopc:$Rd, (intrinsic GPRnopc:$Rn, GPRnopc:$Rm))]>; 3898 3899// Saturating add/subtract 3900let hasSideEffects = 1 in { 3901def QADD8 : AAIIntrinsic<0b01100010, 0b11111001, "qadd8", int_arm_qadd8>; 3902def QADD16 : AAIIntrinsic<0b01100010, 0b11110001, "qadd16", int_arm_qadd16>; 3903def QSUB16 : AAIIntrinsic<0b01100010, 0b11110111, "qsub16", int_arm_qsub16>; 3904def QSUB8 : AAIIntrinsic<0b01100010, 0b11111111, "qsub8", int_arm_qsub8>; 3905 3906def QDADD : AAIRevOpr<0b00010100, 0b00000101, "qdadd", 3907 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, 3908 (int_arm_qadd GPRnopc:$Rn, GPRnopc:$Rn)))]>; 3909def QDSUB : AAIRevOpr<0b00010110, 0b00000101, "qdsub", 3910 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, 3911 (int_arm_qadd GPRnopc:$Rn, GPRnopc:$Rn)))]>; 3912def QSUB : AAIRevOpr<0b00010010, 0b00000101, "qsub", 3913 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))]>; 3914let DecoderMethod = "DecodeQADDInstruction" in 3915 def QADD : AAIRevOpr<0b00010000, 0b00000101, "qadd", 3916 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))]>; 3917} 3918 3919def : ARMV5TEPat<(saddsat GPR:$a, GPR:$b), 3920 (QADD GPR:$a, GPR:$b)>; 3921def : ARMV5TEPat<(ssubsat GPR:$a, GPR:$b), 3922 (QSUB GPR:$a, GPR:$b)>; 3923def : ARMV5TEPat<(saddsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)), 3924 (QDADD rGPR:$Rm, rGPR:$Rn)>; 3925def : ARMV5TEPat<(ssubsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)), 3926 (QDSUB rGPR:$Rm, rGPR:$Rn)>; 3927def : ARMV6Pat<(ARMqadd8b rGPR:$Rm, rGPR:$Rn), 3928 (QADD8 rGPR:$Rm, rGPR:$Rn)>; 3929def : ARMV6Pat<(ARMqsub8b rGPR:$Rm, rGPR:$Rn), 3930 (QSUB8 rGPR:$Rm, rGPR:$Rn)>; 3931def : ARMV6Pat<(ARMqadd16b rGPR:$Rm, rGPR:$Rn), 3932 (QADD16 rGPR:$Rm, rGPR:$Rn)>; 3933def : ARMV6Pat<(ARMqsub16b rGPR:$Rm, rGPR:$Rn), 3934 (QSUB16 rGPR:$Rm, rGPR:$Rn)>; 3935 3936def UQADD16 : AAIIntrinsic<0b01100110, 0b11110001, "uqadd16", int_arm_uqadd16>; 3937def UQADD8 : AAIIntrinsic<0b01100110, 0b11111001, "uqadd8", int_arm_uqadd8>; 3938def UQSUB16 : AAIIntrinsic<0b01100110, 0b11110111, "uqsub16", int_arm_uqsub16>; 3939def UQSUB8 : AAIIntrinsic<0b01100110, 0b11111111, "uqsub8", int_arm_uqsub8>; 3940def QASX : AAIIntrinsic<0b01100010, 0b11110011, "qasx", int_arm_qasx>; 3941def QSAX : AAIIntrinsic<0b01100010, 0b11110101, "qsax", int_arm_qsax>; 3942def UQASX : AAIIntrinsic<0b01100110, 0b11110011, "uqasx", int_arm_uqasx>; 3943def UQSAX : AAIIntrinsic<0b01100110, 0b11110101, "uqsax", int_arm_uqsax>; 3944 3945// Signed/Unsigned add/subtract 3946 3947def SASX : AAIIntrinsic<0b01100001, 0b11110011, "sasx", int_arm_sasx>; 3948def SADD16 : AAIIntrinsic<0b01100001, 0b11110001, "sadd16", int_arm_sadd16>; 3949def SADD8 : AAIIntrinsic<0b01100001, 0b11111001, "sadd8", int_arm_sadd8>; 3950def SSAX : AAIIntrinsic<0b01100001, 0b11110101, "ssax", int_arm_ssax>; 3951def SSUB16 : AAIIntrinsic<0b01100001, 0b11110111, "ssub16", int_arm_ssub16>; 3952def SSUB8 : AAIIntrinsic<0b01100001, 0b11111111, "ssub8", int_arm_ssub8>; 3953def UASX : AAIIntrinsic<0b01100101, 0b11110011, "uasx", int_arm_uasx>; 3954def UADD16 : AAIIntrinsic<0b01100101, 0b11110001, "uadd16", int_arm_uadd16>; 3955def UADD8 : AAIIntrinsic<0b01100101, 0b11111001, "uadd8", int_arm_uadd8>; 3956def USAX : AAIIntrinsic<0b01100101, 0b11110101, "usax", int_arm_usax>; 3957def USUB16 : AAIIntrinsic<0b01100101, 0b11110111, "usub16", int_arm_usub16>; 3958def USUB8 : AAIIntrinsic<0b01100101, 0b11111111, "usub8", int_arm_usub8>; 3959 3960// Signed/Unsigned halving add/subtract 3961 3962def SHASX : AAIIntrinsic<0b01100011, 0b11110011, "shasx", int_arm_shasx>; 3963def SHADD16 : AAIIntrinsic<0b01100011, 0b11110001, "shadd16", int_arm_shadd16>; 3964def SHADD8 : AAIIntrinsic<0b01100011, 0b11111001, "shadd8", int_arm_shadd8>; 3965def SHSAX : AAIIntrinsic<0b01100011, 0b11110101, "shsax", int_arm_shsax>; 3966def SHSUB16 : AAIIntrinsic<0b01100011, 0b11110111, "shsub16", int_arm_shsub16>; 3967def SHSUB8 : AAIIntrinsic<0b01100011, 0b11111111, "shsub8", int_arm_shsub8>; 3968def UHASX : AAIIntrinsic<0b01100111, 0b11110011, "uhasx", int_arm_uhasx>; 3969def UHADD16 : AAIIntrinsic<0b01100111, 0b11110001, "uhadd16", int_arm_uhadd16>; 3970def UHADD8 : AAIIntrinsic<0b01100111, 0b11111001, "uhadd8", int_arm_uhadd8>; 3971def UHSAX : AAIIntrinsic<0b01100111, 0b11110101, "uhsax", int_arm_uhsax>; 3972def UHSUB16 : AAIIntrinsic<0b01100111, 0b11110111, "uhsub16", int_arm_uhsub16>; 3973def UHSUB8 : AAIIntrinsic<0b01100111, 0b11111111, "uhsub8", int_arm_uhsub8>; 3974 3975// Unsigned Sum of Absolute Differences [and Accumulate]. 3976 3977def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3978 MulFrm /* for convenience */, NoItinerary, "usad8", 3979 "\t$Rd, $Rn, $Rm", 3980 [(set GPR:$Rd, (int_arm_usad8 GPR:$Rn, GPR:$Rm))]>, 3981 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> { 3982 bits<4> Rd; 3983 bits<4> Rn; 3984 bits<4> Rm; 3985 let Inst{27-20} = 0b01111000; 3986 let Inst{15-12} = 0b1111; 3987 let Inst{7-4} = 0b0001; 3988 let Inst{19-16} = Rd; 3989 let Inst{11-8} = Rm; 3990 let Inst{3-0} = Rn; 3991} 3992def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3993 MulFrm /* for convenience */, NoItinerary, "usada8", 3994 "\t$Rd, $Rn, $Rm, $Ra", 3995 [(set GPR:$Rd, (int_arm_usada8 GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 3996 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{ 3997 bits<4> Rd; 3998 bits<4> Rn; 3999 bits<4> Rm; 4000 bits<4> Ra; 4001 let Inst{27-20} = 0b01111000; 4002 let Inst{7-4} = 0b0001; 4003 let Inst{19-16} = Rd; 4004 let Inst{15-12} = Ra; 4005 let Inst{11-8} = Rm; 4006 let Inst{3-0} = Rn; 4007} 4008 4009// Signed/Unsigned saturate 4010def SSAT : AI<(outs GPRnopc:$Rd), 4011 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 4012 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>, 4013 Requires<[IsARM,HasV6]>{ 4014 bits<4> Rd; 4015 bits<5> sat_imm; 4016 bits<4> Rn; 4017 bits<8> sh; 4018 let Inst{27-21} = 0b0110101; 4019 let Inst{5-4} = 0b01; 4020 let Inst{20-16} = sat_imm; 4021 let Inst{15-12} = Rd; 4022 let Inst{11-7} = sh{4-0}; 4023 let Inst{6} = sh{5}; 4024 let Inst{3-0} = Rn; 4025} 4026 4027def SSAT16 : AI<(outs GPRnopc:$Rd), 4028 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm, 4029 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []>, 4030 Requires<[IsARM,HasV6]>{ 4031 bits<4> Rd; 4032 bits<4> sat_imm; 4033 bits<4> Rn; 4034 let Inst{27-20} = 0b01101010; 4035 let Inst{11-4} = 0b11110011; 4036 let Inst{15-12} = Rd; 4037 let Inst{19-16} = sat_imm; 4038 let Inst{3-0} = Rn; 4039} 4040 4041def USAT : AI<(outs GPRnopc:$Rd), 4042 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 4043 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []>, 4044 Requires<[IsARM,HasV6]> { 4045 bits<4> Rd; 4046 bits<5> sat_imm; 4047 bits<4> Rn; 4048 bits<8> sh; 4049 let Inst{27-21} = 0b0110111; 4050 let Inst{5-4} = 0b01; 4051 let Inst{15-12} = Rd; 4052 let Inst{11-7} = sh{4-0}; 4053 let Inst{6} = sh{5}; 4054 let Inst{20-16} = sat_imm; 4055 let Inst{3-0} = Rn; 4056} 4057 4058def USAT16 : AI<(outs GPRnopc:$Rd), 4059 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm, 4060 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []>, 4061 Requires<[IsARM,HasV6]>{ 4062 bits<4> Rd; 4063 bits<4> sat_imm; 4064 bits<4> Rn; 4065 let Inst{27-20} = 0b01101110; 4066 let Inst{11-4} = 0b11110011; 4067 let Inst{15-12} = Rd; 4068 let Inst{19-16} = sat_imm; 4069 let Inst{3-0} = Rn; 4070} 4071 4072def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm1_32:$pos), 4073 (SSAT imm1_32:$pos, GPRnopc:$a, 0)>; 4074def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm0_31:$pos), 4075 (USAT imm0_31:$pos, GPRnopc:$a, 0)>; 4076def : ARMPat<(ARMssat GPRnopc:$Rn, imm0_31:$imm), 4077 (SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>; 4078def : ARMPat<(ARMusat GPRnopc:$Rn, imm0_31:$imm), 4079 (USAT imm0_31:$imm, GPRnopc:$Rn, 0)>; 4080def : ARMV6Pat<(int_arm_ssat16 GPRnopc:$a, imm1_16:$pos), 4081 (SSAT16 imm1_16:$pos, GPRnopc:$a)>; 4082def : ARMV6Pat<(int_arm_usat16 GPRnopc:$a, imm0_15:$pos), 4083 (USAT16 imm0_15:$pos, GPRnopc:$a)>; 4084def : ARMV6Pat<(int_arm_ssat (shl GPRnopc:$a, imm0_31:$shft), imm1_32:$pos), 4085 (SSAT imm1_32:$pos, GPRnopc:$a, imm0_31:$shft)>; 4086def : ARMV6Pat<(int_arm_ssat (sra GPRnopc:$a, asr_imm:$shft), imm1_32:$pos), 4087 (SSAT imm1_32:$pos, GPRnopc:$a, asr_imm:$shft)>; 4088def : ARMV6Pat<(int_arm_usat (shl GPRnopc:$a, imm0_31:$shft), imm0_31:$pos), 4089 (USAT imm0_31:$pos, GPRnopc:$a, imm0_31:$shft)>; 4090def : ARMV6Pat<(int_arm_usat (sra GPRnopc:$a, asr_imm:$shft), imm0_31:$pos), 4091 (USAT imm0_31:$pos, GPRnopc:$a, asr_imm:$shft)>; 4092def : ARMPat<(ARMssat (shl GPRnopc:$Rn, imm0_31:$shft), imm0_31:$pos), 4093 (SSAT imm0_31:$pos, GPRnopc:$Rn, imm0_31:$shft)>; 4094def : ARMPat<(ARMssat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos), 4095 (SSAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>; 4096def : ARMPat<(ARMusat (shl GPRnopc:$Rn, imm0_31:$shft), imm0_31:$pos), 4097 (USAT imm0_31:$pos, GPRnopc:$Rn, imm0_31:$shft)>; 4098def : ARMPat<(ARMusat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos), 4099 (USAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>; 4100 4101 4102//===----------------------------------------------------------------------===// 4103// Bitwise Instructions. 4104// 4105 4106defm AND : AsI1_bin_irs<0b0000, "and", 4107 IIC_iBITi, IIC_iBITr, IIC_iBITsr, and, 1>; 4108defm ORR : AsI1_bin_irs<0b1100, "orr", 4109 IIC_iBITi, IIC_iBITr, IIC_iBITsr, or, 1>; 4110defm EOR : AsI1_bin_irs<0b0001, "eor", 4111 IIC_iBITi, IIC_iBITr, IIC_iBITsr, xor, 1>; 4112defm BIC : AsI1_bin_irs<0b1110, "bic", 4113 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 4114 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 4115 4116// FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just 4117// like in the actual instruction encoding. The complexity of mapping the mask 4118// to the lsb/msb pair should be handled by ISel, not encapsulated in the 4119// instruction description. 4120def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm), 4121 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 4122 "bfc", "\t$Rd, $imm", "$src = $Rd", 4123 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>, 4124 Requires<[IsARM, HasV6T2]> { 4125 bits<4> Rd; 4126 bits<10> imm; 4127 let Inst{27-21} = 0b0111110; 4128 let Inst{6-0} = 0b0011111; 4129 let Inst{15-12} = Rd; 4130 let Inst{11-7} = imm{4-0}; // lsb 4131 let Inst{20-16} = imm{9-5}; // msb 4132} 4133 4134// A8.6.18 BFI - Bitfield insert (Encoding A1) 4135def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm), 4136 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 4137 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd", 4138 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn, 4139 bf_inv_mask_imm:$imm))]>, 4140 Requires<[IsARM, HasV6T2]> { 4141 bits<4> Rd; 4142 bits<4> Rn; 4143 bits<10> imm; 4144 let Inst{27-21} = 0b0111110; 4145 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15 4146 let Inst{15-12} = Rd; 4147 let Inst{11-7} = imm{4-0}; // lsb 4148 let Inst{20-16} = imm{9-5}; // width 4149 let Inst{3-0} = Rn; 4150} 4151 4152def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr, 4153 "mvn", "\t$Rd, $Rm", 4154 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> { 4155 bits<4> Rd; 4156 bits<4> Rm; 4157 let Inst{25} = 0; 4158 let Inst{19-16} = 0b0000; 4159 let Inst{11-4} = 0b00000000; 4160 let Inst{15-12} = Rd; 4161 let Inst{3-0} = Rm; 4162 4163 let Unpredictable{19-16} = 0b1111; 4164} 4165def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift), 4166 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 4167 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP, 4168 Sched<[WriteALU]> { 4169 bits<4> Rd; 4170 bits<12> shift; 4171 let Inst{25} = 0; 4172 let Inst{19-16} = 0b0000; 4173 let Inst{15-12} = Rd; 4174 let Inst{11-5} = shift{11-5}; 4175 let Inst{4} = 0; 4176 let Inst{3-0} = shift{3-0}; 4177 4178 let Unpredictable{19-16} = 0b1111; 4179} 4180def MVNsr : AsI1<0b1111, (outs GPRnopc:$Rd), (ins so_reg_reg:$shift), 4181 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 4182 [(set GPRnopc:$Rd, (not so_reg_reg:$shift))]>, UnaryDP, 4183 Sched<[WriteALU]> { 4184 bits<4> Rd; 4185 bits<12> shift; 4186 let Inst{25} = 0; 4187 let Inst{19-16} = 0b0000; 4188 let Inst{15-12} = Rd; 4189 let Inst{11-8} = shift{11-8}; 4190 let Inst{7} = 0; 4191 let Inst{6-5} = shift{6-5}; 4192 let Inst{4} = 1; 4193 let Inst{3-0} = shift{3-0}; 4194 4195 let Unpredictable{19-16} = 0b1111; 4196} 4197let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 4198def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, 4199 IIC_iMVNi, "mvn", "\t$Rd, $imm", 4200 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> { 4201 bits<4> Rd; 4202 bits<12> imm; 4203 let Inst{25} = 1; 4204 let Inst{19-16} = 0b0000; 4205 let Inst{15-12} = Rd; 4206 let Inst{11-0} = imm; 4207} 4208 4209let AddedComplexity = 1 in 4210def : ARMPat<(and GPR:$src, mod_imm_not:$imm), 4211 (BICri GPR:$src, mod_imm_not:$imm)>; 4212 4213//===----------------------------------------------------------------------===// 4214// Multiply Instructions. 4215// 4216class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 4217 string opc, string asm, list<dag> pattern> 4218 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 4219 bits<4> Rd; 4220 bits<4> Rm; 4221 bits<4> Rn; 4222 let Inst{19-16} = Rd; 4223 let Inst{11-8} = Rm; 4224 let Inst{3-0} = Rn; 4225} 4226class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 4227 string opc, string asm, list<dag> pattern> 4228 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 4229 bits<4> RdLo; 4230 bits<4> RdHi; 4231 bits<4> Rm; 4232 bits<4> Rn; 4233 let Inst{19-16} = RdHi; 4234 let Inst{15-12} = RdLo; 4235 let Inst{11-8} = Rm; 4236 let Inst{3-0} = Rn; 4237} 4238class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 4239 string opc, string asm, list<dag> pattern> 4240 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 4241 bits<4> RdLo; 4242 bits<4> RdHi; 4243 bits<4> Rm; 4244 bits<4> Rn; 4245 let Inst{19-16} = RdHi; 4246 let Inst{15-12} = RdLo; 4247 let Inst{11-8} = Rm; 4248 let Inst{3-0} = Rn; 4249} 4250 4251// FIXME: The v5 pseudos are only necessary for the additional Constraint 4252// property. Remove them when it's possible to add those properties 4253// on an individual MachineInstr, not just an instruction description. 4254let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in { 4255def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd), 4256 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4257 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", 4258 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>, 4259 Requires<[IsARM, HasV6]>, 4260 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4261 let Inst{15-12} = 0b0000; 4262 let Unpredictable{15-12} = 0b1111; 4263} 4264 4265let Constraints = "@earlyclobber $Rd" in 4266def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, 4267 pred:$p, cc_out:$s), 4268 4, IIC_iMUL32, 4269 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))], 4270 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>, 4271 Requires<[IsARM, NoV6, UseMulOps]>, 4272 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4273} 4274 4275def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd), 4276 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra), 4277 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra", 4278 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>, 4279 Requires<[IsARM, HasV6, UseMulOps]>, 4280 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { 4281 bits<4> Ra; 4282 let Inst{15-12} = Ra; 4283} 4284 4285let Constraints = "@earlyclobber $Rd" in 4286def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd), 4287 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 4288 pred:$p, cc_out:$s), 4, IIC_iMAC32, 4289 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))], 4290 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>, 4291 Requires<[IsARM, NoV6]>, 4292 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4293 4294def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4295 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra", 4296 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>, 4297 Requires<[IsARM, HasV6T2, UseMulOps]>, 4298 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { 4299 bits<4> Rd; 4300 bits<4> Rm; 4301 bits<4> Rn; 4302 bits<4> Ra; 4303 let Inst{19-16} = Rd; 4304 let Inst{15-12} = Ra; 4305 let Inst{11-8} = Rm; 4306 let Inst{3-0} = Rn; 4307} 4308 4309// Extra precision multiplies with low / high results 4310let hasSideEffects = 0 in { 4311let isCommutable = 1 in { 4312def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi), 4313 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 4314 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", 4315 [(set GPR:$RdLo, GPR:$RdHi, 4316 (smullohi GPR:$Rn, GPR:$Rm))]>, 4317 Requires<[IsARM, HasV6]>, 4318 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4319 4320def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi), 4321 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 4322 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", 4323 [(set GPR:$RdLo, GPR:$RdHi, 4324 (umullohi GPR:$Rn, GPR:$Rm))]>, 4325 Requires<[IsARM, HasV6]>, 4326 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL]>; 4327 4328let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in { 4329def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4330 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 4331 4, IIC_iMUL64, 4332 [(set GPR:$RdLo, GPR:$RdHi, 4333 (smullohi GPR:$Rn, GPR:$Rm))], 4334 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 4335 Requires<[IsARM, NoV6]>, 4336 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4337 4338def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4339 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 4340 4, IIC_iMUL64, 4341 [(set GPR:$RdLo, GPR:$RdHi, 4342 (umullohi GPR:$Rn, GPR:$Rm))], 4343 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 4344 Requires<[IsARM, NoV6]>, 4345 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4346} 4347} 4348 4349// Multiply + accumulate 4350def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi), 4351 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 4352 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4353 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4354 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4355def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi), 4356 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 4357 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4358 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4359 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4360 4361def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi), 4362 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4363 IIC_iMAC64, 4364 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4365 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4366 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]> { 4367 bits<4> RdLo; 4368 bits<4> RdHi; 4369 bits<4> Rm; 4370 bits<4> Rn; 4371 let Inst{19-16} = RdHi; 4372 let Inst{15-12} = RdLo; 4373 let Inst{11-8} = Rm; 4374 let Inst{3-0} = Rn; 4375} 4376 4377let Constraints = 4378 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in { 4379def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4380 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4381 4, IIC_iMAC64, [], 4382 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 4383 pred:$p, cc_out:$s)>, 4384 Requires<[IsARM, NoV6]>, 4385 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4386def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4387 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4388 4, IIC_iMAC64, [], 4389 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 4390 pred:$p, cc_out:$s)>, 4391 Requires<[IsARM, NoV6]>, 4392 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4393} 4394 4395} // hasSideEffects 4396 4397// Most significant word multiply 4398def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4399 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm", 4400 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>, 4401 Requires<[IsARM, HasV6]>, 4402 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4403 let Inst{15-12} = 0b1111; 4404} 4405 4406def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4407 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", 4408 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, (i32 0)))]>, 4409 Requires<[IsARM, HasV6]>, 4410 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4411 let Inst{15-12} = 0b1111; 4412} 4413 4414def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd), 4415 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4416 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra", 4417 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, 4418 Requires<[IsARM, HasV6, UseMulOps]>, 4419 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4420 4421def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd), 4422 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4423 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", 4424 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 4425 Requires<[IsARM, HasV6]>, 4426 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4427 4428def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd), 4429 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4430 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>, 4431 Requires<[IsARM, HasV6, UseMulOps]>, 4432 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4433 4434def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd), 4435 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4436 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", 4437 [(set GPR:$Rd, (ARMsmmlsr GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 4438 Requires<[IsARM, HasV6]>, 4439 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4440 4441multiclass AI_smul<string opc> { 4442 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4443 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm", 4444 [(set GPR:$Rd, (bb_mul GPR:$Rn, GPR:$Rm))]>, 4445 Requires<[IsARM, HasV5TE]>, 4446 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4447 4448 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4449 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm", 4450 [(set GPR:$Rd, (bt_mul GPR:$Rn, GPR:$Rm))]>, 4451 Requires<[IsARM, HasV5TE]>, 4452 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4453 4454 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4455 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm", 4456 [(set GPR:$Rd, (tb_mul GPR:$Rn, GPR:$Rm))]>, 4457 Requires<[IsARM, HasV5TE]>, 4458 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4459 4460 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4461 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm", 4462 [(set GPR:$Rd, (tt_mul GPR:$Rn, GPR:$Rm))]>, 4463 Requires<[IsARM, HasV5TE]>, 4464 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4465 4466 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4467 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", 4468 [(set GPR:$Rd, (ARMsmulwb GPR:$Rn, GPR:$Rm))]>, 4469 Requires<[IsARM, HasV5TE]>, 4470 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4471 4472 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4473 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm", 4474 [(set GPR:$Rd, (ARMsmulwt GPR:$Rn, GPR:$Rm))]>, 4475 Requires<[IsARM, HasV5TE]>, 4476 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4477} 4478 4479 4480multiclass AI_smla<string opc> { 4481 let DecoderMethod = "DecodeSMLAInstruction" in { 4482 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd), 4483 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4484 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", 4485 [(set GPRnopc:$Rd, (add GPR:$Ra, 4486 (bb_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4487 Requires<[IsARM, HasV5TE, UseMulOps]>, 4488 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4489 4490 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd), 4491 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4492 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", 4493 [(set GPRnopc:$Rd, (add GPR:$Ra, 4494 (bt_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4495 Requires<[IsARM, HasV5TE, UseMulOps]>, 4496 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4497 4498 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd), 4499 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4500 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", 4501 [(set GPRnopc:$Rd, (add GPR:$Ra, 4502 (tb_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4503 Requires<[IsARM, HasV5TE, UseMulOps]>, 4504 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4505 4506 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd), 4507 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4508 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", 4509 [(set GPRnopc:$Rd, (add GPR:$Ra, 4510 (tt_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4511 Requires<[IsARM, HasV5TE, UseMulOps]>, 4512 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4513 4514 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd), 4515 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4516 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", 4517 [(set GPRnopc:$Rd, 4518 (add GPR:$Ra, (ARMsmulwb GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4519 Requires<[IsARM, HasV5TE, UseMulOps]>, 4520 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4521 4522 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd), 4523 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4524 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", 4525 [(set GPRnopc:$Rd, 4526 (add GPR:$Ra, (ARMsmulwt GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4527 Requires<[IsARM, HasV5TE, UseMulOps]>, 4528 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4529 } 4530} 4531 4532defm SMUL : AI_smul<"smul">; 4533defm SMLA : AI_smla<"smla">; 4534 4535// Halfword multiply accumulate long: SMLAL<x><y>. 4536class SMLAL<bits<2> opc1, string asm> 4537 : AMulxyI64<0b0001010, opc1, 4538 (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4539 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4540 IIC_iMAC64, asm, "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4541 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4542 Requires<[IsARM, HasV5TE]>, 4543 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4544 4545def SMLALBB : SMLAL<0b00, "smlalbb">; 4546def SMLALBT : SMLAL<0b10, "smlalbt">; 4547def SMLALTB : SMLAL<0b01, "smlaltb">; 4548def SMLALTT : SMLAL<0b11, "smlaltt">; 4549 4550def : ARMV5TEPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4551 (SMLALBB $Rn, $Rm, $RLo, $RHi)>; 4552def : ARMV5TEPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4553 (SMLALBT $Rn, $Rm, $RLo, $RHi)>; 4554def : ARMV5TEPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4555 (SMLALTB $Rn, $Rm, $RLo, $RHi)>; 4556def : ARMV5TEPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4557 (SMLALTT $Rn, $Rm, $RLo, $RHi)>; 4558 4559// Helper class for AI_smld. 4560class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops, 4561 InstrItinClass itin, string opc, string asm> 4562 : AI<oops, iops, MulFrm, itin, opc, asm, []>, 4563 Requires<[IsARM, HasV6]> { 4564 bits<4> Rn; 4565 bits<4> Rm; 4566 let Inst{27-23} = 0b01110; 4567 let Inst{22} = long; 4568 let Inst{21-20} = 0b00; 4569 let Inst{11-8} = Rm; 4570 let Inst{7} = 0; 4571 let Inst{6} = sub; 4572 let Inst{5} = swap; 4573 let Inst{4} = 1; 4574 let Inst{3-0} = Rn; 4575} 4576class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops, 4577 InstrItinClass itin, string opc, string asm> 4578 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4579 bits<4> Rd; 4580 let Inst{15-12} = 0b1111; 4581 let Inst{19-16} = Rd; 4582} 4583class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops, 4584 InstrItinClass itin, string opc, string asm> 4585 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4586 bits<4> Ra; 4587 bits<4> Rd; 4588 let Inst{19-16} = Rd; 4589 let Inst{15-12} = Ra; 4590} 4591class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops, 4592 InstrItinClass itin, string opc, string asm> 4593 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4594 bits<4> RdLo; 4595 bits<4> RdHi; 4596 let Inst{19-16} = RdHi; 4597 let Inst{15-12} = RdLo; 4598} 4599 4600multiclass AI_smld<bit sub, string opc> { 4601 4602 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd), 4603 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4604 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">, 4605 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4606 4607 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd), 4608 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4609 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">, 4610 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4611 4612 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4613 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4614 NoItinerary, 4615 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">, 4616 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4617 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4618 4619 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4620 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4621 NoItinerary, 4622 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">, 4623 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4624 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4625} 4626 4627defm SMLA : AI_smld<0, "smla">; 4628defm SMLS : AI_smld<1, "smls">; 4629 4630def : ARMV6Pat<(int_arm_smlad GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4631 (SMLAD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4632def : ARMV6Pat<(int_arm_smladx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4633 (SMLADX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4634def : ARMV6Pat<(int_arm_smlsd GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4635 (SMLSD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4636def : ARMV6Pat<(int_arm_smlsdx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4637 (SMLSDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4638def : ARMV6Pat<(ARMSmlald GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4639 (SMLALD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4640def : ARMV6Pat<(ARMSmlaldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4641 (SMLALDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4642def : ARMV6Pat<(ARMSmlsld GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4643 (SMLSLD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4644def : ARMV6Pat<(ARMSmlsldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4645 (SMLSLDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4646 4647multiclass AI_sdml<bit sub, string opc> { 4648 4649 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), 4650 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">, 4651 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4652 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm), 4653 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">, 4654 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4655} 4656 4657defm SMUA : AI_sdml<0, "smua">; 4658defm SMUS : AI_sdml<1, "smus">; 4659 4660def : ARMV6Pat<(int_arm_smuad GPRnopc:$Rn, GPRnopc:$Rm), 4661 (SMUAD GPRnopc:$Rn, GPRnopc:$Rm)>; 4662def : ARMV6Pat<(int_arm_smuadx GPRnopc:$Rn, GPRnopc:$Rm), 4663 (SMUADX GPRnopc:$Rn, GPRnopc:$Rm)>; 4664def : ARMV6Pat<(int_arm_smusd GPRnopc:$Rn, GPRnopc:$Rm), 4665 (SMUSD GPRnopc:$Rn, GPRnopc:$Rm)>; 4666def : ARMV6Pat<(int_arm_smusdx GPRnopc:$Rn, GPRnopc:$Rm), 4667 (SMUSDX GPRnopc:$Rn, GPRnopc:$Rm)>; 4668 4669//===----------------------------------------------------------------------===// 4670// Division Instructions (ARMv7-A with virtualization extension) 4671// 4672def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4673 "sdiv", "\t$Rd, $Rn, $Rm", 4674 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>, 4675 Requires<[IsARM, HasDivideInARM]>, 4676 Sched<[WriteDIV]>; 4677 4678def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4679 "udiv", "\t$Rd, $Rn, $Rm", 4680 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>, 4681 Requires<[IsARM, HasDivideInARM]>, 4682 Sched<[WriteDIV]>; 4683 4684//===----------------------------------------------------------------------===// 4685// Misc. Arithmetic Instructions. 4686// 4687 4688def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm), 4689 IIC_iUNAr, "clz", "\t$Rd, $Rm", 4690 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>, 4691 Sched<[WriteALU]>; 4692 4693def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4694 IIC_iUNAr, "rbit", "\t$Rd, $Rm", 4695 [(set GPR:$Rd, (bitreverse GPR:$Rm))]>, 4696 Requires<[IsARM, HasV6T2]>, 4697 Sched<[WriteALU]>; 4698 4699def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4700 IIC_iUNAr, "rev", "\t$Rd, $Rm", 4701 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>, 4702 Sched<[WriteALU]>; 4703 4704let AddedComplexity = 5 in 4705def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4706 IIC_iUNAr, "rev16", "\t$Rd, $Rm", 4707 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>, 4708 Requires<[IsARM, HasV6]>, 4709 Sched<[WriteALU]>; 4710 4711def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)), 4712 (REV16 (LDRH addrmode3:$addr))>; 4713def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr), 4714 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>; 4715 4716let AddedComplexity = 5 in 4717def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4718 IIC_iUNAr, "revsh", "\t$Rd, $Rm", 4719 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>, 4720 Requires<[IsARM, HasV6]>, 4721 Sched<[WriteALU]>; 4722 4723def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)), 4724 (and (srl GPR:$Rm, (i32 8)), 0xFF)), 4725 (REVSH GPR:$Rm)>; 4726 4727def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd), 4728 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh), 4729 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", 4730 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF), 4731 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh), 4732 0xFFFF0000)))]>, 4733 Requires<[IsARM, HasV6]>, 4734 Sched<[WriteALUsi, ReadALU]>; 4735 4736// Alternate cases for PKHBT where identities eliminate some nodes. 4737def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)), 4738 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>; 4739def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)), 4740 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>; 4741 4742// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 4743// will match the pattern below. 4744def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd), 4745 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh), 4746 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", 4747 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000), 4748 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh), 4749 0xFFFF)))]>, 4750 Requires<[IsARM, HasV6]>, 4751 Sched<[WriteALUsi, ReadALU]>; 4752 4753// Alternate cases for PKHTB where identities eliminate some nodes. Note that 4754// a shift amount of 0 is *not legal* here, it is PKHBT instead. 4755// We also can not replace a srl (17..31) by an arithmetic shift we would use in 4756// pkhtb src1, src2, asr (17..31). 4757def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4758 (srl GPRnopc:$src2, imm16:$sh)), 4759 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>; 4760def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4761 (sra GPRnopc:$src2, imm16_31:$sh)), 4762 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>; 4763def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4764 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)), 4765 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>; 4766 4767//===----------------------------------------------------------------------===// 4768// CRC Instructions 4769// 4770// Polynomials: 4771// + CRC32{B,H,W} 0x04C11DB7 4772// + CRC32C{B,H,W} 0x1EDC6F41 4773// 4774 4775class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin> 4776 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary, 4777 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm", 4778 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>, 4779 Requires<[IsARM, HasV8, HasCRC]> { 4780 bits<4> Rd; 4781 bits<4> Rn; 4782 bits<4> Rm; 4783 4784 let Inst{31-28} = 0b1110; 4785 let Inst{27-23} = 0b00010; 4786 let Inst{22-21} = sz; 4787 let Inst{20} = 0; 4788 let Inst{19-16} = Rn; 4789 let Inst{15-12} = Rd; 4790 let Inst{11-10} = 0b00; 4791 let Inst{9} = C; 4792 let Inst{8} = 0; 4793 let Inst{7-4} = 0b0100; 4794 let Inst{3-0} = Rm; 4795 4796 let Unpredictable{11-8} = 0b1101; 4797} 4798 4799def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>; 4800def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>; 4801def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>; 4802def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>; 4803def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>; 4804def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>; 4805 4806//===----------------------------------------------------------------------===// 4807// ARMv8.1a Privilege Access Never extension 4808// 4809// SETPAN #imm1 4810 4811def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan", 4812 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> { 4813 bits<1> imm; 4814 4815 let Inst{31-28} = 0b1111; 4816 let Inst{27-20} = 0b00010001; 4817 let Inst{19-16} = 0b0000; 4818 let Inst{15-10} = 0b000000; 4819 let Inst{9} = imm; 4820 let Inst{8} = 0b0; 4821 let Inst{7-4} = 0b0000; 4822 let Inst{3-0} = 0b0000; 4823 4824 let Unpredictable{19-16} = 0b1111; 4825 let Unpredictable{15-10} = 0b111111; 4826 let Unpredictable{8} = 0b1; 4827 let Unpredictable{3-0} = 0b1111; 4828} 4829 4830//===----------------------------------------------------------------------===// 4831// Comparison Instructions... 4832// 4833 4834defm CMP : AI1_cmp_irs<0b1010, "cmp", 4835 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, ARMcmp>; 4836 4837// ARMcmpZ can re-use the above instruction definitions. 4838def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm), 4839 (CMPri GPR:$src, mod_imm:$imm)>; 4840def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs), 4841 (CMPrr GPR:$src, GPR:$rhs)>; 4842def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs), 4843 (CMPrsi GPR:$src, so_reg_imm:$rhs)>; 4844def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs), 4845 (CMPrsr GPR:$src, so_reg_reg:$rhs)>; 4846 4847// CMN register-integer 4848let isCompare = 1, Defs = [CPSR] in { 4849def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi, 4850 "cmn", "\t$Rn, $imm", 4851 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>, 4852 Sched<[WriteCMP, ReadALU]> { 4853 bits<4> Rn; 4854 bits<12> imm; 4855 let Inst{25} = 1; 4856 let Inst{20} = 1; 4857 let Inst{19-16} = Rn; 4858 let Inst{15-12} = 0b0000; 4859 let Inst{11-0} = imm; 4860 4861 let Unpredictable{15-12} = 0b1111; 4862} 4863 4864// CMN register-register/shift 4865def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr, 4866 "cmn", "\t$Rn, $Rm", 4867 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4868 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> { 4869 bits<4> Rn; 4870 bits<4> Rm; 4871 let isCommutable = 1; 4872 let Inst{25} = 0; 4873 let Inst{20} = 1; 4874 let Inst{19-16} = Rn; 4875 let Inst{15-12} = 0b0000; 4876 let Inst{11-4} = 0b00000000; 4877 let Inst{3-0} = Rm; 4878 4879 let Unpredictable{15-12} = 0b1111; 4880} 4881 4882def CMNzrsi : AI1<0b1011, (outs), 4883 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr, 4884 "cmn", "\t$Rn, $shift", 4885 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4886 GPR:$Rn, so_reg_imm:$shift)]>, 4887 Sched<[WriteCMPsi, ReadALU]> { 4888 bits<4> Rn; 4889 bits<12> shift; 4890 let Inst{25} = 0; 4891 let Inst{20} = 1; 4892 let Inst{19-16} = Rn; 4893 let Inst{15-12} = 0b0000; 4894 let Inst{11-5} = shift{11-5}; 4895 let Inst{4} = 0; 4896 let Inst{3-0} = shift{3-0}; 4897 4898 let Unpredictable{15-12} = 0b1111; 4899} 4900 4901def CMNzrsr : AI1<0b1011, (outs), 4902 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr, 4903 "cmn", "\t$Rn, $shift", 4904 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4905 GPRnopc:$Rn, so_reg_reg:$shift)]>, 4906 Sched<[WriteCMPsr, ReadALU]> { 4907 bits<4> Rn; 4908 bits<12> shift; 4909 let Inst{25} = 0; 4910 let Inst{20} = 1; 4911 let Inst{19-16} = Rn; 4912 let Inst{15-12} = 0b0000; 4913 let Inst{11-8} = shift{11-8}; 4914 let Inst{7} = 0; 4915 let Inst{6-5} = shift{6-5}; 4916 let Inst{4} = 1; 4917 let Inst{3-0} = shift{3-0}; 4918 4919 let Unpredictable{15-12} = 0b1111; 4920} 4921 4922} 4923 4924def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm), 4925 (CMNri GPR:$src, mod_imm_neg:$imm)>; 4926 4927def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm), 4928 (CMNri GPR:$src, mod_imm_neg:$imm)>; 4929 4930// Note that TST/TEQ don't set all the same flags that CMP does! 4931defm TST : AI1_cmp_irs<0b1000, "tst", 4932 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4933 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1, 4934 "DecodeTSTInstruction">; 4935defm TEQ : AI1_cmp_irs<0b1001, "teq", 4936 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4937 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>; 4938 4939// Pseudo i64 compares for some floating point compares. 4940let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, 4941 Defs = [CPSR] in { 4942def BCCi64 : PseudoInst<(outs), 4943 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst), 4944 IIC_Br, 4945 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>, 4946 Sched<[WriteBr]>; 4947 4948def BCCZi64 : PseudoInst<(outs), 4949 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, 4950 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>, 4951 Sched<[WriteBr]>; 4952} // usesCustomInserter 4953 4954 4955// Conditional moves 4956let hasSideEffects = 0 in { 4957 4958let isCommutable = 1, isSelect = 1 in 4959def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), 4960 (ins GPR:$false, GPR:$Rm, cmovpred:$p), 4961 4, IIC_iCMOVr, 4962 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, 4963 cmovpred:$p))]>, 4964 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4965 4966def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd), 4967 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p), 4968 4, IIC_iCMOVsr, 4969 [(set GPR:$Rd, 4970 (ARMcmov GPR:$false, so_reg_imm:$shift, 4971 cmovpred:$p))]>, 4972 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4973def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd), 4974 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p), 4975 4, IIC_iCMOVsr, 4976 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift, 4977 cmovpred:$p))]>, 4978 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4979 4980 4981let isMoveImm = 1 in 4982def MOVCCi16 4983 : ARMPseudoInst<(outs GPR:$Rd), 4984 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p), 4985 4, IIC_iMOVi, 4986 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm, 4987 cmovpred:$p))]>, 4988 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>, 4989 Sched<[WriteALU]>; 4990 4991let isMoveImm = 1 in 4992def MOVCCi : ARMPseudoInst<(outs GPR:$Rd), 4993 (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 4994 4, IIC_iCMOVi, 4995 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm, 4996 cmovpred:$p))]>, 4997 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4998 4999// Two instruction predicate mov immediate. 5000let isMoveImm = 1 in 5001def MOVCCi32imm 5002 : ARMPseudoInst<(outs GPR:$Rd), 5003 (ins GPR:$false, i32imm:$src, cmovpred:$p), 5004 8, IIC_iCMOVix2, 5005 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src, 5006 cmovpred:$p))]>, 5007 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>; 5008 5009let isMoveImm = 1 in 5010def MVNCCi : ARMPseudoInst<(outs GPR:$Rd), 5011 (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 5012 4, IIC_iCMOVi, 5013 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm, 5014 cmovpred:$p))]>, 5015 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 5016 5017} // hasSideEffects 5018 5019 5020//===----------------------------------------------------------------------===// 5021// Atomic operations intrinsics 5022// 5023 5024def MemBarrierOptOperand : AsmOperandClass { 5025 let Name = "MemBarrierOpt"; 5026 let ParserMethod = "parseMemBarrierOptOperand"; 5027} 5028def memb_opt : Operand<i32> { 5029 let PrintMethod = "printMemBOption"; 5030 let ParserMatchClass = MemBarrierOptOperand; 5031 let DecoderMethod = "DecodeMemBarrierOption"; 5032} 5033 5034def InstSyncBarrierOptOperand : AsmOperandClass { 5035 let Name = "InstSyncBarrierOpt"; 5036 let ParserMethod = "parseInstSyncBarrierOptOperand"; 5037} 5038def instsyncb_opt : Operand<i32> { 5039 let PrintMethod = "printInstSyncBOption"; 5040 let ParserMatchClass = InstSyncBarrierOptOperand; 5041 let DecoderMethod = "DecodeInstSyncBarrierOption"; 5042} 5043 5044def TraceSyncBarrierOptOperand : AsmOperandClass { 5045 let Name = "TraceSyncBarrierOpt"; 5046 let ParserMethod = "parseTraceSyncBarrierOptOperand"; 5047} 5048def tsb_opt : Operand<i32> { 5049 let PrintMethod = "printTraceSyncBOption"; 5050 let ParserMatchClass = TraceSyncBarrierOptOperand; 5051} 5052 5053// Memory barriers protect the atomic sequences 5054let hasSideEffects = 1 in { 5055def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 5056 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>, 5057 Requires<[IsARM, HasDB]> { 5058 bits<4> opt; 5059 let Inst{31-4} = 0xf57ff05; 5060 let Inst{3-0} = opt; 5061} 5062 5063def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 5064 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>, 5065 Requires<[IsARM, HasDB]> { 5066 bits<4> opt; 5067 let Inst{31-4} = 0xf57ff04; 5068 let Inst{3-0} = opt; 5069} 5070 5071// ISB has only full system option 5072def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary, 5073 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>, 5074 Requires<[IsARM, HasDB]> { 5075 bits<4> opt; 5076 let Inst{31-4} = 0xf57ff06; 5077 let Inst{3-0} = opt; 5078} 5079 5080let hasNoSchedulingInfo = 1 in 5081def TSB : AInoP<(outs), (ins tsb_opt:$opt), MiscFrm, NoItinerary, 5082 "tsb", "\t$opt", []>, Requires<[IsARM, HasV8_4a]> { 5083 let Inst{31-0} = 0xe320f012; 5084} 5085 5086} 5087 5088// Armv8.5-A speculation barrier 5089def SB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "sb", "", []>, 5090 Requires<[IsARM, HasSB]>, Sched<[]> { 5091 let Inst{31-0} = 0xf57ff070; 5092 let Unpredictable = 0x000fff0f; 5093 let hasSideEffects = 1; 5094} 5095 5096let usesCustomInserter = 1, Defs = [CPSR], hasNoSchedulingInfo = 1 in { 5097 // Pseudo instruction that combines movs + predicated rsbmi 5098 // to implement integer ABS 5099 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>; 5100} 5101 5102let usesCustomInserter = 1, Defs = [CPSR], hasNoSchedulingInfo = 1 in { 5103 def COPY_STRUCT_BYVAL_I32 : PseudoInst< 5104 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment), 5105 NoItinerary, 5106 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>; 5107} 5108 5109let hasPostISelHook = 1, Constraints = "$newdst = $dst, $newsrc = $src" in { 5110 // %newsrc, %newdst = MEMCPY %dst, %src, N, ...N scratch regs... 5111 // Copies N registers worth of memory from address %src to address %dst 5112 // and returns the incremented addresses. N scratch register will 5113 // be attached for the copy to use. 5114 def MEMCPY : PseudoInst< 5115 (outs GPR:$newdst, GPR:$newsrc), 5116 (ins GPR:$dst, GPR:$src, i32imm:$nreg, variable_ops), 5117 NoItinerary, 5118 [(set GPR:$newdst, GPR:$newsrc, 5119 (ARMmemcopy GPR:$dst, GPR:$src, imm:$nreg))]>; 5120} 5121 5122def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 5123 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 5124}]>; 5125 5126def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 5127 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 5128}]>; 5129 5130def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 5131 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 5132}]>; 5133 5134def strex_1 : PatFrag<(ops node:$val, node:$ptr), 5135 (int_arm_strex node:$val, node:$ptr), [{ 5136 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 5137}]>; 5138 5139def strex_2 : PatFrag<(ops node:$val, node:$ptr), 5140 (int_arm_strex node:$val, node:$ptr), [{ 5141 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 5142}]>; 5143 5144def strex_4 : PatFrag<(ops node:$val, node:$ptr), 5145 (int_arm_strex node:$val, node:$ptr), [{ 5146 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 5147}]>; 5148 5149def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 5150 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 5151}]>; 5152 5153def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 5154 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 5155}]>; 5156 5157def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 5158 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 5159}]>; 5160 5161def stlex_1 : PatFrag<(ops node:$val, node:$ptr), 5162 (int_arm_stlex node:$val, node:$ptr), [{ 5163 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 5164}]>; 5165 5166def stlex_2 : PatFrag<(ops node:$val, node:$ptr), 5167 (int_arm_stlex node:$val, node:$ptr), [{ 5168 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 5169}]>; 5170 5171def stlex_4 : PatFrag<(ops node:$val, node:$ptr), 5172 (int_arm_stlex node:$val, node:$ptr), [{ 5173 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 5174}]>; 5175 5176let mayLoad = 1 in { 5177def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5178 NoItinerary, "ldrexb", "\t$Rt, $addr", 5179 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>; 5180def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5181 NoItinerary, "ldrexh", "\t$Rt, $addr", 5182 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>; 5183def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5184 NoItinerary, "ldrex", "\t$Rt, $addr", 5185 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>; 5186let hasExtraDefRegAllocReq = 1 in 5187def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 5188 NoItinerary, "ldrexd", "\t$Rt, $addr", []> { 5189 let DecoderMethod = "DecodeDoubleRegLoad"; 5190} 5191 5192def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5193 NoItinerary, "ldaexb", "\t$Rt, $addr", 5194 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>; 5195def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5196 NoItinerary, "ldaexh", "\t$Rt, $addr", 5197 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>; 5198def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5199 NoItinerary, "ldaex", "\t$Rt, $addr", 5200 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>; 5201let hasExtraDefRegAllocReq = 1 in 5202def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 5203 NoItinerary, "ldaexd", "\t$Rt, $addr", []> { 5204 let DecoderMethod = "DecodeDoubleRegLoad"; 5205} 5206} 5207 5208let mayStore = 1, Constraints = "@earlyclobber $Rd" in { 5209def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5210 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", 5211 [(set GPR:$Rd, (strex_1 GPR:$Rt, 5212 addr_offset_none:$addr))]>; 5213def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5214 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", 5215 [(set GPR:$Rd, (strex_2 GPR:$Rt, 5216 addr_offset_none:$addr))]>; 5217def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5218 NoItinerary, "strex", "\t$Rd, $Rt, $addr", 5219 [(set GPR:$Rd, (strex_4 GPR:$Rt, 5220 addr_offset_none:$addr))]>; 5221let hasExtraSrcRegAllocReq = 1 in 5222def STREXD : AIstrex<0b01, (outs GPR:$Rd), 5223 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 5224 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> { 5225 let DecoderMethod = "DecodeDoubleRegStore"; 5226} 5227def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5228 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr", 5229 [(set GPR:$Rd, 5230 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>; 5231def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5232 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr", 5233 [(set GPR:$Rd, 5234 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>; 5235def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5236 NoItinerary, "stlex", "\t$Rd, $Rt, $addr", 5237 [(set GPR:$Rd, 5238 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>; 5239let hasExtraSrcRegAllocReq = 1 in 5240def STLEXD : AIstlex<0b01, (outs GPR:$Rd), 5241 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 5242 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> { 5243 let DecoderMethod = "DecodeDoubleRegStore"; 5244} 5245} 5246 5247def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", 5248 [(int_arm_clrex)]>, 5249 Requires<[IsARM, HasV6K]> { 5250 let Inst{31-0} = 0b11110101011111111111000000011111; 5251} 5252 5253def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 5254 (STREXB GPR:$Rt, addr_offset_none:$addr)>; 5255def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 5256 (STREXH GPR:$Rt, addr_offset_none:$addr)>; 5257 5258def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 5259 (STLEXB GPR:$Rt, addr_offset_none:$addr)>; 5260def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 5261 (STLEXH GPR:$Rt, addr_offset_none:$addr)>; 5262 5263class acquiring_load<PatFrag base> 5264 : PatFrag<(ops node:$ptr), (base node:$ptr), [{ 5265 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 5266 return isAcquireOrStronger(Ordering); 5267}]>; 5268 5269def atomic_load_acquire_8 : acquiring_load<atomic_load_8>; 5270def atomic_load_acquire_16 : acquiring_load<atomic_load_16>; 5271def atomic_load_acquire_32 : acquiring_load<atomic_load_32>; 5272 5273class releasing_store<PatFrag base> 5274 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ 5275 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 5276 return isReleaseOrStronger(Ordering); 5277}]>; 5278 5279def atomic_store_release_8 : releasing_store<atomic_store_8>; 5280def atomic_store_release_16 : releasing_store<atomic_store_16>; 5281def atomic_store_release_32 : releasing_store<atomic_store_32>; 5282 5283let AddedComplexity = 8 in { 5284 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>; 5285 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>; 5286 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>; 5287 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>; 5288 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>; 5289 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>; 5290} 5291 5292// SWP/SWPB are deprecated in V6/V7 and optional in v7VE. 5293// FIXME Use InstAlias to generate LDREX/STREX pairs instead. 5294let mayLoad = 1, mayStore = 1 in { 5295def SWP : AIswp<0, (outs GPRnopc:$Rt), 5296 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>, 5297 Requires<[IsARM,PreV8]>; 5298def SWPB: AIswp<1, (outs GPRnopc:$Rt), 5299 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>, 5300 Requires<[IsARM,PreV8]>; 5301} 5302 5303//===----------------------------------------------------------------------===// 5304// Coprocessor Instructions. 5305// 5306 5307def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5308 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 5309 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5310 [(int_arm_cdp timm:$cop, timm:$opc1, timm:$CRd, timm:$CRn, 5311 timm:$CRm, timm:$opc2)]>, 5312 Requires<[IsARM,PreV8]> { 5313 bits<4> opc1; 5314 bits<4> CRn; 5315 bits<4> CRd; 5316 bits<4> cop; 5317 bits<3> opc2; 5318 bits<4> CRm; 5319 5320 let Inst{3-0} = CRm; 5321 let Inst{4} = 0; 5322 let Inst{7-5} = opc2; 5323 let Inst{11-8} = cop; 5324 let Inst{15-12} = CRd; 5325 let Inst{19-16} = CRn; 5326 let Inst{23-20} = opc1; 5327 5328 let DecoderNamespace = "CoProc"; 5329} 5330 5331def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5332 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 5333 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5334 [(int_arm_cdp2 timm:$cop, timm:$opc1, timm:$CRd, timm:$CRn, 5335 timm:$CRm, timm:$opc2)]>, 5336 Requires<[IsARM,PreV8]> { 5337 let Inst{31-28} = 0b1111; 5338 bits<4> opc1; 5339 bits<4> CRn; 5340 bits<4> CRd; 5341 bits<4> cop; 5342 bits<3> opc2; 5343 bits<4> CRm; 5344 5345 let Inst{3-0} = CRm; 5346 let Inst{4} = 0; 5347 let Inst{7-5} = opc2; 5348 let Inst{11-8} = cop; 5349 let Inst{15-12} = CRd; 5350 let Inst{19-16} = CRn; 5351 let Inst{23-20} = opc1; 5352 5353 let DecoderNamespace = "CoProc"; 5354} 5355 5356class ACI<dag oops, dag iops, string opc, string asm, 5357 list<dag> pattern, IndexMode im = IndexModeNone> 5358 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 5359 opc, asm, "", pattern> { 5360 let Inst{27-25} = 0b110; 5361} 5362class ACInoP<dag oops, dag iops, string opc, string asm, 5363 list<dag> pattern, IndexMode im = IndexModeNone> 5364 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 5365 opc, asm, "", pattern> { 5366 let Inst{31-28} = 0b1111; 5367 let Inst{27-25} = 0b110; 5368} 5369 5370let DecoderNamespace = "CoProc" in { 5371multiclass LdStCop<bit load, bit Dbit, string asm, list<dag> pattern> { 5372 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 5373 asm, "\t$cop, $CRd, $addr", pattern> { 5374 bits<13> addr; 5375 bits<4> cop; 5376 bits<4> CRd; 5377 let Inst{24} = 1; // P = 1 5378 let Inst{23} = addr{8}; 5379 let Inst{22} = Dbit; 5380 let Inst{21} = 0; // W = 0 5381 let Inst{20} = load; 5382 let Inst{19-16} = addr{12-9}; 5383 let Inst{15-12} = CRd; 5384 let Inst{11-8} = cop; 5385 let Inst{7-0} = addr{7-0}; 5386 let DecoderMethod = "DecodeCopMemInstruction"; 5387 } 5388 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 5389 asm, "\t$cop, $CRd, $addr!", [], IndexModePre> { 5390 bits<13> addr; 5391 bits<4> cop; 5392 bits<4> CRd; 5393 let Inst{24} = 1; // P = 1 5394 let Inst{23} = addr{8}; 5395 let Inst{22} = Dbit; 5396 let Inst{21} = 1; // W = 1 5397 let Inst{20} = load; 5398 let Inst{19-16} = addr{12-9}; 5399 let Inst{15-12} = CRd; 5400 let Inst{11-8} = cop; 5401 let Inst{7-0} = addr{7-0}; 5402 let DecoderMethod = "DecodeCopMemInstruction"; 5403 } 5404 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5405 postidx_imm8s4:$offset), 5406 asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> { 5407 bits<9> offset; 5408 bits<4> addr; 5409 bits<4> cop; 5410 bits<4> CRd; 5411 let Inst{24} = 0; // P = 0 5412 let Inst{23} = offset{8}; 5413 let Inst{22} = Dbit; 5414 let Inst{21} = 1; // W = 1 5415 let Inst{20} = load; 5416 let Inst{19-16} = addr; 5417 let Inst{15-12} = CRd; 5418 let Inst{11-8} = cop; 5419 let Inst{7-0} = offset{7-0}; 5420 let DecoderMethod = "DecodeCopMemInstruction"; 5421 } 5422 def _OPTION : ACI<(outs), 5423 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5424 coproc_option_imm:$option), 5425 asm, "\t$cop, $CRd, $addr, $option", []> { 5426 bits<8> option; 5427 bits<4> addr; 5428 bits<4> cop; 5429 bits<4> CRd; 5430 let Inst{24} = 0; // P = 0 5431 let Inst{23} = 1; // U = 1 5432 let Inst{22} = Dbit; 5433 let Inst{21} = 0; // W = 0 5434 let Inst{20} = load; 5435 let Inst{19-16} = addr; 5436 let Inst{15-12} = CRd; 5437 let Inst{11-8} = cop; 5438 let Inst{7-0} = option; 5439 let DecoderMethod = "DecodeCopMemInstruction"; 5440 } 5441} 5442multiclass LdSt2Cop<bit load, bit Dbit, string asm, list<dag> pattern> { 5443 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 5444 asm, "\t$cop, $CRd, $addr", pattern> { 5445 bits<13> addr; 5446 bits<4> cop; 5447 bits<4> CRd; 5448 let Inst{24} = 1; // P = 1 5449 let Inst{23} = addr{8}; 5450 let Inst{22} = Dbit; 5451 let Inst{21} = 0; // W = 0 5452 let Inst{20} = load; 5453 let Inst{19-16} = addr{12-9}; 5454 let Inst{15-12} = CRd; 5455 let Inst{11-8} = cop; 5456 let Inst{7-0} = addr{7-0}; 5457 let DecoderMethod = "DecodeCopMemInstruction"; 5458 } 5459 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 5460 asm, "\t$cop, $CRd, $addr!", [], IndexModePre> { 5461 bits<13> addr; 5462 bits<4> cop; 5463 bits<4> CRd; 5464 let Inst{24} = 1; // P = 1 5465 let Inst{23} = addr{8}; 5466 let Inst{22} = Dbit; 5467 let Inst{21} = 1; // W = 1 5468 let Inst{20} = load; 5469 let Inst{19-16} = addr{12-9}; 5470 let Inst{15-12} = CRd; 5471 let Inst{11-8} = cop; 5472 let Inst{7-0} = addr{7-0}; 5473 let DecoderMethod = "DecodeCopMemInstruction"; 5474 } 5475 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5476 postidx_imm8s4:$offset), 5477 asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> { 5478 bits<9> offset; 5479 bits<4> addr; 5480 bits<4> cop; 5481 bits<4> CRd; 5482 let Inst{24} = 0; // P = 0 5483 let Inst{23} = offset{8}; 5484 let Inst{22} = Dbit; 5485 let Inst{21} = 1; // W = 1 5486 let Inst{20} = load; 5487 let Inst{19-16} = addr; 5488 let Inst{15-12} = CRd; 5489 let Inst{11-8} = cop; 5490 let Inst{7-0} = offset{7-0}; 5491 let DecoderMethod = "DecodeCopMemInstruction"; 5492 } 5493 def _OPTION : ACInoP<(outs), 5494 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5495 coproc_option_imm:$option), 5496 asm, "\t$cop, $CRd, $addr, $option", []> { 5497 bits<8> option; 5498 bits<4> addr; 5499 bits<4> cop; 5500 bits<4> CRd; 5501 let Inst{24} = 0; // P = 0 5502 let Inst{23} = 1; // U = 1 5503 let Inst{22} = Dbit; 5504 let Inst{21} = 0; // W = 0 5505 let Inst{20} = load; 5506 let Inst{19-16} = addr; 5507 let Inst{15-12} = CRd; 5508 let Inst{11-8} = cop; 5509 let Inst{7-0} = option; 5510 let DecoderMethod = "DecodeCopMemInstruction"; 5511 } 5512} 5513 5514defm LDC : LdStCop <1, 0, "ldc", [(int_arm_ldc timm:$cop, timm:$CRd, addrmode5:$addr)]>; 5515defm LDCL : LdStCop <1, 1, "ldcl", [(int_arm_ldcl timm:$cop, timm:$CRd, addrmode5:$addr)]>; 5516defm LDC2 : LdSt2Cop<1, 0, "ldc2", [(int_arm_ldc2 timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5517defm LDC2L : LdSt2Cop<1, 1, "ldc2l", [(int_arm_ldc2l timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5518 5519defm STC : LdStCop <0, 0, "stc", [(int_arm_stc timm:$cop, timm:$CRd, addrmode5:$addr)]>; 5520defm STCL : LdStCop <0, 1, "stcl", [(int_arm_stcl timm:$cop, timm:$CRd, addrmode5:$addr)]>; 5521defm STC2 : LdSt2Cop<0, 0, "stc2", [(int_arm_stc2 timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5522defm STC2L : LdSt2Cop<0, 1, "stc2l", [(int_arm_stc2l timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5523 5524} // DecoderNamespace = "CoProc" 5525 5526//===----------------------------------------------------------------------===// 5527// Move between coprocessor and ARM core register. 5528// 5529 5530class MovRCopro<string opc, bit direction, dag oops, dag iops, 5531 list<dag> pattern> 5532 : ABI<0b1110, oops, iops, NoItinerary, opc, 5533 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> { 5534 let Inst{20} = direction; 5535 let Inst{4} = 1; 5536 5537 bits<4> Rt; 5538 bits<4> cop; 5539 bits<3> opc1; 5540 bits<3> opc2; 5541 bits<4> CRm; 5542 bits<4> CRn; 5543 5544 let Inst{15-12} = Rt; 5545 let Inst{11-8} = cop; 5546 let Inst{23-21} = opc1; 5547 let Inst{7-5} = opc2; 5548 let Inst{3-0} = CRm; 5549 let Inst{19-16} = CRn; 5550 5551 let DecoderNamespace = "CoProc"; 5552} 5553 5554def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */, 5555 (outs), 5556 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5557 c_imm:$CRm, imm0_7:$opc2), 5558 [(int_arm_mcr timm:$cop, timm:$opc1, GPR:$Rt, timm:$CRn, 5559 timm:$CRm, timm:$opc2)]>, 5560 ComplexDeprecationPredicate<"MCR">; 5561def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 5562 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5563 c_imm:$CRm, 0, pred:$p)>; 5564def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */, 5565 (outs GPRwithAPSR:$Rt), 5566 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 5567 imm0_7:$opc2), []>, 5568 ComplexDeprecationPredicate<"MRC">; 5569def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm", 5570 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 5571 c_imm:$CRm, 0, pred:$p)>; 5572 5573def : ARMPat<(int_arm_mrc timm:$cop, timm:$opc1, timm:$CRn, timm:$CRm, timm:$opc2), 5574 (MRC p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2)>; 5575 5576class MovRCopro2<string opc, bit direction, dag oops, dag iops, 5577 list<dag> pattern> 5578 : ABXI<0b1110, oops, iops, NoItinerary, 5579 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> { 5580 let Inst{31-24} = 0b11111110; 5581 let Inst{20} = direction; 5582 let Inst{4} = 1; 5583 5584 bits<4> Rt; 5585 bits<4> cop; 5586 bits<3> opc1; 5587 bits<3> opc2; 5588 bits<4> CRm; 5589 bits<4> CRn; 5590 5591 let Inst{15-12} = Rt; 5592 let Inst{11-8} = cop; 5593 let Inst{23-21} = opc1; 5594 let Inst{7-5} = opc2; 5595 let Inst{3-0} = CRm; 5596 let Inst{19-16} = CRn; 5597 5598 let DecoderNamespace = "CoProc"; 5599} 5600 5601def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */, 5602 (outs), 5603 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5604 c_imm:$CRm, imm0_7:$opc2), 5605 [(int_arm_mcr2 timm:$cop, timm:$opc1, GPR:$Rt, timm:$CRn, 5606 timm:$CRm, timm:$opc2)]>, 5607 Requires<[IsARM,PreV8]>; 5608def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm", 5609 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5610 c_imm:$CRm, 0)>; 5611def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */, 5612 (outs GPRwithAPSR:$Rt), 5613 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 5614 imm0_7:$opc2), []>, 5615 Requires<[IsARM,PreV8]>; 5616def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm", 5617 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 5618 c_imm:$CRm, 0)>; 5619 5620def : ARMV5TPat<(int_arm_mrc2 timm:$cop, timm:$opc1, timm:$CRn, 5621 timm:$CRm, timm:$opc2), 5622 (MRC2 p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2)>; 5623 5624class MovRRCopro<string opc, bit direction, dag oops, dag iops, list<dag> 5625 pattern = []> 5626 : ABI<0b1100, oops, iops, NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", 5627 pattern> { 5628 5629 let Inst{23-21} = 0b010; 5630 let Inst{20} = direction; 5631 5632 bits<4> Rt; 5633 bits<4> Rt2; 5634 bits<4> cop; 5635 bits<4> opc1; 5636 bits<4> CRm; 5637 5638 let Inst{15-12} = Rt; 5639 let Inst{19-16} = Rt2; 5640 let Inst{11-8} = cop; 5641 let Inst{7-4} = opc1; 5642 let Inst{3-0} = CRm; 5643} 5644 5645def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */, 5646 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, 5647 GPRnopc:$Rt2, c_imm:$CRm), 5648 [(int_arm_mcrr timm:$cop, timm:$opc1, GPRnopc:$Rt, 5649 GPRnopc:$Rt2, timm:$CRm)]>; 5650def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */, 5651 (outs GPRnopc:$Rt, GPRnopc:$Rt2), 5652 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; 5653 5654class MovRRCopro2<string opc, bit direction, dag oops, dag iops, 5655 list<dag> pattern = []> 5656 : ABXI<0b1100, oops, iops, NoItinerary, 5657 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>, 5658 Requires<[IsARM,PreV8]> { 5659 let Inst{31-28} = 0b1111; 5660 let Inst{23-21} = 0b010; 5661 let Inst{20} = direction; 5662 5663 bits<4> Rt; 5664 bits<4> Rt2; 5665 bits<4> cop; 5666 bits<4> opc1; 5667 bits<4> CRm; 5668 5669 let Inst{15-12} = Rt; 5670 let Inst{19-16} = Rt2; 5671 let Inst{11-8} = cop; 5672 let Inst{7-4} = opc1; 5673 let Inst{3-0} = CRm; 5674 5675 let DecoderMethod = "DecoderForMRRC2AndMCRR2"; 5676} 5677 5678def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */, 5679 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, 5680 GPRnopc:$Rt2, c_imm:$CRm), 5681 [(int_arm_mcrr2 timm:$cop, timm:$opc1, GPRnopc:$Rt, 5682 GPRnopc:$Rt2, timm:$CRm)]>; 5683 5684def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */, 5685 (outs GPRnopc:$Rt, GPRnopc:$Rt2), 5686 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; 5687 5688//===----------------------------------------------------------------------===// 5689// Move between special register and ARM core register 5690// 5691 5692// Move to ARM core register from Special Register 5693def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5694 "mrs", "\t$Rd, apsr", []> { 5695 bits<4> Rd; 5696 let Inst{23-16} = 0b00001111; 5697 let Unpredictable{19-17} = 0b111; 5698 5699 let Inst{15-12} = Rd; 5700 5701 let Inst{11-0} = 0b000000000000; 5702 let Unpredictable{11-0} = 0b110100001111; 5703} 5704 5705def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p), 0>, 5706 Requires<[IsARM]>; 5707 5708// The MRSsys instruction is the MRS instruction from the ARM ARM, 5709// section B9.3.9, with the R bit set to 1. 5710def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5711 "mrs", "\t$Rd, spsr", []> { 5712 bits<4> Rd; 5713 let Inst{23-16} = 0b01001111; 5714 let Unpredictable{19-16} = 0b1111; 5715 5716 let Inst{15-12} = Rd; 5717 5718 let Inst{11-0} = 0b000000000000; 5719 let Unpredictable{11-0} = 0b110100001111; 5720} 5721 5722// However, the MRS (banked register) system instruction (ARMv7VE) *does* have a 5723// separate encoding (distinguished by bit 5. 5724def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked), 5725 NoItinerary, "mrs", "\t$Rd, $banked", []>, 5726 Requires<[IsARM, HasVirtualization]> { 5727 bits<6> banked; 5728 bits<4> Rd; 5729 5730 let Inst{23} = 0; 5731 let Inst{22} = banked{5}; // R bit 5732 let Inst{21-20} = 0b00; 5733 let Inst{19-16} = banked{3-0}; 5734 let Inst{15-12} = Rd; 5735 let Inst{11-9} = 0b001; 5736 let Inst{8} = banked{4}; 5737 let Inst{7-0} = 0b00000000; 5738} 5739 5740// Move from ARM core register to Special Register 5741// 5742// No need to have both system and application versions of MSR (immediate) or 5743// MSR (register), the encodings are the same and the assembly parser has no way 5744// to distinguish between them. The mask operand contains the special register 5745// (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be 5746// accessed in the special register. 5747let Defs = [CPSR] in 5748def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, 5749 "msr", "\t$mask, $Rn", []> { 5750 bits<5> mask; 5751 bits<4> Rn; 5752 5753 let Inst{23} = 0; 5754 let Inst{22} = mask{4}; // R bit 5755 let Inst{21-20} = 0b10; 5756 let Inst{19-16} = mask{3-0}; 5757 let Inst{15-12} = 0b1111; 5758 let Inst{11-4} = 0b00000000; 5759 let Inst{3-0} = Rn; 5760} 5761 5762let Defs = [CPSR] in 5763def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary, 5764 "msr", "\t$mask, $imm", []> { 5765 bits<5> mask; 5766 bits<12> imm; 5767 5768 let Inst{23} = 0; 5769 let Inst{22} = mask{4}; // R bit 5770 let Inst{21-20} = 0b10; 5771 let Inst{19-16} = mask{3-0}; 5772 let Inst{15-12} = 0b1111; 5773 let Inst{11-0} = imm; 5774} 5775 5776// However, the MSR (banked register) system instruction (ARMv7VE) *does* have a 5777// separate encoding (distinguished by bit 5. 5778def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn), 5779 NoItinerary, "msr", "\t$banked, $Rn", []>, 5780 Requires<[IsARM, HasVirtualization]> { 5781 bits<6> banked; 5782 bits<4> Rn; 5783 5784 let Inst{23} = 0; 5785 let Inst{22} = banked{5}; // R bit 5786 let Inst{21-20} = 0b10; 5787 let Inst{19-16} = banked{3-0}; 5788 let Inst{15-12} = 0b1111; 5789 let Inst{11-9} = 0b001; 5790 let Inst{8} = banked{4}; 5791 let Inst{7-4} = 0b0000; 5792 let Inst{3-0} = Rn; 5793} 5794 5795// Dynamic stack allocation yields a _chkstk for Windows targets. These calls 5796// are needed to probe the stack when allocating more than 5797// 4k bytes in one go. Touching the stack at 4K increments is necessary to 5798// ensure that the guard pages used by the OS virtual memory manager are 5799// allocated in correct sequence. 5800// The main point of having separate instruction are extra unmodelled effects 5801// (compared to ordinary calls) like stack pointer change. 5802 5803def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone, 5804 [SDNPHasChain, SDNPSideEffect]>; 5805let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP], hasNoSchedulingInfo = 1 in 5806 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>; 5807 5808def win__dbzchk : SDNode<"ARMISD::WIN__DBZCHK", SDT_WIN__DBZCHK, 5809 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 5810let usesCustomInserter = 1, Defs = [CPSR], hasNoSchedulingInfo = 1 in 5811 def WIN__DBZCHK : PseudoInst<(outs), (ins tGPR:$divisor), NoItinerary, 5812 [(win__dbzchk tGPR:$divisor)]>; 5813 5814//===----------------------------------------------------------------------===// 5815// TLS Instructions 5816// 5817 5818// __aeabi_read_tp preserves the registers r1-r3. 5819// This is a pseudo inst so that we can get the encoding right, 5820// complete with fixup for the aeabi_read_tp function. 5821// TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern 5822// is defined in "ARMInstrThumb.td". 5823let isCall = 1, 5824 Defs = [R0, R12, LR, CPSR], Uses = [SP] in { 5825 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br, 5826 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>, 5827 Requires<[IsARM, IsReadTPSoft]>; 5828} 5829 5830// Reading thread pointer from coprocessor register 5831def : ARMPat<(ARMthread_pointer), (MRC 15, 0, 13, 0, 3)>, 5832 Requires<[IsARM, IsReadTPHard]>; 5833 5834//===----------------------------------------------------------------------===// 5835// SJLJ Exception handling intrinsics 5836// eh_sjlj_setjmp() is an instruction sequence to store the return 5837// address and save #0 in R0 for the non-longjmp case. 5838// Since by its nature we may be coming from some other function to get 5839// here, and we're using the stack frame for the containing function to 5840// save/restore registers, we can't keep anything live in regs across 5841// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 5842// when we get here from a longjmp(). We force everything out of registers 5843// except for our own input by listing the relevant registers in Defs. By 5844// doing so, we also cause the prologue/epilogue code to actively preserve 5845// all of the callee-saved registers, which is exactly what we want. 5846// A constant value is passed in $val, and we use the location as a scratch. 5847// 5848// These are pseudo-instructions and are lowered to individual MC-insts, so 5849// no encoding information is necessary. 5850let Defs = 5851 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, 5852 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ], 5853 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5854 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5855 NoItinerary, 5856 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5857 Requires<[IsARM, HasVFP2]>; 5858} 5859 5860let Defs = 5861 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], 5862 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5863 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5864 NoItinerary, 5865 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5866 Requires<[IsARM, NoVFP]>; 5867} 5868 5869// FIXME: Non-IOS version(s) 5870let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, 5871 Defs = [ R7, LR, SP ] in { 5872def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch), 5873 NoItinerary, 5874 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 5875 Requires<[IsARM]>; 5876} 5877 5878let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1 in 5879def Int_eh_sjlj_setup_dispatch : PseudoInst<(outs), (ins), NoItinerary, 5880 [(ARMeh_sjlj_setup_dispatch)]>; 5881 5882// eh.sjlj.dispatchsetup pseudo-instruction. 5883// This pseudo is used for both ARM and Thumb. Any differences are handled when 5884// the pseudo is expanded (which happens before any passes that need the 5885// instruction size). 5886let isBarrier = 1 in 5887def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>; 5888 5889 5890//===----------------------------------------------------------------------===// 5891// Non-Instruction Patterns 5892// 5893 5894// ARMv4 indirect branch using (MOVr PC, dst) 5895let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in 5896 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst), 5897 4, IIC_Br, [(brind GPR:$dst)], 5898 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5899 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5900 5901let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in 5902 def TAILJMPr4 : ARMPseudoExpand<(outs), (ins GPR:$dst), 5903 4, IIC_Br, [], 5904 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5905 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5906 5907// Large immediate handling. 5908 5909// 32-bit immediate using two piece mod_imms or movw + movt. 5910// This is a single pseudo instruction, the benefit is that it can be remat'd 5911// as a single unit instead of having to handle reg inputs. 5912// FIXME: Remove this when we can do generalized remat. 5913let isReMaterializable = 1, isMoveImm = 1 in 5914def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, 5915 [(set GPR:$dst, (arm_i32imm:$src))]>, 5916 Requires<[IsARM]>; 5917 5918def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i, 5919 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>, 5920 Requires<[IsARM, DontUseMovt]>; 5921 5922// Pseudo instruction that combines movw + movt + add pc (if PIC). 5923// It also makes it possible to rematerialize the instructions. 5924// FIXME: Remove this when we can do generalized remat and when machine licm 5925// can properly the instructions. 5926let isReMaterializable = 1 in { 5927def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5928 IIC_iMOVix2addpc, 5929 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, 5930 Requires<[IsARM, UseMovtInPic]>; 5931 5932def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5933 IIC_iLoadiALU, 5934 [(set GPR:$dst, 5935 (ARMWrapperPIC tglobaladdr:$addr))]>, 5936 Requires<[IsARM, DontUseMovtInPic]>; 5937 5938let AddedComplexity = 10 in 5939def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5940 NoItinerary, 5941 [(set GPR:$dst, 5942 (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5943 Requires<[IsARM, DontUseMovtInPic]>; 5944 5945let AddedComplexity = 10 in 5946def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5947 IIC_iMOVix2ld, 5948 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5949 Requires<[IsARM, UseMovtInPic]>; 5950} // isReMaterializable 5951 5952// The many different faces of TLS access. 5953def : ARMPat<(ARMWrapper tglobaltlsaddr :$dst), 5954 (MOVi32imm tglobaltlsaddr :$dst)>, 5955 Requires<[IsARM, UseMovt]>; 5956 5957def : Pat<(ARMWrapper tglobaltlsaddr:$src), 5958 (LDRLIT_ga_abs tglobaltlsaddr:$src)>, 5959 Requires<[IsARM, DontUseMovt]>; 5960 5961def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 5962 (MOV_ga_pcrel tglobaltlsaddr:$addr)>, Requires<[IsARM, UseMovtInPic]>; 5963 5964def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 5965 (LDRLIT_ga_pcrel tglobaltlsaddr:$addr)>, 5966 Requires<[IsARM, DontUseMovtInPic]>; 5967let AddedComplexity = 10 in 5968def : Pat<(load (ARMWrapperPIC tglobaltlsaddr:$addr)), 5969 (MOV_ga_pcrel_ldr tglobaltlsaddr:$addr)>, 5970 Requires<[IsARM, UseMovtInPic]>; 5971 5972 5973// ConstantPool, GlobalAddress, and JumpTable 5974def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; 5975def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>, 5976 Requires<[IsARM, UseMovt]>; 5977def : ARMPat<(ARMWrapper texternalsym :$dst), (MOVi32imm texternalsym :$dst)>, 5978 Requires<[IsARM, UseMovt]>; 5979def : ARMPat<(ARMWrapperJT tjumptable:$dst), 5980 (LEApcrelJT tjumptable:$dst)>; 5981 5982// TODO: add,sub,and, 3-instr forms? 5983 5984// Tail calls. These patterns also apply to Thumb mode. 5985def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>; 5986def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>; 5987def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>; 5988 5989// Direct calls 5990def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>; 5991def : ARMPat<(ARMcall_nolink texternalsym:$func), 5992 (BMOVPCB_CALL texternalsym:$func)>; 5993 5994// zextload i1 -> zextload i8 5995def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5996def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5997 5998// extload -> zextload 5999def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 6000def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 6001def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 6002def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 6003 6004def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; 6005 6006def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>; 6007def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; 6008 6009// smul* and smla* 6010def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), 6011 (SMULBB GPR:$a, GPR:$b)>; 6012def : ARMV5TEPat<(mul sext_16_node:$a, (sext_bottom_16 GPR:$b)), 6013 (SMULBB GPR:$a, GPR:$b)>; 6014def : ARMV5TEPat<(mul sext_16_node:$a, (sext_top_16 GPR:$b)), 6015 (SMULBT GPR:$a, GPR:$b)>; 6016def : ARMV5TEPat<(mul (sext_top_16 GPR:$a), sext_16_node:$b), 6017 (SMULTB GPR:$a, GPR:$b)>; 6018def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, sext_16_node:$b)), 6019 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 6020def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, (sext_bottom_16 GPR:$b))), 6021 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 6022def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, (sext_top_16 GPR:$b))), 6023 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 6024def : ARMV5MOPat<(add GPR:$acc, (mul (sext_top_16 GPR:$a), sext_16_node:$b)), 6025 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 6026 6027def : ARMV5TEPat<(int_arm_smulbb GPR:$a, GPR:$b), 6028 (SMULBB GPR:$a, GPR:$b)>; 6029def : ARMV5TEPat<(int_arm_smulbt GPR:$a, GPR:$b), 6030 (SMULBT GPR:$a, GPR:$b)>; 6031def : ARMV5TEPat<(int_arm_smultb GPR:$a, GPR:$b), 6032 (SMULTB GPR:$a, GPR:$b)>; 6033def : ARMV5TEPat<(int_arm_smultt GPR:$a, GPR:$b), 6034 (SMULTT GPR:$a, GPR:$b)>; 6035def : ARMV5TEPat<(int_arm_smulwb GPR:$a, GPR:$b), 6036 (SMULWB GPR:$a, GPR:$b)>; 6037def : ARMV5TEPat<(int_arm_smulwt GPR:$a, GPR:$b), 6038 (SMULWT GPR:$a, GPR:$b)>; 6039 6040def : ARMV5TEPat<(int_arm_smlabb GPR:$a, GPR:$b, GPR:$acc), 6041 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 6042def : ARMV5TEPat<(int_arm_smlabt GPR:$a, GPR:$b, GPR:$acc), 6043 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 6044def : ARMV5TEPat<(int_arm_smlatb GPR:$a, GPR:$b, GPR:$acc), 6045 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 6046def : ARMV5TEPat<(int_arm_smlatt GPR:$a, GPR:$b, GPR:$acc), 6047 (SMLATT GPR:$a, GPR:$b, GPR:$acc)>; 6048def : ARMV5TEPat<(int_arm_smlawb GPR:$a, GPR:$b, GPR:$acc), 6049 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 6050def : ARMV5TEPat<(int_arm_smlawt GPR:$a, GPR:$b, GPR:$acc), 6051 (SMLAWT GPR:$a, GPR:$b, GPR:$acc)>; 6052 6053// Pre-v7 uses MCR for synchronization barriers. 6054def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>, 6055 Requires<[IsARM, HasV6]>; 6056 6057// SXT/UXT with no rotate 6058let AddedComplexity = 16 in { 6059def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>; 6060def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>; 6061def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>; 6062def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)), 6063 (UXTAB GPR:$Rn, GPR:$Rm, 0)>; 6064def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)), 6065 (UXTAH GPR:$Rn, GPR:$Rm, 0)>; 6066} 6067 6068def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>; 6069def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>; 6070 6071def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)), 6072 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>; 6073def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)), 6074 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>; 6075 6076// Atomic load/store patterns 6077def : ARMPat<(atomic_load_8 ldst_so_reg:$src), 6078 (LDRBrs ldst_so_reg:$src)>; 6079def : ARMPat<(atomic_load_8 addrmode_imm12:$src), 6080 (LDRBi12 addrmode_imm12:$src)>; 6081def : ARMPat<(atomic_load_16 addrmode3:$src), 6082 (LDRH addrmode3:$src)>; 6083def : ARMPat<(atomic_load_32 ldst_so_reg:$src), 6084 (LDRrs ldst_so_reg:$src)>; 6085def : ARMPat<(atomic_load_32 addrmode_imm12:$src), 6086 (LDRi12 addrmode_imm12:$src)>; 6087def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val), 6088 (STRBrs GPR:$val, ldst_so_reg:$ptr)>; 6089def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val), 6090 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>; 6091def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val), 6092 (STRH GPR:$val, addrmode3:$ptr)>; 6093def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val), 6094 (STRrs GPR:$val, ldst_so_reg:$ptr)>; 6095def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val), 6096 (STRi12 GPR:$val, addrmode_imm12:$ptr)>; 6097 6098 6099//===----------------------------------------------------------------------===// 6100// Thumb Support 6101// 6102 6103include "ARMInstrThumb.td" 6104 6105//===----------------------------------------------------------------------===// 6106// Thumb2 Support 6107// 6108 6109include "ARMInstrThumb2.td" 6110 6111//===----------------------------------------------------------------------===// 6112// Floating Point Support 6113// 6114 6115include "ARMInstrVFP.td" 6116 6117//===----------------------------------------------------------------------===// 6118// Advanced SIMD (NEON) Support 6119// 6120 6121include "ARMInstrNEON.td" 6122 6123//===----------------------------------------------------------------------===// 6124// MVE Support 6125// 6126 6127include "ARMInstrMVE.td" 6128 6129//===----------------------------------------------------------------------===// 6130// CDE (Custom Datapath Extension) 6131// 6132 6133include "ARMInstrCDE.td" 6134 6135//===----------------------------------------------------------------------===// 6136// Assembler aliases 6137// 6138 6139// Memory barriers 6140def : InstAlias<"dmb", (DMB 0xf), 0>, Requires<[IsARM, HasDB]>; 6141def : InstAlias<"dsb", (DSB 0xf), 0>, Requires<[IsARM, HasDB]>; 6142def : InstAlias<"ssbb", (DSB 0x0), 1>, Requires<[IsARM, HasDB]>; 6143def : InstAlias<"pssbb", (DSB 0x4), 1>, Requires<[IsARM, HasDB]>; 6144def : InstAlias<"isb", (ISB 0xf), 0>, Requires<[IsARM, HasDB]>; 6145// Armv8-R 'Data Full Barrier' 6146def : InstAlias<"dfb", (DSB 0xc), 1>, Requires<[IsARM, HasDFB]>; 6147 6148// System instructions 6149def : MnemonicAlias<"swi", "svc">; 6150 6151// Load / Store Multiple 6152def : MnemonicAlias<"ldmfd", "ldm">; 6153def : MnemonicAlias<"ldmia", "ldm">; 6154def : MnemonicAlias<"ldmea", "ldmdb">; 6155def : MnemonicAlias<"stmfd", "stmdb">; 6156def : MnemonicAlias<"stmia", "stm">; 6157def : MnemonicAlias<"stmea", "stm">; 6158 6159// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the 6160// input operands swapped when the shift amount is zero (i.e., unspecified). 6161def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", 6162 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p), 0>, 6163 Requires<[IsARM, HasV6]>; 6164def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", 6165 (PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p), 0>, 6166 Requires<[IsARM, HasV6]>; 6167 6168// PUSH/POP aliases for STM/LDM 6169def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>; 6170def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>; 6171 6172// SSAT/USAT optional shift operand. 6173def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn", 6174 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 6175def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn", 6176 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 6177 6178 6179// Extend instruction optional rotate operand. 6180def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm", 6181 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 6182def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm", 6183 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 6184def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm", 6185 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 6186def : ARMInstAlias<"sxtb${p} $Rd, $Rm", 6187 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6188def : ARMInstAlias<"sxtb16${p} $Rd, $Rm", 6189 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6190def : ARMInstAlias<"sxth${p} $Rd, $Rm", 6191 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6192 6193def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm", 6194 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 6195def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm", 6196 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 6197def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm", 6198 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 6199def : ARMInstAlias<"uxtb${p} $Rd, $Rm", 6200 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6201def : ARMInstAlias<"uxtb16${p} $Rd, $Rm", 6202 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6203def : ARMInstAlias<"uxth${p} $Rd, $Rm", 6204 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6205 6206 6207// RFE aliases 6208def : MnemonicAlias<"rfefa", "rfeda">; 6209def : MnemonicAlias<"rfeea", "rfedb">; 6210def : MnemonicAlias<"rfefd", "rfeia">; 6211def : MnemonicAlias<"rfeed", "rfeib">; 6212def : MnemonicAlias<"rfe", "rfeia">; 6213 6214// SRS aliases 6215def : MnemonicAlias<"srsfa", "srsib">; 6216def : MnemonicAlias<"srsea", "srsia">; 6217def : MnemonicAlias<"srsfd", "srsdb">; 6218def : MnemonicAlias<"srsed", "srsda">; 6219def : MnemonicAlias<"srs", "srsia">; 6220 6221// QSAX == QSUBADDX 6222def : MnemonicAlias<"qsubaddx", "qsax">; 6223// SASX == SADDSUBX 6224def : MnemonicAlias<"saddsubx", "sasx">; 6225// SHASX == SHADDSUBX 6226def : MnemonicAlias<"shaddsubx", "shasx">; 6227// SHSAX == SHSUBADDX 6228def : MnemonicAlias<"shsubaddx", "shsax">; 6229// SSAX == SSUBADDX 6230def : MnemonicAlias<"ssubaddx", "ssax">; 6231// UASX == UADDSUBX 6232def : MnemonicAlias<"uaddsubx", "uasx">; 6233// UHASX == UHADDSUBX 6234def : MnemonicAlias<"uhaddsubx", "uhasx">; 6235// UHSAX == UHSUBADDX 6236def : MnemonicAlias<"uhsubaddx", "uhsax">; 6237// UQASX == UQADDSUBX 6238def : MnemonicAlias<"uqaddsubx", "uqasx">; 6239// UQSAX == UQSUBADDX 6240def : MnemonicAlias<"uqsubaddx", "uqsax">; 6241// USAX == USUBADDX 6242def : MnemonicAlias<"usubaddx", "usax">; 6243 6244// "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like 6245// for isel. 6246def : ARMInstSubst<"mov${s}${p} $Rd, $imm", 6247 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6248def : ARMInstSubst<"mvn${s}${p} $Rd, $imm", 6249 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6250// Same for AND <--> BIC 6251def : ARMInstSubst<"bic${s}${p} $Rd, $Rn, $imm", 6252 (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, 6253 pred:$p, cc_out:$s)>; 6254def : ARMInstSubst<"bic${s}${p} $Rdn, $imm", 6255 (ANDri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, 6256 pred:$p, cc_out:$s)>; 6257def : ARMInstSubst<"and${s}${p} $Rd, $Rn, $imm", 6258 (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, 6259 pred:$p, cc_out:$s)>; 6260def : ARMInstSubst<"and${s}${p} $Rdn, $imm", 6261 (BICri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, 6262 pred:$p, cc_out:$s)>; 6263 6264// Likewise, "add Rd, mod_imm_neg" -> sub 6265def : ARMInstSubst<"add${s}${p} $Rd, $Rn, $imm", 6266 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6267def : ARMInstSubst<"add${s}${p} $Rd, $imm", 6268 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6269// Likewise, "sub Rd, mod_imm_neg" -> add 6270def : ARMInstSubst<"sub${s}${p} $Rd, $Rn, $imm", 6271 (ADDri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6272def : ARMInstSubst<"sub${s}${p} $Rd, $imm", 6273 (ADDri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6274 6275 6276def : ARMInstSubst<"adc${s}${p} $Rd, $Rn, $imm", 6277 (SBCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6278def : ARMInstSubst<"adc${s}${p} $Rdn, $imm", 6279 (SBCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6280def : ARMInstSubst<"sbc${s}${p} $Rd, $Rn, $imm", 6281 (ADCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6282def : ARMInstSubst<"sbc${s}${p} $Rdn, $imm", 6283 (ADCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6284 6285// Same for CMP <--> CMN via mod_imm_neg 6286def : ARMInstSubst<"cmp${p} $Rd, $imm", 6287 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; 6288def : ARMInstSubst<"cmn${p} $Rd, $imm", 6289 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; 6290 6291// The shifter forms of the MOV instruction are aliased to the ASR, LSL, 6292// LSR, ROR, and RRX instructions. 6293// FIXME: We need C++ parser hooks to map the alias to the MOV 6294// encoding. It seems we should be able to do that sort of thing 6295// in tblgen, but it could get ugly. 6296let TwoOperandAliasConstraint = "$Rm = $Rd" in { 6297def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm", 6298 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 6299 cc_out:$s)>; 6300def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm", 6301 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 6302 cc_out:$s)>; 6303def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm", 6304 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 6305 cc_out:$s)>; 6306def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm", 6307 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 6308 cc_out:$s)>; 6309} 6310def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm", 6311 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>; 6312let TwoOperandAliasConstraint = "$Rn = $Rd" in { 6313def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm", 6314 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6315 cc_out:$s)>; 6316def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm", 6317 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6318 cc_out:$s)>; 6319def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm", 6320 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6321 cc_out:$s)>; 6322def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm", 6323 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6324 cc_out:$s)>; 6325} 6326 6327// "neg" is and alias for "rsb rd, rn, #0" 6328def : ARMInstAlias<"neg${s}${p} $Rd, $Rm", 6329 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>; 6330 6331// Pre-v6, 'mov r0, r0' was used as a NOP encoding. 6332def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>, 6333 Requires<[IsARM, NoV6]>; 6334 6335// MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but 6336// the instruction definitions need difference constraints pre-v6. 6337// Use these aliases for the assembly parsing on pre-v6. 6338def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm", 6339 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s), 0>, 6340 Requires<[IsARM, NoV6]>; 6341def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra", 6342 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 6343 pred:$p, cc_out:$s), 0>, 6344 Requires<[IsARM, NoV6]>; 6345def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6346 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6347 Requires<[IsARM, NoV6]>; 6348def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6349 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6350 Requires<[IsARM, NoV6]>; 6351def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6352 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6353 Requires<[IsARM, NoV6]>; 6354def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6355 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6356 Requires<[IsARM, NoV6]>; 6357 6358// 'it' blocks in ARM mode just validate the predicates. The IT itself 6359// is discarded. 6360def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>, 6361 ComplexDeprecationPredicate<"IT">; 6362 6363let mayLoad = 1, mayStore =1, hasSideEffects = 1, hasNoSchedulingInfo = 1 in 6364def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn), 6365 NoItinerary, 6366 [(set GPR:$Rd, (int_arm_space timm:$size, GPR:$Rn))]>; 6367 6368//===---------------------------------- 6369// Atomic cmpxchg for -O0 6370//===---------------------------------- 6371 6372// The fast register allocator used during -O0 inserts spills to cover any VRegs 6373// live across basic block boundaries. When this happens between an LDXR and an 6374// STXR it can clear the exclusive monitor, causing all cmpxchg attempts to 6375// fail. 6376 6377// Unfortunately, this means we have to have an alternative (expanded 6378// post-regalloc) path for -O0 compilations. Fortunately this path can be 6379// significantly more naive than the standard expansion: we conservatively 6380// assume seq_cst, strong cmpxchg and omit clrex on failure. 6381 6382let Constraints = "@earlyclobber $Rd,@earlyclobber $temp", 6383 mayLoad = 1, mayStore = 1 in { 6384def CMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6385 (ins GPR:$addr, GPR:$desired, GPR:$new), 6386 NoItinerary, []>, Sched<[]>; 6387 6388def CMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6389 (ins GPR:$addr, GPR:$desired, GPR:$new), 6390 NoItinerary, []>, Sched<[]>; 6391 6392def CMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6393 (ins GPR:$addr, GPR:$desired, GPR:$new), 6394 NoItinerary, []>, Sched<[]>; 6395 6396def CMP_SWAP_64 : PseudoInst<(outs GPRPair:$Rd, GPR:$temp), 6397 (ins GPR:$addr, GPRPair:$desired, GPRPair:$new), 6398 NoItinerary, []>, Sched<[]>; 6399} 6400 6401def CompilerBarrier : PseudoInst<(outs), (ins i32imm:$ordering), NoItinerary, 6402 [(atomic_fence timm:$ordering, 0)]> { 6403 let hasSideEffects = 1; 6404 let Size = 0; 6405 let AsmString = "@ COMPILER BARRIER"; 6406 let hasNoSchedulingInfo = 1; 6407} 6408