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Lines Matching refs:Enable

59                                         "Enable 64-bit instructions">;
61 "Enable floating-point instructions">;
63 "Enable 64-bit registers usage for ppc32 [beta]">;
67 "Enable classic FPU instructions",
70 "Enable Altivec instructions",
73 "Enable SPE instructions",
76 "Enable the MFOCRF instruction">;
78 "Enable the fsqrt instruction",
81 "Enable the fcpsgn instruction",
84 "Enable the fre instruction",
87 "Enable the fres instruction",
90 "Enable the frsqrte instruction",
93 "Enable the frsqrtes instruction",
98 "Enable the stfiwx instruction",
101 "Enable the lfiwax instruction",
104 "Enable the fri[mnpz] instructions",
107 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",
110 "Enable the isel instruction">;
112 "Enable the bpermd instruction">;
114 "Enable extended divide instructions">;
116 "Enable the ldbrx instruction">;
118 "Enable the cmpb instruction">;
120 "Enable icbt instruction">;
122 "Enable Book E instructions",
128 "Enable E500/E500mc instructions">;
130 "Enable secure plt mode">;
132 "Enable PPC 4xx instructions">;
134 "Enable PPC 6xx instructions">;
136 "Enable VSX instructions",
142 "Enable POWER8 Altivec instructions",
145 "Enable POWER8 Crypto instructions",
148 "Enable POWER8 vector instructions",
152 "Enable Power8 direct move instructions",
156 "Enable l[bh]arx and st[bh]cx.">;
164 "Enable Hardware Transactional Memory instructions">;
191 "Enable the __float128 data type for IEEE-754R Binary128.",
195 "Enable the popcnt[dw] instructions">;
208 "Enable instructions in ISA 3.0.">;
211 "Enable instructions in ISA 3.1.",
214 "Enable POWER9 Altivec instructions",
217 "Enable POWER9 vector instructions",
222 "Enable POWER10 vector instructions",
233 "Enable prefixed instructions",
238 "Enable PC relative Memory Ops",
245 "Enable MMA instructions",