1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This is the top level entry point for the PowerPC target. 10// 11//===----------------------------------------------------------------------===// 12 13// Get the target-independent interfaces which we are implementing. 14// 15include "llvm/Target/Target.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC Subtarget features. 19// 20 21//===----------------------------------------------------------------------===// 22// CPU Directives // 23//===----------------------------------------------------------------------===// 24 25def Directive440 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_440", "">; 26def Directive601 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_601", "">; 27def Directive602 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_602", "">; 28def Directive603 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 29def Directive604 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 30def Directive620 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 31def Directive7400: SubtargetFeature<"", "CPUDirective", "PPC::DIR_7400", "">; 32def Directive750 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_750", "">; 33def Directive970 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_970", "">; 34def Directive32 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_32", "">; 35def Directive64 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_64", "">; 36def DirectiveA2 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_A2", "">; 37def DirectiveE500 : SubtargetFeature<"", "CPUDirective", 38 "PPC::DIR_E500", "">; 39def DirectiveE500mc : SubtargetFeature<"", "CPUDirective", 40 "PPC::DIR_E500mc", "">; 41def DirectiveE5500 : SubtargetFeature<"", "CPUDirective", 42 "PPC::DIR_E5500", "">; 43def DirectivePwr3: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR3", "">; 44def DirectivePwr4: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR4", "">; 45def DirectivePwr5: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5", "">; 46def DirectivePwr5x 47 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5X", "">; 48def DirectivePwr6: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6", "">; 49def DirectivePwr6x 50 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6X", "">; 51def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">; 52def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">; 53def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">; 54def DirectivePwr10: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR10", "">; 55def DirectivePwrFuture 56 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">; 57 58def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", 59 "Enable 64-bit instructions">; 60def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true", 61 "Enable floating-point instructions">; 62def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", 63 "Enable 64-bit registers usage for ppc32 [beta]">; 64def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true", 65 "Use condition-register bits individually">; 66def FeatureFPU : SubtargetFeature<"fpu","HasFPU","true", 67 "Enable classic FPU instructions", 68 [FeatureHardFloat]>; 69def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", 70 "Enable Altivec instructions", 71 [FeatureFPU]>; 72def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true", 73 "Enable SPE instructions", 74 [FeatureHardFloat]>; 75def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", 76 "Enable the MFOCRF instruction">; 77def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", 78 "Enable the fsqrt instruction", 79 [FeatureFPU]>; 80def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true", 81 "Enable the fcpsgn instruction", 82 [FeatureFPU]>; 83def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true", 84 "Enable the fre instruction", 85 [FeatureFPU]>; 86def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true", 87 "Enable the fres instruction", 88 [FeatureFPU]>; 89def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true", 90 "Enable the frsqrte instruction", 91 [FeatureFPU]>; 92def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true", 93 "Enable the frsqrtes instruction", 94 [FeatureFPU]>; 95def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true", 96 "Assume higher precision reciprocal estimates">; 97def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", 98 "Enable the stfiwx instruction", 99 [FeatureFPU]>; 100def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true", 101 "Enable the lfiwax instruction", 102 [FeatureFPU]>; 103def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true", 104 "Enable the fri[mnpz] instructions", 105 [FeatureFPU]>; 106def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true", 107 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions", 108 [FeatureFPU]>; 109def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", 110 "Enable the isel instruction">; 111def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true", 112 "Enable the bpermd instruction">; 113def FeatureExtDiv : SubtargetFeature<"extdiv", "HasExtDiv", "true", 114 "Enable extended divide instructions">; 115def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true", 116 "Enable the ldbrx instruction">; 117def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true", 118 "Enable the cmpb instruction">; 119def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true", 120 "Enable icbt instruction">; 121def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true", 122 "Enable Book E instructions", 123 [FeatureICBT]>; 124def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true", 125 "Has only the msync instruction instead of sync", 126 [FeatureBookE]>; 127def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true", 128 "Enable E500/E500mc instructions">; 129def FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt", "true", 130 "Enable secure plt mode">; 131def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true", 132 "Enable PPC 4xx instructions">; 133def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true", 134 "Enable PPC 6xx instructions">; 135def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true", 136 "Enable VSX instructions", 137 [FeatureAltivec]>; 138def FeatureTwoConstNR : 139 SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true", 140 "Requires two constant Newton-Raphson computation">; 141def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true", 142 "Enable POWER8 Altivec instructions", 143 [FeatureAltivec]>; 144def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true", 145 "Enable POWER8 Crypto instructions", 146 [FeatureP8Altivec]>; 147def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true", 148 "Enable POWER8 vector instructions", 149 [FeatureVSX, FeatureP8Altivec]>; 150def FeatureDirectMove : 151 SubtargetFeature<"direct-move", "HasDirectMove", "true", 152 "Enable Power8 direct move instructions", 153 [FeatureVSX]>; 154def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics", 155 "HasPartwordAtomics", "true", 156 "Enable l[bh]arx and st[bh]cx.">; 157def FeatureInvariantFunctionDescriptors : 158 SubtargetFeature<"invariant-function-descriptors", 159 "HasInvariantFunctionDescriptors", "true", 160 "Assume function descriptors are invariant">; 161def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true", 162 "Always use indirect calls">; 163def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true", 164 "Enable Hardware Transactional Memory instructions">; 165def FeatureMFTB : SubtargetFeature<"", "FeatureMFTB", "true", 166 "Implement mftb using the mfspr instruction">; 167def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true", 168 "Target supports instruction fusion">; 169def FeatureAddiLoadFusion : SubtargetFeature<"fuse-addi-load", 170 "HasAddiLoadFusion", "true", 171 "Power8 Addi-Load fusion", 172 [FeatureFusion]>; 173def FeatureAddisLoadFusion : SubtargetFeature<"fuse-addis-load", 174 "HasAddisLoadFusion", "true", 175 "Power8 Addis-Load fusion", 176 [FeatureFusion]>; 177def FeatureStoreFusion : SubtargetFeature<"fuse-store", "HasStoreFusion", "true", 178 "Target supports store clustering", 179 [FeatureFusion]>; 180def FeatureUnalignedFloats : 181 SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess", 182 "true", "CPU does not trap on unaligned FP access">; 183def FeaturePPCPreRASched: 184 SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true", 185 "Use PowerPC pre-RA scheduling strategy">; 186def FeaturePPCPostRASched: 187 SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true", 188 "Use PowerPC post-RA scheduling strategy">; 189def FeatureFloat128 : 190 SubtargetFeature<"float128", "HasFloat128", "true", 191 "Enable the __float128 data type for IEEE-754R Binary128.", 192 [FeatureVSX]>; 193def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", 194 "POPCNTD_Fast", 195 "Enable the popcnt[dw] instructions">; 196// Note that for the a2 processor models we should not use popcnt[dw] by 197// default. These processors do support the instructions, but they're 198// microcoded, and the software emulation is about twice as fast. 199def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD", 200 "POPCNTD_Slow", 201 "Has slow popcnt[dw] instructions">; 202 203def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true", 204 "Treat vector data stream cache control instructions as deprecated">; 205 206def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0", 207 "true", 208 "Enable instructions in ISA 3.0.">; 209def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1", 210 "true", 211 "Enable instructions in ISA 3.1.", 212 [FeatureISA3_0]>; 213def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true", 214 "Enable POWER9 Altivec instructions", 215 [FeatureISA3_0, FeatureP8Altivec]>; 216def FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true", 217 "Enable POWER9 vector instructions", 218 [FeatureISA3_0, FeatureP8Vector, 219 FeatureP9Altivec]>; 220def FeatureP10Vector : SubtargetFeature<"power10-vector", "HasP10Vector", 221 "true", 222 "Enable POWER10 vector instructions", 223 [FeatureISA3_1, FeatureP9Vector]>; 224// A separate feature for this even though it is equivalent to P9Vector 225// because this is a feature of the implementation rather than the architecture 226// and may go away with future CPU's. 227def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units", 228 "VectorsUseTwoUnits", 229 "true", 230 "Vectors use two units">; 231def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs", 232 "true", 233 "Enable prefixed instructions", 234 [FeatureISA3_0, FeatureP8Vector, 235 FeatureP9Altivec]>; 236def FeaturePCRelativeMemops : 237 SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true", 238 "Enable PC relative Memory Ops", 239 [FeatureISA3_0, FeaturePrefixInstrs]>; 240def FeaturePairedVectorMemops: 241 SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true", 242 "32Byte load and store instructions", 243 [FeatureISA3_0]>; 244def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true", 245 "Enable MMA instructions", 246 [FeatureP8Vector, FeatureP9Altivec, 247 FeaturePairedVectorMemops]>; 248 249def FeaturePredictableSelectIsExpensive : 250 SubtargetFeature<"predictable-select-expensive", 251 "PredictableSelectIsExpensive", 252 "true", 253 "Prefer likely predicted branches over selects">; 254 255// Since new processors generally contain a superset of features of those that 256// came before them, the idea is to make implementations of new processors 257// less error prone and easier to read. 258// Namely: 259// list<SubtargetFeature> P8InheritableFeatures = ... 260// list<SubtargetFeature> FutureProcessorAddtionalFeatures = 261// [ features that Power8 does not support but inheritable ] 262// list<SubtargetFeature> FutureProcessorSpecificFeatures = 263// [ features that Power8 does not support and not inheritable ] 264// list<SubtargetFeature> FutureProcessorInheritableFeatures = 265// !listconcat(P8InheritableFeatures, FutureProcessorAddtionalFeatures) 266// list<SubtargetFeature> FutureProcessorFeatures = 267// !listconcat(FutureProcessorInheritableFeatures, 268// FutureProcessorSpecificFeatures) 269 270// Makes it explicit and obvious what is new in FutureProcessor vs. Power8 as 271// well as providing a single point of definition if the feature set will be 272// used elsewhere. 273def ProcessorFeatures { 274 // Power7 275 list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7, 276 FeatureAltivec, 277 FeatureVSX, 278 FeatureMFOCRF, 279 FeatureFCPSGN, 280 FeatureFSqrt, 281 FeatureFRE, 282 FeatureFRES, 283 FeatureFRSQRTE, 284 FeatureFRSQRTES, 285 FeatureRecipPrec, 286 FeatureSTFIWX, 287 FeatureLFIWAX, 288 FeatureFPRND, 289 FeatureFPCVT, 290 FeatureISEL, 291 FeaturePOPCNTD, 292 FeatureCMPB, 293 FeatureLDBRX, 294 Feature64Bit, 295 /* Feature64BitRegs, */ 296 FeatureBPERMD, 297 FeatureExtDiv, 298 FeatureMFTB, 299 DeprecatedDST, 300 FeatureTwoConstNR, 301 FeatureUnalignedFloats]; 302 list<SubtargetFeature> P7SpecificFeatures = []; 303 list<SubtargetFeature> P7Features = 304 !listconcat(P7InheritableFeatures, P7SpecificFeatures); 305 306 // Power8 307 list<SubtargetFeature> P8AdditionalFeatures = 308 [DirectivePwr8, 309 FeatureP8Altivec, 310 FeatureP8Vector, 311 FeatureP8Crypto, 312 FeatureHTM, 313 FeatureDirectMove, 314 FeatureICBT, 315 FeaturePartwordAtomic, 316 FeaturePredictableSelectIsExpensive 317 ]; 318 319 list<SubtargetFeature> P8SpecificFeatures = [FeatureAddiLoadFusion, 320 FeatureAddisLoadFusion]; 321 list<SubtargetFeature> P8InheritableFeatures = 322 !listconcat(P7InheritableFeatures, P8AdditionalFeatures); 323 list<SubtargetFeature> P8Features = 324 !listconcat(P8InheritableFeatures, P8SpecificFeatures); 325 326 // Power9 327 list<SubtargetFeature> P9AdditionalFeatures = 328 [DirectivePwr9, 329 FeatureP9Altivec, 330 FeatureP9Vector, 331 FeaturePPCPreRASched, 332 FeaturePPCPostRASched, 333 FeatureISA3_0, 334 FeaturePredictableSelectIsExpensive 335 ]; 336 337 // Some features are unique to Power9 and there is no reason to assume 338 // they will be part of any future CPUs. One example is the narrower 339 // dispatch for vector operations than scalar ones. For the time being, 340 // this list also includes scheduling-related features since we do not have 341 // enough info to create custom scheduling strategies for future CPUs. 342 list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits]; 343 list<SubtargetFeature> P9InheritableFeatures = 344 !listconcat(P8InheritableFeatures, P9AdditionalFeatures); 345 list<SubtargetFeature> P9Features = 346 !listconcat(P9InheritableFeatures, P9SpecificFeatures); 347 348 // Power10 349 // For P10 CPU we assume that all of the existing features from Power9 350 // still exist with the exception of those we know are Power9 specific. 351 list<SubtargetFeature> FusionFeatures = [FeatureStoreFusion]; 352 list<SubtargetFeature> P10AdditionalFeatures = 353 !listconcat(FusionFeatures, [ 354 DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs, 355 FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA, 356 FeaturePairedVectorMemops]); 357 list<SubtargetFeature> P10SpecificFeatures = []; 358 list<SubtargetFeature> P10InheritableFeatures = 359 !listconcat(P9InheritableFeatures, P10AdditionalFeatures); 360 list<SubtargetFeature> P10Features = 361 !listconcat(P10InheritableFeatures, P10SpecificFeatures); 362 363 // Future 364 // For future CPU we assume that all of the existing features from Power10 365 // still exist with the exception of those we know are Power10 specific. 366 list<SubtargetFeature> FutureAdditionalFeatures = []; 367 list<SubtargetFeature> FutureSpecificFeatures = []; 368 list<SubtargetFeature> FutureInheritableFeatures = 369 !listconcat(P10InheritableFeatures, FutureAdditionalFeatures); 370 list<SubtargetFeature> FutureFeatures = 371 !listconcat(FutureInheritableFeatures, FutureSpecificFeatures); 372} 373 374// Note: Future features to add when support is extended to more 375// recent ISA levels: 376// 377// DFP p6, p6x, p7 decimal floating-point instructions 378// POPCNTB p5 through p7 popcntb and related instructions 379 380//===----------------------------------------------------------------------===// 381// Classes used for relation maps. 382//===----------------------------------------------------------------------===// 383// RecFormRel - Filter class used to relate non-record-form instructions with 384// their record-form variants. 385class RecFormRel; 386 387// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX 388// FMA instruction forms with their corresponding factor-killing forms. 389class AltVSXFMARel { 390 bit IsVSXFMAAlt = 0; 391} 392 393//===----------------------------------------------------------------------===// 394// Relation Map Definitions. 395//===----------------------------------------------------------------------===// 396 397def getRecordFormOpcode : InstrMapping { 398 let FilterClass = "RecFormRel"; 399 // Instructions with the same BaseName and Interpretation64Bit values 400 // form a row. 401 let RowFields = ["BaseName", "Interpretation64Bit"]; 402 // Instructions with the same RC value form a column. 403 let ColFields = ["RC"]; 404 // The key column are the non-record-form instructions. 405 let KeyCol = ["0"]; 406 // Value columns RC=1 407 let ValueCols = [["1"]]; 408} 409 410def getNonRecordFormOpcode : InstrMapping { 411 let FilterClass = "RecFormRel"; 412 // Instructions with the same BaseName and Interpretation64Bit values 413 // form a row. 414 let RowFields = ["BaseName", "Interpretation64Bit"]; 415 // Instructions with the same RC value form a column. 416 let ColFields = ["RC"]; 417 // The key column are the record-form instructions. 418 let KeyCol = ["1"]; 419 // Value columns are RC=0 420 let ValueCols = [["0"]]; 421} 422 423def getAltVSXFMAOpcode : InstrMapping { 424 let FilterClass = "AltVSXFMARel"; 425 // Instructions with the same BaseName value form a row. 426 let RowFields = ["BaseName"]; 427 // Instructions with the same IsVSXFMAAlt value form a column. 428 let ColFields = ["IsVSXFMAAlt"]; 429 // The key column are the (default) addend-killing instructions. 430 let KeyCol = ["0"]; 431 // Value columns IsVSXFMAAlt=1 432 let ValueCols = [["1"]]; 433} 434 435//===----------------------------------------------------------------------===// 436// Register File Description 437//===----------------------------------------------------------------------===// 438 439include "PPCRegisterInfo.td" 440include "PPCSchedule.td" 441include "GISel/PPCRegisterBanks.td" 442 443//===----------------------------------------------------------------------===// 444// PowerPC processors supported. 445// 446 447def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat, 448 FeatureMFTB]>; 449def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, 450 FeatureFRES, FeatureFRSQRTE, 451 FeatureICBT, FeatureBookE, 452 FeatureMSYNC, FeatureMFTB]>; 453def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, 454 FeatureFRES, FeatureFRSQRTE, 455 FeatureICBT, FeatureBookE, 456 FeatureMSYNC, FeatureMFTB]>; 457def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>; 458def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU, 459 FeatureMFTB]>; 460def : Processor<"603", G3Itineraries, [Directive603, 461 FeatureFRES, FeatureFRSQRTE, 462 FeatureMFTB]>; 463def : Processor<"603e", G3Itineraries, [Directive603, 464 FeatureFRES, FeatureFRSQRTE, 465 FeatureMFTB]>; 466def : Processor<"603ev", G3Itineraries, [Directive603, 467 FeatureFRES, FeatureFRSQRTE, 468 FeatureMFTB]>; 469def : Processor<"604", G3Itineraries, [Directive604, 470 FeatureFRES, FeatureFRSQRTE, 471 FeatureMFTB]>; 472def : Processor<"604e", G3Itineraries, [Directive604, 473 FeatureFRES, FeatureFRSQRTE, 474 FeatureMFTB]>; 475def : Processor<"620", G3Itineraries, [Directive620, 476 FeatureFRES, FeatureFRSQRTE, 477 FeatureMFTB]>; 478def : Processor<"750", G4Itineraries, [Directive750, 479 FeatureFRES, FeatureFRSQRTE, 480 FeatureMFTB]>; 481def : Processor<"g3", G3Itineraries, [Directive750, 482 FeatureFRES, FeatureFRSQRTE, 483 FeatureMFTB]>; 484def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec, 485 FeatureFRES, FeatureFRSQRTE, 486 FeatureMFTB]>; 487def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec, 488 FeatureFRES, FeatureFRSQRTE, 489 FeatureMFTB]>; 490def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec, 491 FeatureFRES, FeatureFRSQRTE, 492 FeatureMFTB]>; 493def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec, 494 FeatureFRES, FeatureFRSQRTE, 495 FeatureMFTB]>; 496 497def : ProcessorModel<"970", G5Model, 498 [Directive970, FeatureAltivec, 499 FeatureMFOCRF, FeatureFSqrt, 500 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, 501 Feature64Bit /*, Feature64BitRegs */, 502 FeatureMFTB]>; 503def : ProcessorModel<"g5", G5Model, 504 [Directive970, FeatureAltivec, 505 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, 506 FeatureFRES, FeatureFRSQRTE, 507 Feature64Bit /*, Feature64BitRegs */, 508 FeatureMFTB, DeprecatedDST]>; 509def : ProcessorModel<"e500", PPCE500Model, 510 [DirectiveE500, 511 FeatureICBT, FeatureBookE, 512 FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>; 513def : ProcessorModel<"e500mc", PPCE500mcModel, 514 [DirectiveE500mc, 515 FeatureSTFIWX, FeatureICBT, FeatureBookE, 516 FeatureISEL, FeatureMFTB]>; 517def : ProcessorModel<"e5500", PPCE5500Model, 518 [DirectiveE5500, FeatureMFOCRF, Feature64Bit, 519 FeatureSTFIWX, FeatureICBT, FeatureBookE, 520 FeatureISEL, FeatureMFTB]>; 521def : ProcessorModel<"a2", PPCA2Model, 522 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, 523 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 524 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 525 FeatureSTFIWX, FeatureLFIWAX, 526 FeatureFPRND, FeatureFPCVT, FeatureISEL, 527 FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX, 528 Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>; 529def : ProcessorModel<"pwr3", G5Model, 530 [DirectivePwr3, FeatureAltivec, 531 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, 532 FeatureSTFIWX, Feature64Bit]>; 533def : ProcessorModel<"pwr4", G5Model, 534 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, 535 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, 536 FeatureSTFIWX, Feature64Bit, FeatureMFTB]>; 537def : ProcessorModel<"pwr5", G5Model, 538 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, 539 FeatureFSqrt, FeatureFRE, FeatureFRES, 540 FeatureFRSQRTE, FeatureFRSQRTES, 541 FeatureSTFIWX, Feature64Bit, 542 FeatureMFTB, DeprecatedDST]>; 543def : ProcessorModel<"pwr5x", G5Model, 544 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 545 FeatureFSqrt, FeatureFRE, FeatureFRES, 546 FeatureFRSQRTE, FeatureFRSQRTES, 547 FeatureSTFIWX, FeatureFPRND, Feature64Bit, 548 FeatureMFTB, DeprecatedDST]>; 549def : ProcessorModel<"pwr6", G5Model, 550 [DirectivePwr6, FeatureAltivec, 551 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 552 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 553 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 554 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */, 555 FeatureMFTB, DeprecatedDST]>; 556def : ProcessorModel<"pwr6x", G5Model, 557 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 558 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 559 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 560 FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 561 FeatureFPRND, Feature64Bit, 562 FeatureMFTB, DeprecatedDST]>; 563def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>; 564def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>; 565def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>; 566// No scheduler model yet. 567def : ProcessorModel<"pwr10", P9Model, ProcessorFeatures.P10Features>; 568// No scheduler model for future CPU. 569def : ProcessorModel<"future", NoSchedModel, 570 ProcessorFeatures.FutureFeatures>; 571def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat, 572 FeatureMFTB]>; 573def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat, 574 FeatureMFTB]>; 575def : ProcessorModel<"ppc64", G5Model, 576 [Directive64, FeatureAltivec, 577 FeatureMFOCRF, FeatureFSqrt, FeatureFRES, 578 FeatureFRSQRTE, FeatureSTFIWX, 579 Feature64Bit /*, Feature64BitRegs */, 580 FeatureMFTB]>; 581def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>; 582 583//===----------------------------------------------------------------------===// 584// Calling Conventions 585//===----------------------------------------------------------------------===// 586 587include "PPCCallingConv.td" 588 589def PPCInstrInfo : InstrInfo { 590 let isLittleEndianEncoding = 1; 591 592 // FIXME: Unset this when no longer needed! 593 let decodePositionallyEncodedOperands = 1; 594 595 let noNamedPositionallyEncodedOperands = 1; 596} 597 598def PPCAsmParser : AsmParser { 599 let ShouldEmitMatchRegisterName = 0; 600} 601 602def PPCAsmParserVariant : AsmParserVariant { 603 int Variant = 0; 604 605 // We do not use hard coded registers in asm strings. However, some 606 // InstAlias definitions use immediate literals. Set RegisterPrefix 607 // so that those are not misinterpreted as registers. 608 string RegisterPrefix = "%"; 609 string BreakCharacters = "."; 610} 611 612def PPC : Target { 613 // Information about the instructions. 614 let InstructionSet = PPCInstrInfo; 615 616 let AssemblyParsers = [PPCAsmParser]; 617 let AssemblyParserVariants = [PPCAsmParserVariant]; 618 let AllowRegisterRenaming = 1; 619} 620 621//===----------------------------------------------------------------------===// 622// Pfm Counters 623//===----------------------------------------------------------------------===// 624 625include "PPCPfmCounters.td" 626