Lines Matching refs:ARM
66 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
67 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
68 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
69 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
70 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
71 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
72 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
73 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
76 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
77 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
78 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
79 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
80 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
81 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
82 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
83 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
87 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), in ARMBaseInstrInfo()
168 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress()
178 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg) in convertToThreeAddress()
188 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) in convertToThreeAddress()
202 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress()
210 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) in convertToThreeAddress()
416 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); in InsertBranch()
418 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); in InsertBranch()
525 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) || in DefinesPredicate()
526 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) { in DefinesPredicate()
537 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead()) in isCPSRDefined()
545 case ARM::tADC: // ADC (register) T1 in isEligibleForITBlock()
546 case ARM::tADDi3: // ADD (immediate) T1 in isEligibleForITBlock()
547 case ARM::tADDi8: // ADD (immediate) T2 in isEligibleForITBlock()
548 case ARM::tADDrr: // ADD (register) T1 in isEligibleForITBlock()
549 case ARM::tAND: // AND (register) T1 in isEligibleForITBlock()
550 case ARM::tASRri: // ASR (immediate) T1 in isEligibleForITBlock()
551 case ARM::tASRrr: // ASR (register) T1 in isEligibleForITBlock()
552 case ARM::tBIC: // BIC (register) T1 in isEligibleForITBlock()
553 case ARM::tEOR: // EOR (register) T1 in isEligibleForITBlock()
554 case ARM::tLSLri: // LSL (immediate) T1 in isEligibleForITBlock()
555 case ARM::tLSLrr: // LSL (register) T1 in isEligibleForITBlock()
556 case ARM::tLSRri: // LSR (immediate) T1 in isEligibleForITBlock()
557 case ARM::tLSRrr: // LSR (register) T1 in isEligibleForITBlock()
558 case ARM::tMUL: // MUL T1 in isEligibleForITBlock()
559 case ARM::tMVN: // MVN (register) T1 in isEligibleForITBlock()
560 case ARM::tORR: // ORR (register) T1 in isEligibleForITBlock()
561 case ARM::tROR: // ROR (register) T1 in isEligibleForITBlock()
562 case ARM::tRSB: // RSB (immediate) T1 in isEligibleForITBlock()
563 case ARM::tSBC: // SBC (register) T1 in isEligibleForITBlock()
564 case ARM::tSUBi3: // SUB (immediate) T1 in isEligibleForITBlock()
565 case ARM::tSUBi8: // SUB (immediate) T2 in isEligibleForITBlock()
566 case ARM::tSUBrr: // SUB (register) T1 in isEligibleForITBlock()
601 if (MO.getReg() != ARM::CPSR) in IsCPSRDead()
623 if (MI.getOpcode() == ARM::INLINEASM) in GetInstSizeInBytes()
632 case ARM::MOVi16_ga_pcrel: in GetInstSizeInBytes()
633 case ARM::MOVTi16_ga_pcrel: in GetInstSizeInBytes()
634 case ARM::t2MOVi16_ga_pcrel: in GetInstSizeInBytes()
635 case ARM::t2MOVTi16_ga_pcrel: in GetInstSizeInBytes()
637 case ARM::MOVi32imm: in GetInstSizeInBytes()
638 case ARM::t2MOVi32imm: in GetInstSizeInBytes()
640 case ARM::CONSTPOOL_ENTRY: in GetInstSizeInBytes()
641 case ARM::JUMPTABLE_INSTS: in GetInstSizeInBytes()
642 case ARM::JUMPTABLE_ADDRS: in GetInstSizeInBytes()
643 case ARM::JUMPTABLE_TBB: in GetInstSizeInBytes()
644 case ARM::JUMPTABLE_TBH: in GetInstSizeInBytes()
648 case ARM::Int_eh_sjlj_longjmp: in GetInstSizeInBytes()
650 case ARM::tInt_eh_sjlj_longjmp: in GetInstSizeInBytes()
652 case ARM::tInt_WIN_eh_sjlj_longjmp: in GetInstSizeInBytes()
654 case ARM::Int_eh_sjlj_setjmp: in GetInstSizeInBytes()
655 case ARM::Int_eh_sjlj_setjmp_nofp: in GetInstSizeInBytes()
657 case ARM::tInt_eh_sjlj_setjmp: in GetInstSizeInBytes()
658 case ARM::t2Int_eh_sjlj_setjmp: in GetInstSizeInBytes()
659 case ARM::t2Int_eh_sjlj_setjmp_nofp: in GetInstSizeInBytes()
661 case ARM::SPACE: in GetInstSizeInBytes()
682 ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR) in copyFromCPSR()
683 : ARM::MRS; in copyFromCPSR()
695 MIB.addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc)); in copyFromCPSR()
703 ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR) in copyToCPSR()
704 : ARM::MSR; in copyToCPSR()
717 MIB.addReg(ARM::CPSR, RegState::Implicit | RegState::Define); in copyToCPSR()
724 bool GPRDest = ARM::GPRRegClass.contains(DestReg); in copyPhysReg()
725 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); in copyPhysReg()
728 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) in copyPhysReg()
733 bool SPRDest = ARM::SPRRegClass.contains(DestReg); in copyPhysReg()
734 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); in copyPhysReg()
738 Opc = ARM::VMOVS; in copyPhysReg()
740 Opc = ARM::VMOVRS; in copyPhysReg()
742 Opc = ARM::VMOVSR; in copyPhysReg()
743 else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && !Subtarget.isFPOnlySP()) in copyPhysReg()
744 Opc = ARM::VMOVD; in copyPhysReg()
745 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
746 Opc = ARM::VORRq; in copyPhysReg()
751 if (Opc == ARM::VORRq) in copyPhysReg()
763 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
764 Opc = ARM::VORRq; in copyPhysReg()
765 BeginIdx = ARM::qsub_0; in copyPhysReg()
767 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
768 Opc = ARM::VORRq; in copyPhysReg()
769 BeginIdx = ARM::qsub_0; in copyPhysReg()
772 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
773 Opc = ARM::VMOVD; in copyPhysReg()
774 BeginIdx = ARM::dsub_0; in copyPhysReg()
776 } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
777 Opc = ARM::VMOVD; in copyPhysReg()
778 BeginIdx = ARM::dsub_0; in copyPhysReg()
780 } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
781 Opc = ARM::VMOVD; in copyPhysReg()
782 BeginIdx = ARM::dsub_0; in copyPhysReg()
784 } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
785 Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr; in copyPhysReg()
786 BeginIdx = ARM::gsub_0; in copyPhysReg()
788 } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
789 Opc = ARM::VMOVD; in copyPhysReg()
790 BeginIdx = ARM::dsub_0; in copyPhysReg()
793 } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
794 Opc = ARM::VMOVD; in copyPhysReg()
795 BeginIdx = ARM::dsub_0; in copyPhysReg()
798 } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
799 Opc = ARM::VMOVD; in copyPhysReg()
800 BeginIdx = ARM::dsub_0; in copyPhysReg()
803 } else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.isFPOnlySP()) { in copyPhysReg()
804 Opc = ARM::VMOVS; in copyPhysReg()
805 BeginIdx = ARM::ssub_0; in copyPhysReg()
807 } else if (SrcReg == ARM::CPSR) { in copyPhysReg()
810 } else if (DestReg == ARM::CPSR) { in copyPhysReg()
838 if (Opc == ARM::VORRq) in copyPhysReg()
842 if (Opc == ARM::MOVr) in copyPhysReg()
880 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
881 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12)) in storeRegToStackSlot()
884 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
885 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) in storeRegToStackSlot()
892 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
893 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) in storeRegToStackSlot()
896 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
898 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD)); in storeRegToStackSlot()
899 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
900 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot()
908 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STMIA)) in storeRegToStackSlot()
910 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
911 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot()
917 if (ARM::DPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
920 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64)) in storeRegToStackSlot()
925 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA)) in storeRegToStackSlot()
934 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
937 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo)) in storeRegToStackSlot()
943 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) in storeRegToStackSlot()
946 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
947 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
948 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
954 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
958 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo)) in storeRegToStackSlot()
964 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) in storeRegToStackSlot()
967 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
968 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
969 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
970 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); in storeRegToStackSlot()
976 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
978 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) in storeRegToStackSlot()
981 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
982 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
983 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
984 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); in storeRegToStackSlot()
985 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); in storeRegToStackSlot()
986 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); in storeRegToStackSlot()
987 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); in storeRegToStackSlot()
988 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); in storeRegToStackSlot()
1001 case ARM::STRrs: in isStoreToStackSlot()
1002 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. in isStoreToStackSlot()
1010 case ARM::STRi12: in isStoreToStackSlot()
1011 case ARM::t2STRi12: in isStoreToStackSlot()
1012 case ARM::tSTRspi: in isStoreToStackSlot()
1013 case ARM::VSTRD: in isStoreToStackSlot()
1014 case ARM::VSTRS: in isStoreToStackSlot()
1021 case ARM::VST1q64: in isStoreToStackSlot()
1022 case ARM::VST1d64TPseudo: in isStoreToStackSlot()
1023 case ARM::VST1d64QPseudo: in isStoreToStackSlot()
1029 case ARM::VSTMQIA: in isStoreToStackSlot()
1062 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1063 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) in loadRegFromStackSlot()
1066 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1067 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) in loadRegFromStackSlot()
1073 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1074 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) in loadRegFromStackSlot()
1076 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1080 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD)); in loadRegFromStackSlot()
1081 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1082 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1089 MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA)) in loadRegFromStackSlot()
1091 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1092 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1101 if (ARM::DPairRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1103 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg) in loadRegFromStackSlot()
1107 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) in loadRegFromStackSlot()
1115 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1117 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg) in loadRegFromStackSlot()
1122 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) in loadRegFromStackSlot()
1125 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1126 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1127 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1135 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1137 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) in loadRegFromStackSlot()
1142 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) in loadRegFromStackSlot()
1145 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1146 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1147 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1148 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1156 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1158 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) in loadRegFromStackSlot()
1161 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1162 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1163 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1164 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1165 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1166 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1167 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1168 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1183 case ARM::LDRrs: in isLoadFromStackSlot()
1184 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. in isLoadFromStackSlot()
1192 case ARM::LDRi12: in isLoadFromStackSlot()
1193 case ARM::t2LDRi12: in isLoadFromStackSlot()
1194 case ARM::tLDRspi: in isLoadFromStackSlot()
1195 case ARM::VLDRD: in isLoadFromStackSlot()
1196 case ARM::VLDRS: in isLoadFromStackSlot()
1203 case ARM::VLD1q64: in isLoadFromStackSlot()
1204 case ARM::VLD1d64TPseudo: in isLoadFromStackSlot()
1205 case ARM::VLD1d64QPseudo: in isLoadFromStackSlot()
1211 case ARM::VLDMQIA: in isLoadFromStackSlot()
1240 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA_UPD in expandMEMCPY()
1241 : isThumb1 ? ARM::tLDMIA_UPD in expandMEMCPY()
1242 : ARM::LDMIA_UPD)) in expandMEMCPY()
1245 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA : ARM::LDMIA)); in expandMEMCPY()
1249 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD in expandMEMCPY()
1250 : isThumb1 ? ARM::tSTMIA_UPD in expandMEMCPY()
1251 : ARM::STMIA_UPD)) in expandMEMCPY()
1254 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA)); in expandMEMCPY()
1290 if (MI.getOpcode() == ARM::MEMCPY) { in expandPostRAPseudo()
1306 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS)) in expandPostRAPseudo()
1310 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0, in expandPostRAPseudo()
1311 &ARM::DPRRegClass); in expandPostRAPseudo()
1312 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0, in expandPostRAPseudo()
1313 &ARM::DPRRegClass); in expandPostRAPseudo()
1338 MI.setDesc(get(ARM::VMOVD)); in expandPostRAPseudo()
1419 case ARM::tLDRpci_pic: in reMaterialize()
1420 case ARM::t2LDRpci_pic: { in reMaterialize()
1438 case ARM::tLDRpci_pic: in duplicate()
1439 case ARM::t2LDRpci_pic: { in duplicate()
1454 if (Opcode == ARM::t2LDRpci || in produceSameValue()
1455 Opcode == ARM::t2LDRpci_pic || in produceSameValue()
1456 Opcode == ARM::tLDRpci || in produceSameValue()
1457 Opcode == ARM::tLDRpci_pic || in produceSameValue()
1458 Opcode == ARM::LDRLIT_ga_pcrel || in produceSameValue()
1459 Opcode == ARM::LDRLIT_ga_pcrel_ldr || in produceSameValue()
1460 Opcode == ARM::tLDRLIT_ga_pcrel || in produceSameValue()
1461 Opcode == ARM::MOV_ga_pcrel || in produceSameValue()
1462 Opcode == ARM::MOV_ga_pcrel_ldr || in produceSameValue()
1463 Opcode == ARM::t2MOV_ga_pcrel) { in produceSameValue()
1474 if (Opcode == ARM::LDRLIT_ga_pcrel || in produceSameValue()
1475 Opcode == ARM::LDRLIT_ga_pcrel_ldr || in produceSameValue()
1476 Opcode == ARM::tLDRLIT_ga_pcrel || in produceSameValue()
1477 Opcode == ARM::MOV_ga_pcrel || in produceSameValue()
1478 Opcode == ARM::MOV_ga_pcrel_ldr || in produceSameValue()
1479 Opcode == ARM::t2MOV_ga_pcrel) in produceSameValue()
1501 } else if (Opcode == ARM::PICLDR) { in produceSameValue()
1557 case ARM::LDRi12: in areLoadsFromSameBasePtr()
1558 case ARM::LDRBi12: in areLoadsFromSameBasePtr()
1559 case ARM::LDRD: in areLoadsFromSameBasePtr()
1560 case ARM::LDRH: in areLoadsFromSameBasePtr()
1561 case ARM::LDRSB: in areLoadsFromSameBasePtr()
1562 case ARM::LDRSH: in areLoadsFromSameBasePtr()
1563 case ARM::VLDRD: in areLoadsFromSameBasePtr()
1564 case ARM::VLDRS: in areLoadsFromSameBasePtr()
1565 case ARM::t2LDRi8: in areLoadsFromSameBasePtr()
1566 case ARM::t2LDRBi8: in areLoadsFromSameBasePtr()
1567 case ARM::t2LDRDi8: in areLoadsFromSameBasePtr()
1568 case ARM::t2LDRSHi8: in areLoadsFromSameBasePtr()
1569 case ARM::t2LDRi12: in areLoadsFromSameBasePtr()
1570 case ARM::t2LDRBi12: in areLoadsFromSameBasePtr()
1571 case ARM::t2LDRSHi12: in areLoadsFromSameBasePtr()
1578 case ARM::LDRi12: in areLoadsFromSameBasePtr()
1579 case ARM::LDRBi12: in areLoadsFromSameBasePtr()
1580 case ARM::LDRD: in areLoadsFromSameBasePtr()
1581 case ARM::LDRH: in areLoadsFromSameBasePtr()
1582 case ARM::LDRSB: in areLoadsFromSameBasePtr()
1583 case ARM::LDRSH: in areLoadsFromSameBasePtr()
1584 case ARM::VLDRD: in areLoadsFromSameBasePtr()
1585 case ARM::VLDRS: in areLoadsFromSameBasePtr()
1586 case ARM::t2LDRi8: in areLoadsFromSameBasePtr()
1587 case ARM::t2LDRBi8: in areLoadsFromSameBasePtr()
1588 case ARM::t2LDRSHi8: in areLoadsFromSameBasePtr()
1589 case ARM::t2LDRi12: in areLoadsFromSameBasePtr()
1590 case ARM::t2LDRBi12: in areLoadsFromSameBasePtr()
1591 case ARM::t2LDRSHi12: in areLoadsFromSameBasePtr()
1643 !((Load1->getMachineOpcode() == ARM::t2LDRBi8 && in shouldScheduleLoadsNear()
1644 Load2->getMachineOpcode() == ARM::t2LDRBi12) || in shouldScheduleLoadsNear()
1645 (Load1->getMachineOpcode() == ARM::t2LDRBi12 && in shouldScheduleLoadsNear()
1646 Load2->getMachineOpcode() == ARM::t2LDRBi8))) in shouldScheduleLoadsNear()
1682 if (I != MBB->end() && I->getOpcode() == ARM::t2IT) in isSchedulingBoundary()
1693 if (!MI.isCall() && MI.definesRegister(ARM::SP)) in isSchedulingBoundary()
1713 if (LastMI->getOpcode() == ARM::t2Bcc) { in isProfitableToIfCvt()
1717 if (CmpMI->getOpcode() == ARM::tCMPi8 || in isProfitableToIfCvt()
1718 CmpMI->getOpcode() == ARM::t2CMPri) { in isProfitableToIfCvt()
1790 if (Opc == ARM::B) in getMatchingCondBranchOpcode()
1791 return ARM::Bcc; in getMatchingCondBranchOpcode()
1792 if (Opc == ARM::tB) in getMatchingCondBranchOpcode()
1793 return ARM::tBcc; in getMatchingCondBranchOpcode()
1794 if (Opc == ARM::t2B) in getMatchingCondBranchOpcode()
1795 return ARM::t2Bcc; in getMatchingCondBranchOpcode()
1805 case ARM::MOVCCr: in commuteInstructionImpl()
1806 case ARM::t2MOVCCr: { in commuteInstructionImpl()
1811 if (CC == ARMCC::AL || PredReg != ARM::CPSR) in commuteInstructionImpl()
1868 assert((MI.getOpcode() == ARM::MOVCCr || MI.getOpcode() == ARM::t2MOVCCr) && in analyzeSelect()
1889 assert((MI.getOpcode() == ARM::MOVCCr || MI.getOpcode() == ARM::t2MOVCCr) && in optimizeSelect()
1964 {ARM::ADDSri, ARM::ADDri},
1965 {ARM::ADDSrr, ARM::ADDrr},
1966 {ARM::ADDSrsi, ARM::ADDrsi},
1967 {ARM::ADDSrsr, ARM::ADDrsr},
1969 {ARM::SUBSri, ARM::SUBri},
1970 {ARM::SUBSrr, ARM::SUBrr},
1971 {ARM::SUBSrsi, ARM::SUBrsi},
1972 {ARM::SUBSrsr, ARM::SUBrsr},
1974 {ARM::RSBSri, ARM::RSBri},
1975 {ARM::RSBSrsi, ARM::RSBrsi},
1976 {ARM::RSBSrsr, ARM::RSBrsr},
1978 {ARM::t2ADDSri, ARM::t2ADDri},
1979 {ARM::t2ADDSrr, ARM::t2ADDrr},
1980 {ARM::t2ADDSrs, ARM::t2ADDrs},
1982 {ARM::t2SUBSri, ARM::t2SUBri},
1983 {ARM::t2SUBSrr, ARM::t2SUBrr},
1984 {ARM::t2SUBSrs, ARM::t2SUBrs},
1986 {ARM::t2RSBSri, ARM::t2RSBri},
1987 {ARM::t2RSBSrs, ARM::t2RSBrs},
2005 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg) in emitARMRegPlusImmediate()
2026 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; in emitARMRegPlusImmediate()
2051 bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD || in tryFoldSPUpdateIntoPushPop()
2052 MI->getOpcode() == ARM::VLDMDIA_UPD; in tryFoldSPUpdateIntoPushPop()
2053 bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH || in tryFoldSPUpdateIntoPushPop()
2054 MI->getOpcode() == ARM::tPOP || in tryFoldSPUpdateIntoPushPop()
2055 MI->getOpcode() == ARM::tPOP_RET; in tryFoldSPUpdateIntoPushPop()
2057 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP && in tryFoldSPUpdateIntoPushPop()
2058 MI->getOperand(1).getReg() == ARM::SP)) && in tryFoldSPUpdateIntoPushPop()
2075 RD0Reg = ARM::D0; in tryFoldSPUpdateIntoPushPop()
2078 RD0Reg = ARM::R0; in tryFoldSPUpdateIntoPushPop()
2152 if (Opcode == ARM::INLINEASM) in rewriteARMFrameIndex()
2155 if (Opcode == ARM::ADDri) { in rewriteARMFrameIndex()
2159 MI.setDesc(TII.get(ARM::MOVr)); in rewriteARMFrameIndex()
2167 MI.setDesc(TII.get(ARM::SUBri)); in rewriteARMFrameIndex()
2292 case ARM::CMPri: in analyzeCompare()
2293 case ARM::t2CMPri: in analyzeCompare()
2299 case ARM::CMPrr: in analyzeCompare()
2300 case ARM::t2CMPrr: in analyzeCompare()
2306 case ARM::TSTri: in analyzeCompare()
2307 case ARM::t2TSTri: in analyzeCompare()
2325 case ARM::ANDri: in isSuitableForMask()
2326 case ARM::t2ANDri: in isSuitableForMask()
2364 if ((CmpI->getOpcode() == ARM::CMPrr || in isRedundantFlagInstr()
2365 CmpI->getOpcode() == ARM::t2CMPrr) && in isRedundantFlagInstr()
2366 (OI->getOpcode() == ARM::SUBrr || in isRedundantFlagInstr()
2367 OI->getOpcode() == ARM::t2SUBrr) && in isRedundantFlagInstr()
2374 if ((CmpI->getOpcode() == ARM::CMPri || in isRedundantFlagInstr()
2375 CmpI->getOpcode() == ARM::t2CMPri) && in isRedundantFlagInstr()
2376 (OI->getOpcode() == ARM::SUBri || in isRedundantFlagInstr()
2377 OI->getOpcode() == ARM::t2SUBri) && in isRedundantFlagInstr()
2438 if (CmpInstr.getOpcode() == ARM::CMPri || in optimizeCompareInstr()
2439 CmpInstr.getOpcode() == ARM::t2CMPri) in optimizeCompareInstr()
2452 if (Instr.modifiesRegister(ARM::CPSR, TRI) || in optimizeCompareInstr()
2453 Instr.readsRegister(ARM::CPSR, TRI)) in optimizeCompareInstr()
2482 case ARM::RSBrr: in optimizeCompareInstr()
2483 case ARM::RSBri: in optimizeCompareInstr()
2484 case ARM::RSCrr: in optimizeCompareInstr()
2485 case ARM::RSCri: in optimizeCompareInstr()
2486 case ARM::ADDrr: in optimizeCompareInstr()
2487 case ARM::ADDri: in optimizeCompareInstr()
2488 case ARM::ADCrr: in optimizeCompareInstr()
2489 case ARM::ADCri: in optimizeCompareInstr()
2490 case ARM::SUBrr: in optimizeCompareInstr()
2491 case ARM::SUBri: in optimizeCompareInstr()
2492 case ARM::SBCrr: in optimizeCompareInstr()
2493 case ARM::SBCri: in optimizeCompareInstr()
2494 case ARM::t2RSBri: in optimizeCompareInstr()
2495 case ARM::t2ADDrr: in optimizeCompareInstr()
2496 case ARM::t2ADDri: in optimizeCompareInstr()
2497 case ARM::t2ADCrr: in optimizeCompareInstr()
2498 case ARM::t2ADCri: in optimizeCompareInstr()
2499 case ARM::t2SUBrr: in optimizeCompareInstr()
2500 case ARM::t2SUBri: in optimizeCompareInstr()
2501 case ARM::t2SBCrr: in optimizeCompareInstr()
2502 case ARM::t2SBCri: in optimizeCompareInstr()
2503 case ARM::ANDrr: in optimizeCompareInstr()
2504 case ARM::ANDri: in optimizeCompareInstr()
2505 case ARM::t2ANDrr: in optimizeCompareInstr()
2506 case ARM::t2ANDri: in optimizeCompareInstr()
2507 case ARM::ORRrr: in optimizeCompareInstr()
2508 case ARM::ORRri: in optimizeCompareInstr()
2509 case ARM::t2ORRrr: in optimizeCompareInstr()
2510 case ARM::t2ORRri: in optimizeCompareInstr()
2511 case ARM::EORrr: in optimizeCompareInstr()
2512 case ARM::EORri: in optimizeCompareInstr()
2513 case ARM::t2EORrr: in optimizeCompareInstr()
2514 case ARM::t2EORri: { in optimizeCompareInstr()
2531 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) { in optimizeCompareInstr()
2535 if (!MO.isReg() || MO.getReg() != ARM::CPSR) in optimizeCompareInstr()
2549 case ARM::VSELEQD: in optimizeCompareInstr()
2550 case ARM::VSELEQS: in optimizeCompareInstr()
2553 case ARM::VSELGTD: in optimizeCompareInstr()
2554 case ARM::VSELGTS: in optimizeCompareInstr()
2557 case ARM::VSELGED: in optimizeCompareInstr()
2558 case ARM::VSELGES: in optimizeCompareInstr()
2561 case ARM::VSELVSS: in optimizeCompareInstr()
2562 case ARM::VSELVSD: in optimizeCompareInstr()
2617 if ((*SI)->isLiveIn(ARM::CPSR)) in optimizeCompareInstr()
2622 MI->getOperand(5).setReg(ARM::CPSR); in optimizeCompareInstr()
2644 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm) in FoldImmediate()
2657 if (MO.getReg() == ARM::CPSR && !MO.isDead()) in FoldImmediate()
2666 if (UseMI.getOperand(NumOps - 1).getReg() == ARM::CPSR) in FoldImmediate()
2679 case ARM::SUBrr: in FoldImmediate()
2680 case ARM::ADDrr: in FoldImmediate()
2681 case ARM::ORRrr: in FoldImmediate()
2682 case ARM::EORrr: in FoldImmediate()
2683 case ARM::t2SUBrr: in FoldImmediate()
2684 case ARM::t2ADDrr: in FoldImmediate()
2685 case ARM::t2ORRrr: in FoldImmediate()
2686 case ARM::t2EORrr: { in FoldImmediate()
2690 case ARM::ADDrr: in FoldImmediate()
2691 case ARM::SUBrr: { in FoldImmediate()
2692 if (UseOpc == ARM::SUBrr && Commute) in FoldImmediate()
2698 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::ADDri : ARM::SUBri; in FoldImmediate()
2701 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::SUBri : ARM::ADDri; in FoldImmediate()
2708 case ARM::ORRrr: in FoldImmediate()
2709 case ARM::EORrr: { in FoldImmediate()
2716 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break; in FoldImmediate()
2717 case ARM::EORrr: NewUseOpc = ARM::EORri; break; in FoldImmediate()
2721 case ARM::t2ADDrr: in FoldImmediate()
2722 case ARM::t2SUBrr: { in FoldImmediate()
2723 if (UseOpc == ARM::t2SUBrr && Commute) in FoldImmediate()
2729 NewUseOpc = UseOpc == ARM::t2ADDrr ? ARM::t2ADDri : ARM::t2SUBri; in FoldImmediate()
2732 NewUseOpc = UseOpc == ARM::t2ADDrr ? ARM::t2SUBri : ARM::t2ADDri; in FoldImmediate()
2739 case ARM::t2ORRrr: in FoldImmediate()
2740 case ARM::t2EORrr: { in FoldImmediate()
2747 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break; in FoldImmediate()
2748 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break; in FoldImmediate()
2783 case ARM::LDRrs: in getNumMicroOpsSwiftLdSt()
2784 case ARM::LDRBrs: in getNumMicroOpsSwiftLdSt()
2785 case ARM::STRrs: in getNumMicroOpsSwiftLdSt()
2786 case ARM::STRBrs: { in getNumMicroOpsSwiftLdSt()
2798 case ARM::LDRH: in getNumMicroOpsSwiftLdSt()
2799 case ARM::STRH: { in getNumMicroOpsSwiftLdSt()
2814 case ARM::LDRSB: in getNumMicroOpsSwiftLdSt()
2815 case ARM::LDRSH: in getNumMicroOpsSwiftLdSt()
2818 case ARM::LDRSB_POST: in getNumMicroOpsSwiftLdSt()
2819 case ARM::LDRSH_POST: { in getNumMicroOpsSwiftLdSt()
2825 case ARM::LDR_PRE_REG: in getNumMicroOpsSwiftLdSt()
2826 case ARM::LDRB_PRE_REG: { in getNumMicroOpsSwiftLdSt()
2842 case ARM::STR_PRE_REG: in getNumMicroOpsSwiftLdSt()
2843 case ARM::STRB_PRE_REG: { in getNumMicroOpsSwiftLdSt()
2855 case ARM::LDRH_PRE: in getNumMicroOpsSwiftLdSt()
2856 case ARM::STRH_PRE: { in getNumMicroOpsSwiftLdSt()
2866 case ARM::LDR_POST_REG: in getNumMicroOpsSwiftLdSt()
2867 case ARM::LDRB_POST_REG: in getNumMicroOpsSwiftLdSt()
2868 case ARM::LDRH_POST: { in getNumMicroOpsSwiftLdSt()
2874 case ARM::LDR_PRE_IMM: in getNumMicroOpsSwiftLdSt()
2875 case ARM::LDRB_PRE_IMM: in getNumMicroOpsSwiftLdSt()
2876 case ARM::LDR_POST_IMM: in getNumMicroOpsSwiftLdSt()
2877 case ARM::LDRB_POST_IMM: in getNumMicroOpsSwiftLdSt()
2878 case ARM::STRB_POST_IMM: in getNumMicroOpsSwiftLdSt()
2879 case ARM::STRB_POST_REG: in getNumMicroOpsSwiftLdSt()
2880 case ARM::STRB_PRE_IMM: in getNumMicroOpsSwiftLdSt()
2881 case ARM::STRH_POST: in getNumMicroOpsSwiftLdSt()
2882 case ARM::STR_POST_IMM: in getNumMicroOpsSwiftLdSt()
2883 case ARM::STR_POST_REG: in getNumMicroOpsSwiftLdSt()
2884 case ARM::STR_PRE_IMM: in getNumMicroOpsSwiftLdSt()
2887 case ARM::LDRSB_PRE: in getNumMicroOpsSwiftLdSt()
2888 case ARM::LDRSH_PRE: { in getNumMicroOpsSwiftLdSt()
2906 case ARM::LDRD: { in getNumMicroOpsSwiftLdSt()
2916 case ARM::STRD: { in getNumMicroOpsSwiftLdSt()
2924 case ARM::LDRD_POST: in getNumMicroOpsSwiftLdSt()
2925 case ARM::t2LDRD_POST: in getNumMicroOpsSwiftLdSt()
2928 case ARM::STRD_POST: in getNumMicroOpsSwiftLdSt()
2929 case ARM::t2STRD_POST: in getNumMicroOpsSwiftLdSt()
2932 case ARM::LDRD_PRE: { in getNumMicroOpsSwiftLdSt()
2942 case ARM::t2LDRD_PRE: { in getNumMicroOpsSwiftLdSt()
2948 case ARM::STRD_PRE: { in getNumMicroOpsSwiftLdSt()
2956 case ARM::t2STRD_PRE: in getNumMicroOpsSwiftLdSt()
2959 case ARM::t2LDR_POST: in getNumMicroOpsSwiftLdSt()
2960 case ARM::t2LDRB_POST: in getNumMicroOpsSwiftLdSt()
2961 case ARM::t2LDRB_PRE: in getNumMicroOpsSwiftLdSt()
2962 case ARM::t2LDRSBi12: in getNumMicroOpsSwiftLdSt()
2963 case ARM::t2LDRSBi8: in getNumMicroOpsSwiftLdSt()
2964 case ARM::t2LDRSBpci: in getNumMicroOpsSwiftLdSt()
2965 case ARM::t2LDRSBs: in getNumMicroOpsSwiftLdSt()
2966 case ARM::t2LDRH_POST: in getNumMicroOpsSwiftLdSt()
2967 case ARM::t2LDRH_PRE: in getNumMicroOpsSwiftLdSt()
2968 case ARM::t2LDRSBT: in getNumMicroOpsSwiftLdSt()
2969 case ARM::t2LDRSB_POST: in getNumMicroOpsSwiftLdSt()
2970 case ARM::t2LDRSB_PRE: in getNumMicroOpsSwiftLdSt()
2971 case ARM::t2LDRSH_POST: in getNumMicroOpsSwiftLdSt()
2972 case ARM::t2LDRSH_PRE: in getNumMicroOpsSwiftLdSt()
2973 case ARM::t2LDRSHi12: in getNumMicroOpsSwiftLdSt()
2974 case ARM::t2LDRSHi8: in getNumMicroOpsSwiftLdSt()
2975 case ARM::t2LDRSHpci: in getNumMicroOpsSwiftLdSt()
2976 case ARM::t2LDRSHs: in getNumMicroOpsSwiftLdSt()
2979 case ARM::t2LDRDi8: { in getNumMicroOpsSwiftLdSt()
2985 case ARM::t2STRB_POST: in getNumMicroOpsSwiftLdSt()
2986 case ARM::t2STRB_PRE: in getNumMicroOpsSwiftLdSt()
2987 case ARM::t2STRBs: in getNumMicroOpsSwiftLdSt()
2988 case ARM::t2STRDi8: in getNumMicroOpsSwiftLdSt()
2989 case ARM::t2STRH_POST: in getNumMicroOpsSwiftLdSt()
2990 case ARM::t2STRH_PRE: in getNumMicroOpsSwiftLdSt()
2991 case ARM::t2STRHs: in getNumMicroOpsSwiftLdSt()
2992 case ARM::t2STR_POST: in getNumMicroOpsSwiftLdSt()
2993 case ARM::t2STR_PRE: in getNumMicroOpsSwiftLdSt()
2994 case ARM::t2STRs: in getNumMicroOpsSwiftLdSt()
3037 case ARM::VLDMDIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3038 case ARM::VLDMDDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3039 case ARM::VLDMSIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3040 case ARM::VLDMSDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3041 case ARM::VSTMDIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3042 case ARM::VSTMDDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3043 case ARM::VSTMSIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3044 case ARM::VSTMSDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3045 case ARM::LDMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3046 case ARM::LDMDA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3047 case ARM::LDMDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3048 case ARM::LDMIB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3049 case ARM::STMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3050 case ARM::STMDA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3051 case ARM::STMDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3052 case ARM::STMIB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3053 case ARM::tLDMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3054 case ARM::tSTMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3055 case ARM::t2LDMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3056 case ARM::t2LDMDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3057 case ARM::t2STMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3058 case ARM::t2STMDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3061 case ARM::LDMIA_RET: in getNumMicroOpsSingleIssuePlusExtras()
3062 case ARM::tPOP_RET: in getNumMicroOpsSingleIssuePlusExtras()
3063 case ARM::t2LDMIA_RET: in getNumMicroOpsSingleIssuePlusExtras()
3089 case ARM::VLDMQIA: in getNumMicroOps()
3090 case ARM::VSTMQIA: in getNumMicroOps()
3103 case ARM::VLDMDIA: in getNumMicroOps()
3104 case ARM::VLDMDIA_UPD: in getNumMicroOps()
3105 case ARM::VLDMDDB_UPD: in getNumMicroOps()
3106 case ARM::VLDMSIA: in getNumMicroOps()
3107 case ARM::VLDMSIA_UPD: in getNumMicroOps()
3108 case ARM::VLDMSDB_UPD: in getNumMicroOps()
3109 case ARM::VSTMDIA: in getNumMicroOps()
3110 case ARM::VSTMDIA_UPD: in getNumMicroOps()
3111 case ARM::VSTMDDB_UPD: in getNumMicroOps()
3112 case ARM::VSTMSIA: in getNumMicroOps()
3113 case ARM::VSTMSIA_UPD: in getNumMicroOps()
3114 case ARM::VSTMSDB_UPD: { in getNumMicroOps()
3119 case ARM::LDMIA_RET: in getNumMicroOps()
3120 case ARM::LDMIA: in getNumMicroOps()
3121 case ARM::LDMDA: in getNumMicroOps()
3122 case ARM::LDMDB: in getNumMicroOps()
3123 case ARM::LDMIB: in getNumMicroOps()
3124 case ARM::LDMIA_UPD: in getNumMicroOps()
3125 case ARM::LDMDA_UPD: in getNumMicroOps()
3126 case ARM::LDMDB_UPD: in getNumMicroOps()
3127 case ARM::LDMIB_UPD: in getNumMicroOps()
3128 case ARM::STMIA: in getNumMicroOps()
3129 case ARM::STMDA: in getNumMicroOps()
3130 case ARM::STMDB: in getNumMicroOps()
3131 case ARM::STMIB: in getNumMicroOps()
3132 case ARM::STMIA_UPD: in getNumMicroOps()
3133 case ARM::STMDA_UPD: in getNumMicroOps()
3134 case ARM::STMDB_UPD: in getNumMicroOps()
3135 case ARM::STMIB_UPD: in getNumMicroOps()
3136 case ARM::tLDMIA: in getNumMicroOps()
3137 case ARM::tLDMIA_UPD: in getNumMicroOps()
3138 case ARM::tSTMIA_UPD: in getNumMicroOps()
3139 case ARM::tPOP_RET: in getNumMicroOps()
3140 case ARM::tPOP: in getNumMicroOps()
3141 case ARM::tPUSH: in getNumMicroOps()
3142 case ARM::t2LDMIA_RET: in getNumMicroOps()
3143 case ARM::t2LDMIA: in getNumMicroOps()
3144 case ARM::t2LDMDB: in getNumMicroOps()
3145 case ARM::t2LDMIA_UPD: in getNumMicroOps()
3146 case ARM::t2LDMDB_UPD: in getNumMicroOps()
3147 case ARM::t2STMIA: in getNumMicroOps()
3148 case ARM::t2STMDB: in getNumMicroOps()
3149 case ARM::t2STMIA_UPD: in getNumMicroOps()
3150 case ARM::t2STMDB_UPD: { in getNumMicroOps()
3205 case ARM::VLDMSIA: in getVLDMDefCycle()
3206 case ARM::VLDMSIA_UPD: in getVLDMDefCycle()
3207 case ARM::VLDMSDB_UPD: in getVLDMDefCycle()
3280 case ARM::VSTMSIA: in getVSTMUseCycle()
3281 case ARM::VSTMSIA_UPD: in getVSTMUseCycle()
3282 case ARM::VSTMSDB_UPD: in getVSTMUseCycle()
3350 case ARM::VLDMDIA: in getOperandLatency()
3351 case ARM::VLDMDIA_UPD: in getOperandLatency()
3352 case ARM::VLDMDDB_UPD: in getOperandLatency()
3353 case ARM::VLDMSIA: in getOperandLatency()
3354 case ARM::VLDMSIA_UPD: in getOperandLatency()
3355 case ARM::VLDMSDB_UPD: in getOperandLatency()
3359 case ARM::LDMIA_RET: in getOperandLatency()
3360 case ARM::LDMIA: in getOperandLatency()
3361 case ARM::LDMDA: in getOperandLatency()
3362 case ARM::LDMDB: in getOperandLatency()
3363 case ARM::LDMIB: in getOperandLatency()
3364 case ARM::LDMIA_UPD: in getOperandLatency()
3365 case ARM::LDMDA_UPD: in getOperandLatency()
3366 case ARM::LDMDB_UPD: in getOperandLatency()
3367 case ARM::LDMIB_UPD: in getOperandLatency()
3368 case ARM::tLDMIA: in getOperandLatency()
3369 case ARM::tLDMIA_UPD: in getOperandLatency()
3370 case ARM::tPUSH: in getOperandLatency()
3371 case ARM::t2LDMIA_RET: in getOperandLatency()
3372 case ARM::t2LDMIA: in getOperandLatency()
3373 case ARM::t2LDMDB: in getOperandLatency()
3374 case ARM::t2LDMIA_UPD: in getOperandLatency()
3375 case ARM::t2LDMDB_UPD: in getOperandLatency()
3391 case ARM::VSTMDIA: in getOperandLatency()
3392 case ARM::VSTMDIA_UPD: in getOperandLatency()
3393 case ARM::VSTMDDB_UPD: in getOperandLatency()
3394 case ARM::VSTMSIA: in getOperandLatency()
3395 case ARM::VSTMSIA_UPD: in getOperandLatency()
3396 case ARM::VSTMSDB_UPD: in getOperandLatency()
3400 case ARM::STMIA: in getOperandLatency()
3401 case ARM::STMDA: in getOperandLatency()
3402 case ARM::STMDB: in getOperandLatency()
3403 case ARM::STMIB: in getOperandLatency()
3404 case ARM::STMIA_UPD: in getOperandLatency()
3405 case ARM::STMDA_UPD: in getOperandLatency()
3406 case ARM::STMDB_UPD: in getOperandLatency()
3407 case ARM::STMIB_UPD: in getOperandLatency()
3408 case ARM::tSTMIA_UPD: in getOperandLatency()
3409 case ARM::tPOP_RET: in getOperandLatency()
3410 case ARM::tPOP: in getOperandLatency()
3411 case ARM::t2STMIA: in getOperandLatency()
3412 case ARM::t2STMDB: in getOperandLatency()
3413 case ARM::t2STMIA_UPD: in getOperandLatency()
3414 case ARM::t2STMDB_UPD: in getOperandLatency()
3478 if (II->getOpcode() != ARM::t2IT) in getBundledUseMI()
3504 case ARM::LDRrs: in adjustDefLatency()
3505 case ARM::LDRBrs: { in adjustDefLatency()
3513 case ARM::t2LDRs: in adjustDefLatency()
3514 case ARM::t2LDRBs: in adjustDefLatency()
3515 case ARM::t2LDRHs: in adjustDefLatency()
3516 case ARM::t2LDRSHs: { in adjustDefLatency()
3529 case ARM::LDRrs: in adjustDefLatency()
3530 case ARM::LDRBrs: { in adjustDefLatency()
3544 case ARM::t2LDRs: in adjustDefLatency()
3545 case ARM::t2LDRBs: in adjustDefLatency()
3546 case ARM::t2LDRHs: in adjustDefLatency()
3547 case ARM::t2LDRSHs: { in adjustDefLatency()
3560 case ARM::VLD1q8: in adjustDefLatency()
3561 case ARM::VLD1q16: in adjustDefLatency()
3562 case ARM::VLD1q32: in adjustDefLatency()
3563 case ARM::VLD1q64: in adjustDefLatency()
3564 case ARM::VLD1q8wb_fixed: in adjustDefLatency()
3565 case ARM::VLD1q16wb_fixed: in adjustDefLatency()
3566 case ARM::VLD1q32wb_fixed: in adjustDefLatency()
3567 case ARM::VLD1q64wb_fixed: in adjustDefLatency()
3568 case ARM::VLD1q8wb_register: in adjustDefLatency()
3569 case ARM::VLD1q16wb_register: in adjustDefLatency()
3570 case ARM::VLD1q32wb_register: in adjustDefLatency()
3571 case ARM::VLD1q64wb_register: in adjustDefLatency()
3572 case ARM::VLD2d8: in adjustDefLatency()
3573 case ARM::VLD2d16: in adjustDefLatency()
3574 case ARM::VLD2d32: in adjustDefLatency()
3575 case ARM::VLD2q8: in adjustDefLatency()
3576 case ARM::VLD2q16: in adjustDefLatency()
3577 case ARM::VLD2q32: in adjustDefLatency()
3578 case ARM::VLD2d8wb_fixed: in adjustDefLatency()
3579 case ARM::VLD2d16wb_fixed: in adjustDefLatency()
3580 case ARM::VLD2d32wb_fixed: in adjustDefLatency()
3581 case ARM::VLD2q8wb_fixed: in adjustDefLatency()
3582 case ARM::VLD2q16wb_fixed: in adjustDefLatency()
3583 case ARM::VLD2q32wb_fixed: in adjustDefLatency()
3584 case ARM::VLD2d8wb_register: in adjustDefLatency()
3585 case ARM::VLD2d16wb_register: in adjustDefLatency()
3586 case ARM::VLD2d32wb_register: in adjustDefLatency()
3587 case ARM::VLD2q8wb_register: in adjustDefLatency()
3588 case ARM::VLD2q16wb_register: in adjustDefLatency()
3589 case ARM::VLD2q32wb_register: in adjustDefLatency()
3590 case ARM::VLD3d8: in adjustDefLatency()
3591 case ARM::VLD3d16: in adjustDefLatency()
3592 case ARM::VLD3d32: in adjustDefLatency()
3593 case ARM::VLD1d64T: in adjustDefLatency()
3594 case ARM::VLD3d8_UPD: in adjustDefLatency()
3595 case ARM::VLD3d16_UPD: in adjustDefLatency()
3596 case ARM::VLD3d32_UPD: in adjustDefLatency()
3597 case ARM::VLD1d64Twb_fixed: in adjustDefLatency()
3598 case ARM::VLD1d64Twb_register: in adjustDefLatency()
3599 case ARM::VLD3q8_UPD: in adjustDefLatency()
3600 case ARM::VLD3q16_UPD: in adjustDefLatency()
3601 case ARM::VLD3q32_UPD: in adjustDefLatency()
3602 case ARM::VLD4d8: in adjustDefLatency()
3603 case ARM::VLD4d16: in adjustDefLatency()
3604 case ARM::VLD4d32: in adjustDefLatency()
3605 case ARM::VLD1d64Q: in adjustDefLatency()
3606 case ARM::VLD4d8_UPD: in adjustDefLatency()
3607 case ARM::VLD4d16_UPD: in adjustDefLatency()
3608 case ARM::VLD4d32_UPD: in adjustDefLatency()
3609 case ARM::VLD1d64Qwb_fixed: in adjustDefLatency()
3610 case ARM::VLD1d64Qwb_register: in adjustDefLatency()
3611 case ARM::VLD4q8_UPD: in adjustDefLatency()
3612 case ARM::VLD4q16_UPD: in adjustDefLatency()
3613 case ARM::VLD4q32_UPD: in adjustDefLatency()
3614 case ARM::VLD1DUPq8: in adjustDefLatency()
3615 case ARM::VLD1DUPq16: in adjustDefLatency()
3616 case ARM::VLD1DUPq32: in adjustDefLatency()
3617 case ARM::VLD1DUPq8wb_fixed: in adjustDefLatency()
3618 case ARM::VLD1DUPq16wb_fixed: in adjustDefLatency()
3619 case ARM::VLD1DUPq32wb_fixed: in adjustDefLatency()
3620 case ARM::VLD1DUPq8wb_register: in adjustDefLatency()
3621 case ARM::VLD1DUPq16wb_register: in adjustDefLatency()
3622 case ARM::VLD1DUPq32wb_register: in adjustDefLatency()
3623 case ARM::VLD2DUPd8: in adjustDefLatency()
3624 case ARM::VLD2DUPd16: in adjustDefLatency()
3625 case ARM::VLD2DUPd32: in adjustDefLatency()
3626 case ARM::VLD2DUPd8wb_fixed: in adjustDefLatency()
3627 case ARM::VLD2DUPd16wb_fixed: in adjustDefLatency()
3628 case ARM::VLD2DUPd32wb_fixed: in adjustDefLatency()
3629 case ARM::VLD2DUPd8wb_register: in adjustDefLatency()
3630 case ARM::VLD2DUPd16wb_register: in adjustDefLatency()
3631 case ARM::VLD2DUPd32wb_register: in adjustDefLatency()
3632 case ARM::VLD4DUPd8: in adjustDefLatency()
3633 case ARM::VLD4DUPd16: in adjustDefLatency()
3634 case ARM::VLD4DUPd32: in adjustDefLatency()
3635 case ARM::VLD4DUPd8_UPD: in adjustDefLatency()
3636 case ARM::VLD4DUPd16_UPD: in adjustDefLatency()
3637 case ARM::VLD4DUPd32_UPD: in adjustDefLatency()
3638 case ARM::VLD1LNd8: in adjustDefLatency()
3639 case ARM::VLD1LNd16: in adjustDefLatency()
3640 case ARM::VLD1LNd32: in adjustDefLatency()
3641 case ARM::VLD1LNd8_UPD: in adjustDefLatency()
3642 case ARM::VLD1LNd16_UPD: in adjustDefLatency()
3643 case ARM::VLD1LNd32_UPD: in adjustDefLatency()
3644 case ARM::VLD2LNd8: in adjustDefLatency()
3645 case ARM::VLD2LNd16: in adjustDefLatency()
3646 case ARM::VLD2LNd32: in adjustDefLatency()
3647 case ARM::VLD2LNq16: in adjustDefLatency()
3648 case ARM::VLD2LNq32: in adjustDefLatency()
3649 case ARM::VLD2LNd8_UPD: in adjustDefLatency()
3650 case ARM::VLD2LNd16_UPD: in adjustDefLatency()
3651 case ARM::VLD2LNd32_UPD: in adjustDefLatency()
3652 case ARM::VLD2LNq16_UPD: in adjustDefLatency()
3653 case ARM::VLD2LNq32_UPD: in adjustDefLatency()
3654 case ARM::VLD4LNd8: in adjustDefLatency()
3655 case ARM::VLD4LNd16: in adjustDefLatency()
3656 case ARM::VLD4LNd32: in adjustDefLatency()
3657 case ARM::VLD4LNq16: in adjustDefLatency()
3658 case ARM::VLD4LNq32: in adjustDefLatency()
3659 case ARM::VLD4LNd8_UPD: in adjustDefLatency()
3660 case ARM::VLD4LNd16_UPD: in adjustDefLatency()
3661 case ARM::VLD4LNd32_UPD: in adjustDefLatency()
3662 case ARM::VLD4LNq16_UPD: in adjustDefLatency()
3663 case ARM::VLD4LNq32_UPD: in adjustDefLatency()
3714 if (Reg == ARM::CPSR) { in getOperandLatencyImpl()
3715 if (DefMI.getOpcode() == ARM::FMSTAT) { in getOperandLatencyImpl()
3808 case ARM::LDRrs: in getOperandLatency()
3809 case ARM::LDRBrs: { in getOperandLatency()
3818 case ARM::t2LDRs: in getOperandLatency()
3819 case ARM::t2LDRBs: in getOperandLatency()
3820 case ARM::t2LDRHs: in getOperandLatency()
3821 case ARM::t2LDRSHs: { in getOperandLatency()
3835 case ARM::LDRrs: in getOperandLatency()
3836 case ARM::LDRBrs: { in getOperandLatency()
3848 case ARM::t2LDRs: in getOperandLatency()
3849 case ARM::t2LDRBs: in getOperandLatency()
3850 case ARM::t2LDRHs: in getOperandLatency()
3851 case ARM::t2LDRSHs: { in getOperandLatency()
3862 case ARM::VLD1q8: in getOperandLatency()
3863 case ARM::VLD1q16: in getOperandLatency()
3864 case ARM::VLD1q32: in getOperandLatency()
3865 case ARM::VLD1q64: in getOperandLatency()
3866 case ARM::VLD1q8wb_register: in getOperandLatency()
3867 case ARM::VLD1q16wb_register: in getOperandLatency()
3868 case ARM::VLD1q32wb_register: in getOperandLatency()
3869 case ARM::VLD1q64wb_register: in getOperandLatency()
3870 case ARM::VLD1q8wb_fixed: in getOperandLatency()
3871 case ARM::VLD1q16wb_fixed: in getOperandLatency()
3872 case ARM::VLD1q32wb_fixed: in getOperandLatency()
3873 case ARM::VLD1q64wb_fixed: in getOperandLatency()
3874 case ARM::VLD2d8: in getOperandLatency()
3875 case ARM::VLD2d16: in getOperandLatency()
3876 case ARM::VLD2d32: in getOperandLatency()
3877 case ARM::VLD2q8Pseudo: in getOperandLatency()
3878 case ARM::VLD2q16Pseudo: in getOperandLatency()
3879 case ARM::VLD2q32Pseudo: in getOperandLatency()
3880 case ARM::VLD2d8wb_fixed: in getOperandLatency()
3881 case ARM::VLD2d16wb_fixed: in getOperandLatency()
3882 case ARM::VLD2d32wb_fixed: in getOperandLatency()
3883 case ARM::VLD2q8PseudoWB_fixed: in getOperandLatency()
3884 case ARM::VLD2q16PseudoWB_fixed: in getOperandLatency()
3885 case ARM::VLD2q32PseudoWB_fixed: in getOperandLatency()
3886 case ARM::VLD2d8wb_register: in getOperandLatency()
3887 case ARM::VLD2d16wb_register: in getOperandLatency()
3888 case ARM::VLD2d32wb_register: in getOperandLatency()
3889 case ARM::VLD2q8PseudoWB_register: in getOperandLatency()
3890 case ARM::VLD2q16PseudoWB_register: in getOperandLatency()
3891 case ARM::VLD2q32PseudoWB_register: in getOperandLatency()
3892 case ARM::VLD3d8Pseudo: in getOperandLatency()
3893 case ARM::VLD3d16Pseudo: in getOperandLatency()
3894 case ARM::VLD3d32Pseudo: in getOperandLatency()
3895 case ARM::VLD1d64TPseudo: in getOperandLatency()
3896 case ARM::VLD1d64TPseudoWB_fixed: in getOperandLatency()
3897 case ARM::VLD3d8Pseudo_UPD: in getOperandLatency()
3898 case ARM::VLD3d16Pseudo_UPD: in getOperandLatency()
3899 case ARM::VLD3d32Pseudo_UPD: in getOperandLatency()
3900 case ARM::VLD3q8Pseudo_UPD: in getOperandLatency()
3901 case ARM::VLD3q16Pseudo_UPD: in getOperandLatency()
3902 case ARM::VLD3q32Pseudo_UPD: in getOperandLatency()
3903 case ARM::VLD3q8oddPseudo: in getOperandLatency()
3904 case ARM::VLD3q16oddPseudo: in getOperandLatency()
3905 case ARM::VLD3q32oddPseudo: in getOperandLatency()
3906 case ARM::VLD3q8oddPseudo_UPD: in getOperandLatency()
3907 case ARM::VLD3q16oddPseudo_UPD: in getOperandLatency()
3908 case ARM::VLD3q32oddPseudo_UPD: in getOperandLatency()
3909 case ARM::VLD4d8Pseudo: in getOperandLatency()
3910 case ARM::VLD4d16Pseudo: in getOperandLatency()
3911 case ARM::VLD4d32Pseudo: in getOperandLatency()
3912 case ARM::VLD1d64QPseudo: in getOperandLatency()
3913 case ARM::VLD1d64QPseudoWB_fixed: in getOperandLatency()
3914 case ARM::VLD4d8Pseudo_UPD: in getOperandLatency()
3915 case ARM::VLD4d16Pseudo_UPD: in getOperandLatency()
3916 case ARM::VLD4d32Pseudo_UPD: in getOperandLatency()
3917 case ARM::VLD4q8Pseudo_UPD: in getOperandLatency()
3918 case ARM::VLD4q16Pseudo_UPD: in getOperandLatency()
3919 case ARM::VLD4q32Pseudo_UPD: in getOperandLatency()
3920 case ARM::VLD4q8oddPseudo: in getOperandLatency()
3921 case ARM::VLD4q16oddPseudo: in getOperandLatency()
3922 case ARM::VLD4q32oddPseudo: in getOperandLatency()
3923 case ARM::VLD4q8oddPseudo_UPD: in getOperandLatency()
3924 case ARM::VLD4q16oddPseudo_UPD: in getOperandLatency()
3925 case ARM::VLD4q32oddPseudo_UPD: in getOperandLatency()
3926 case ARM::VLD1DUPq8: in getOperandLatency()
3927 case ARM::VLD1DUPq16: in getOperandLatency()
3928 case ARM::VLD1DUPq32: in getOperandLatency()
3929 case ARM::VLD1DUPq8wb_fixed: in getOperandLatency()
3930 case ARM::VLD1DUPq16wb_fixed: in getOperandLatency()
3931 case ARM::VLD1DUPq32wb_fixed: in getOperandLatency()
3932 case ARM::VLD1DUPq8wb_register: in getOperandLatency()
3933 case ARM::VLD1DUPq16wb_register: in getOperandLatency()
3934 case ARM::VLD1DUPq32wb_register: in getOperandLatency()
3935 case ARM::VLD2DUPd8: in getOperandLatency()
3936 case ARM::VLD2DUPd16: in getOperandLatency()
3937 case ARM::VLD2DUPd32: in getOperandLatency()
3938 case ARM::VLD2DUPd8wb_fixed: in getOperandLatency()
3939 case ARM::VLD2DUPd16wb_fixed: in getOperandLatency()
3940 case ARM::VLD2DUPd32wb_fixed: in getOperandLatency()
3941 case ARM::VLD2DUPd8wb_register: in getOperandLatency()
3942 case ARM::VLD2DUPd16wb_register: in getOperandLatency()
3943 case ARM::VLD2DUPd32wb_register: in getOperandLatency()
3944 case ARM::VLD4DUPd8Pseudo: in getOperandLatency()
3945 case ARM::VLD4DUPd16Pseudo: in getOperandLatency()
3946 case ARM::VLD4DUPd32Pseudo: in getOperandLatency()
3947 case ARM::VLD4DUPd8Pseudo_UPD: in getOperandLatency()
3948 case ARM::VLD4DUPd16Pseudo_UPD: in getOperandLatency()
3949 case ARM::VLD4DUPd32Pseudo_UPD: in getOperandLatency()
3950 case ARM::VLD1LNq8Pseudo: in getOperandLatency()
3951 case ARM::VLD1LNq16Pseudo: in getOperandLatency()
3952 case ARM::VLD1LNq32Pseudo: in getOperandLatency()
3953 case ARM::VLD1LNq8Pseudo_UPD: in getOperandLatency()
3954 case ARM::VLD1LNq16Pseudo_UPD: in getOperandLatency()
3955 case ARM::VLD1LNq32Pseudo_UPD: in getOperandLatency()
3956 case ARM::VLD2LNd8Pseudo: in getOperandLatency()
3957 case ARM::VLD2LNd16Pseudo: in getOperandLatency()
3958 case ARM::VLD2LNd32Pseudo: in getOperandLatency()
3959 case ARM::VLD2LNq16Pseudo: in getOperandLatency()
3960 case ARM::VLD2LNq32Pseudo: in getOperandLatency()
3961 case ARM::VLD2LNd8Pseudo_UPD: in getOperandLatency()
3962 case ARM::VLD2LNd16Pseudo_UPD: in getOperandLatency()
3963 case ARM::VLD2LNd32Pseudo_UPD: in getOperandLatency()
3964 case ARM::VLD2LNq16Pseudo_UPD: in getOperandLatency()
3965 case ARM::VLD2LNq32Pseudo_UPD: in getOperandLatency()
3966 case ARM::VLD4LNd8Pseudo: in getOperandLatency()
3967 case ARM::VLD4LNd16Pseudo: in getOperandLatency()
3968 case ARM::VLD4LNd32Pseudo: in getOperandLatency()
3969 case ARM::VLD4LNq16Pseudo: in getOperandLatency()
3970 case ARM::VLD4LNq32Pseudo: in getOperandLatency()
3971 case ARM::VLD4LNd8Pseudo_UPD: in getOperandLatency()
3972 case ARM::VLD4LNd16Pseudo_UPD: in getOperandLatency()
3973 case ARM::VLD4LNd32Pseudo_UPD: in getOperandLatency()
3974 case ARM::VLD4LNq16Pseudo_UPD: in getOperandLatency()
3975 case ARM::VLD4LNq32Pseudo_UPD: in getOperandLatency()
3995 if (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) { in getPredicationCost()
4017 if (I->getOpcode() != ARM::t2IT) in getInstrLatency()
4024 if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) { in getInstrLatency()
4065 case ARM::VLDMQIA: in getInstrLatency()
4066 case ARM::VSTMQIA: in getInstrLatency()
4190 if (MI.getOpcode() == ARM::VMOVD && !isPredicated(MI)) in getExecutionDomain()
4196 (MI.getOpcode() == ARM::VMOVRS || MI.getOpcode() == ARM::VMOVSR || in getExecutionDomain()
4197 MI.getOpcode() == ARM::VMOVS)) in getExecutionDomain()
4219 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
4222 if (DReg != ARM::NoRegister) in getCorrespondingDRegAndLane()
4226 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
4259 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1); in getImplicitSPRUseForDPRUse()
4284 case ARM::VMOVD: in setExecutionDomain()
4302 MI.setDesc(get(ARM::VORRd)); in setExecutionDomain()
4306 case ARM::VMOVRS: in setExecutionDomain()
4323 MI.setDesc(get(ARM::VGETLNi32)); in setExecutionDomain()
4332 case ARM::VMOVSR: { in setExecutionDomain()
4352 MI.setDesc(get(ARM::VSETLNi32)); in setExecutionDomain()
4366 case ARM::VMOVS: { in setExecutionDomain()
4388 MI.setDesc(get(ARM::VDUPLN32d)); in setExecutionDomain()
4416 NewMIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::VEXTd32), in setExecutionDomain()
4436 MI.setDesc(get(ARM::VEXTd32)); in setExecutionDomain()
4499 case ARM::VLDRS: in getPartialRegUpdateClearance()
4500 case ARM::FCONSTS: in getPartialRegUpdateClearance()
4501 case ARM::VMOVSR: in getPartialRegUpdateClearance()
4502 case ARM::VMOVv8i8: in getPartialRegUpdateClearance()
4503 case ARM::VMOVv4i16: in getPartialRegUpdateClearance()
4504 case ARM::VMOVv2i32: in getPartialRegUpdateClearance()
4505 case ARM::VMOVv2f32: in getPartialRegUpdateClearance()
4506 case ARM::VMOVv1i64: in getPartialRegUpdateClearance()
4511 case ARM::VLD1LNd32: in getPartialRegUpdateClearance()
4528 } else if (ARM::SPRRegClass.contains(Reg)) { in getPartialRegUpdateClearance()
4530 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0, in getPartialRegUpdateClearance()
4531 &ARM::DPRRegClass); in getPartialRegUpdateClearance()
4555 if (ARM::SPRRegClass.contains(Reg)) { in breakPartialRegDependency()
4556 DReg = ARM::D0 + (Reg - ARM::S0) / 2; in breakPartialRegDependency()
4560 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps"); in breakPartialRegDependency()
4572 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::FCONSTD), DReg) in breakPartialRegDependency()
4578 return Subtarget.getFeatureBits()[ARM::HasV6KOps]; in hasNOP()
4602 case ARM::VMOVDRR: in getRegSequenceLikeInputs()
4610 RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_0)); in getRegSequenceLikeInputs()
4614 RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_1)); in getRegSequenceLikeInputs()
4627 case ARM::VMOVRRD: in getExtractSubregLikeInputs()
4635 InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1; in getExtractSubregLikeInputs()
4648 case ARM::VSETLNi32: in getInsertSubregLikeInputs()
4658 InsertedReg.SubIdx = MOIndex.getImm() == 0 ? ARM::ssub_0 : ARM::ssub_1; in getInsertSubregLikeInputs()