Lines Matching refs:src1
29 (ins VecDblRegs:$src1),
30 "$dst=vassignp_W($src1)",
31 [(set VecDblRegs:$dst, (int_hexagon_V6_vassignp VecDblRegs:$src1))]>;
35 (ins VecDblRegs128B:$src1),
36 "$dst=vassignp_W_128B($src1)",
38 VecDblRegs128B:$src1))]>;
42 (ins VecDblRegs:$src1),
43 "$dst=lo_W($src1)",
44 [(set VectorRegs:$dst, (int_hexagon_V6_lo VecDblRegs:$src1))]>;
48 (ins VecDblRegs:$src1),
49 "$dst=hi_W($src1)",
50 [(set VectorRegs:$dst, (int_hexagon_V6_hi VecDblRegs:$src1))]>;
54 (ins VecDblRegs128B:$src1),
55 "$dst=lo_W($src1)",
56 [(set VectorRegs128B:$dst, (int_hexagon_V6_lo_128B VecDblRegs128B:$src1))]>;
60 (ins VecDblRegs128B:$src1),
61 "$dst=hi_W($src1)",
62 [(set VectorRegs128B:$dst, (int_hexagon_V6_hi_128B VecDblRegs128B:$src1))]>;
65 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 VecDblRegs:$src1))),
66 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_loreg)) >,
69 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 VecDblRegs:$src1))),
70 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_hireg)) >,
73 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 VecDblRegs128B:$src1))),
74 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1),
78 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 VecDblRegs128B:$src1))),
79 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1),
84 def : Pat <(v512i1 (bitconvert (v16i32 VectorRegs:$src1))),
85 (v512i1 (V6_vandvrt(v16i32 VectorRegs:$src1),
89 def : Pat <(v512i1 (bitconvert (v32i16 VectorRegs:$src1))),
90 (v512i1 (V6_vandvrt(v32i16 VectorRegs:$src1),
94 def : Pat <(v512i1 (bitconvert (v64i8 VectorRegs:$src1))),
95 (v512i1 (V6_vandvrt(v64i8 VectorRegs:$src1),
99 def : Pat <(v512i1 (bitconvert (v8i64 VectorRegs:$src1))),
100 (v512i1 (V6_vandvrt(v8i64 VectorRegs:$src1),
104 def : Pat <(v16i32 (bitconvert (v512i1 VecPredRegs:$src1))),
105 (v16i32 (V6_vandqrt(v512i1 VecPredRegs:$src1),
109 def : Pat <(v32i16 (bitconvert (v512i1 VecPredRegs:$src1))),
110 (v32i16 (V6_vandqrt(v512i1 VecPredRegs:$src1),
114 def : Pat <(v64i8 (bitconvert (v512i1 VecPredRegs:$src1))),
115 (v64i8 (V6_vandqrt(v512i1 VecPredRegs:$src1),
119 def : Pat <(v8i64 (bitconvert (v512i1 VecPredRegs:$src1))),
120 (v8i64 (V6_vandqrt(v512i1 VecPredRegs:$src1),
124 def : Pat <(v1024i1 (bitconvert (v32i32 VectorRegs128B:$src1))),
125 (v1024i1 (V6_vandvrt_128B(v32i32 VectorRegs128B:$src1),
129 def : Pat <(v1024i1 (bitconvert (v64i16 VectorRegs128B:$src1))),
130 (v1024i1 (V6_vandvrt_128B(v64i16 VectorRegs128B:$src1),
134 def : Pat <(v1024i1 (bitconvert (v128i8 VectorRegs128B:$src1))),
135 (v1024i1 (V6_vandvrt_128B(v128i8 VectorRegs128B:$src1),
139 def : Pat <(v1024i1 (bitconvert (v16i64 VectorRegs128B:$src1))),
140 (v1024i1 (V6_vandvrt_128B(v16i64 VectorRegs128B:$src1),
144 def : Pat <(v32i32 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
145 (v32i32 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
149 def : Pat <(v64i16 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
150 (v64i16 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
154 def : Pat <(v128i8 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
155 (v128i8 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
159 def : Pat <(v16i64 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
160 (v16i64 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
165 def : Pat <(store (v512i1 VecPredRegs:$src1), (i32 IntRegs:$addr)),
167 (v16i32 (V6_vandqrt (v512i1 VecPredRegs:$src1),
176 def : Pat <(store (v1024i1 VecPredRegs128B:$src1), (i32 IntRegs:$addr)),
178 (v32i32 (V6_vandqrt_128B (v1024i1 VecPredRegs128B:$src1),
190 def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>,
192 def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
193 (!cast<InstHexagon>(MI#"_128B") IntRegs:$src1)>,
198 def: Pat<(IntID VectorRegs:$src1),
199 (MI VectorRegs:$src1)>,
202 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1),
203 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1)>,
208 def: Pat<(IntID VecPredRegs:$src1),
209 (MI VecPredRegs:$src1)>,
212 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1),
213 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1)>,
218 def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2),
219 (MI VecDblRegs:$src1, IntRegs:$src2)>,
222 def: Pat<(!cast<Intrinsic>(IntID#"_128B")VecDblRegs128B:$src1, IntRegs:$src2),
223 (!cast<InstHexagon>(MI#"_128B")VecDblRegs128B:$src1, IntRegs:$src2)>,
228 def: Pat<(IntID VectorRegs:$src1, IntRegs:$src2),
229 (MI VectorRegs:$src1, IntRegs:$src2)>,
232 def: Pat<(!cast<Intrinsic>(IntID#"_128B")VectorRegs128B:$src1, IntRegs:$src2),
233 (!cast<InstHexagon>(MI#"_128B")VectorRegs128B:$src1, IntRegs:$src2)>,
238 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2),
239 (MI VecDblRegs:$src1, VectorRegs:$src2)>,
242 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
244 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
250 def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2),
251 (MI VecDblRegs:$src1, VecDblRegs:$src2)>,
254 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
256 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
262 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2),
263 (MI VectorRegs:$src1, VectorRegs:$src2)>,
266 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
268 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
274 def: Pat<(IntID VecPredRegs:$src1, IntRegs:$src2),
275 (MI VecPredRegs:$src1, IntRegs:$src2)>,
278 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
280 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1,
286 def: Pat<(IntID VecPredRegs:$src1, VecPredRegs:$src2),
287 (MI VecPredRegs:$src1, VecPredRegs:$src2)>,
290 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
292 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1,
298 def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3),
299 (MI VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>,
302 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
305 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
312 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
313 (MI VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>,
316 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
319 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
326 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
327 (MI VecDblRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>,
330 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
333 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
340 def: Pat<(IntID VectorRegs:$src1, VecDblRegs:$src2, IntRegs:$src3),
341 (MI VectorRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>,
344 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
347 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
354 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
355 (MI VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>,
358 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
361 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
368 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
369 (MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>,
372 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
375 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
382 def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
383 (MI VecPredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>,
386 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
389 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1,
396 def: Pat<(IntID VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3),
397 (MI VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3)>,
400 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
403 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
411 def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
412 (MI VecPredRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>,
415 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
418 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1,
425 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, imm:$src3),
426 (MI VectorRegs:$src1, VectorRegs:$src2, imm:$src3)>,
429 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
431 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
437 def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2, imm:$src3),
438 (MI VecDblRegs:$src1, IntRegs:$src2, imm:$src3)>,
441 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
443 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
449 def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3, imm:$src4),
450 (MI VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3, imm:$src4)>,
453 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
456 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
463 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3,
465 (MI VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3,
469 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
473 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
481 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3,
483 (MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3,
487 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
491 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,