1//=- HexagonIntrinsicsV60.td - Target Description for Hexagon -*- tablegen *-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Hexagon V60 Compiler Intrinsics in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14 15let isCodeGenOnly = 1 in { 16def HEXAGON_V6_vd0_pseudo : CVI_VA_Resource<(outs VectorRegs:$dst), 17 (ins ), 18 "$dst=#0", 19 [(set VectorRegs:$dst, (int_hexagon_V6_vd0 ))]>; 20 21def HEXAGON_V6_vd0_pseudo_128B : CVI_VA_Resource<(outs VectorRegs128B:$dst), 22 (ins ), 23 "$dst=#0", 24 [(set VectorRegs128B:$dst, (int_hexagon_V6_vd0_128B ))]>; 25} 26 27let isPseudo = 1 in 28def HEXAGON_V6_vassignp : CVI_VA_Resource<(outs VecDblRegs:$dst), 29 (ins VecDblRegs:$src1), 30 "$dst=vassignp_W($src1)", 31 [(set VecDblRegs:$dst, (int_hexagon_V6_vassignp VecDblRegs:$src1))]>; 32 33let isPseudo = 1 in 34def HEXAGON_V6_vassignp_128B : CVI_VA_Resource<(outs VecDblRegs128B:$dst), 35 (ins VecDblRegs128B:$src1), 36 "$dst=vassignp_W_128B($src1)", 37 [(set VecDblRegs128B:$dst, (int_hexagon_V6_vassignp_128B 38 VecDblRegs128B:$src1))]>; 39 40let isPseudo = 1 in 41def HEXAGON_V6_lo : CVI_VA_Resource<(outs VectorRegs:$dst), 42 (ins VecDblRegs:$src1), 43 "$dst=lo_W($src1)", 44 [(set VectorRegs:$dst, (int_hexagon_V6_lo VecDblRegs:$src1))]>; 45 46let isPseudo = 1 in 47def HEXAGON_V6_hi : CVI_VA_Resource<(outs VectorRegs:$dst), 48 (ins VecDblRegs:$src1), 49 "$dst=hi_W($src1)", 50 [(set VectorRegs:$dst, (int_hexagon_V6_hi VecDblRegs:$src1))]>; 51 52let isPseudo = 1 in 53def HEXAGON_V6_lo_128B : CVI_VA_Resource<(outs VectorRegs128B:$dst), 54 (ins VecDblRegs128B:$src1), 55 "$dst=lo_W($src1)", 56 [(set VectorRegs128B:$dst, (int_hexagon_V6_lo_128B VecDblRegs128B:$src1))]>; 57 58let isPseudo = 1 in 59def HEXAGON_V6_hi_128B : CVI_VA_Resource<(outs VectorRegs128B:$dst), 60 (ins VecDblRegs128B:$src1), 61 "$dst=hi_W($src1)", 62 [(set VectorRegs128B:$dst, (int_hexagon_V6_hi_128B VecDblRegs128B:$src1))]>; 63 64let AddedComplexity = 100 in { 65def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 VecDblRegs:$src1))), 66 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_loreg)) >, 67 Requires<[UseHVXSgl]>; 68 69def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 VecDblRegs:$src1))), 70 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_hireg)) >, 71 Requires<[UseHVXSgl]>; 72 73def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 VecDblRegs128B:$src1))), 74 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1), 75 subreg_loreg)) >, 76 Requires<[UseHVXDbl]>; 77 78def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 VecDblRegs128B:$src1))), 79 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1), 80 subreg_hireg)) >, 81 Requires<[UseHVXDbl]>; 82} 83 84def : Pat <(v512i1 (bitconvert (v16i32 VectorRegs:$src1))), 85 (v512i1 (V6_vandvrt(v16i32 VectorRegs:$src1), 86 (A2_tfrsi 0x01010101)))>, 87 Requires<[UseHVXSgl]>; 88 89def : Pat <(v512i1 (bitconvert (v32i16 VectorRegs:$src1))), 90 (v512i1 (V6_vandvrt(v32i16 VectorRegs:$src1), 91 (A2_tfrsi 0x01010101)))>, 92 Requires<[UseHVXSgl]>; 93 94def : Pat <(v512i1 (bitconvert (v64i8 VectorRegs:$src1))), 95 (v512i1 (V6_vandvrt(v64i8 VectorRegs:$src1), 96 (A2_tfrsi 0x01010101)))>, 97 Requires<[UseHVXSgl]>; 98 99def : Pat <(v512i1 (bitconvert (v8i64 VectorRegs:$src1))), 100 (v512i1 (V6_vandvrt(v8i64 VectorRegs:$src1), 101 (A2_tfrsi 0x01010101)))>, 102 Requires<[UseHVXSgl]>; 103 104def : Pat <(v16i32 (bitconvert (v512i1 VecPredRegs:$src1))), 105 (v16i32 (V6_vandqrt(v512i1 VecPredRegs:$src1), 106 (A2_tfrsi 0x01010101)))>, 107 Requires<[UseHVXSgl]>; 108 109def : Pat <(v32i16 (bitconvert (v512i1 VecPredRegs:$src1))), 110 (v32i16 (V6_vandqrt(v512i1 VecPredRegs:$src1), 111 (A2_tfrsi 0x01010101)))>, 112 Requires<[UseHVXSgl]>; 113 114def : Pat <(v64i8 (bitconvert (v512i1 VecPredRegs:$src1))), 115 (v64i8 (V6_vandqrt(v512i1 VecPredRegs:$src1), 116 (A2_tfrsi 0x01010101)))>, 117 Requires<[UseHVXSgl]>; 118 119def : Pat <(v8i64 (bitconvert (v512i1 VecPredRegs:$src1))), 120 (v8i64 (V6_vandqrt(v512i1 VecPredRegs:$src1), 121 (A2_tfrsi 0x01010101)))>, 122 Requires<[UseHVXSgl]>; 123 124def : Pat <(v1024i1 (bitconvert (v32i32 VectorRegs128B:$src1))), 125 (v1024i1 (V6_vandvrt_128B(v32i32 VectorRegs128B:$src1), 126 (A2_tfrsi 0x01010101)))>, 127 Requires<[UseHVXDbl]>; 128 129def : Pat <(v1024i1 (bitconvert (v64i16 VectorRegs128B:$src1))), 130 (v1024i1 (V6_vandvrt_128B(v64i16 VectorRegs128B:$src1), 131 (A2_tfrsi 0x01010101)))>, 132 Requires<[UseHVXDbl]>; 133 134def : Pat <(v1024i1 (bitconvert (v128i8 VectorRegs128B:$src1))), 135 (v1024i1 (V6_vandvrt_128B(v128i8 VectorRegs128B:$src1), 136 (A2_tfrsi 0x01010101)))>, 137 Requires<[UseHVXDbl]>; 138 139def : Pat <(v1024i1 (bitconvert (v16i64 VectorRegs128B:$src1))), 140 (v1024i1 (V6_vandvrt_128B(v16i64 VectorRegs128B:$src1), 141 (A2_tfrsi 0x01010101)))>, 142 Requires<[UseHVXDbl]>; 143 144def : Pat <(v32i32 (bitconvert (v1024i1 VecPredRegs128B:$src1))), 145 (v32i32 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1), 146 (A2_tfrsi 0x01010101)))>, 147 Requires<[UseHVXDbl]>; 148 149def : Pat <(v64i16 (bitconvert (v1024i1 VecPredRegs128B:$src1))), 150 (v64i16 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1), 151 (A2_tfrsi 0x01010101)))>, 152 Requires<[UseHVXDbl]>; 153 154def : Pat <(v128i8 (bitconvert (v1024i1 VecPredRegs128B:$src1))), 155 (v128i8 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1), 156 (A2_tfrsi 0x01010101)))>, 157 Requires<[UseHVXDbl]>; 158 159def : Pat <(v16i64 (bitconvert (v1024i1 VecPredRegs128B:$src1))), 160 (v16i64 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1), 161 (A2_tfrsi 0x01010101)))>, 162 Requires<[UseHVXDbl]>; 163 164let AddedComplexity = 140 in { 165def : Pat <(store (v512i1 VecPredRegs:$src1), (i32 IntRegs:$addr)), 166 (V6_vS32b_ai IntRegs:$addr, 0, 167 (v16i32 (V6_vandqrt (v512i1 VecPredRegs:$src1), 168 (A2_tfrsi 0x01010101))))>, 169 Requires<[UseHVXSgl]>; 170 171def : Pat <(v512i1 (load (i32 IntRegs:$addr))), 172 (v512i1 (V6_vandvrt 173 (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>, 174 Requires<[UseHVXSgl]>; 175 176def : Pat <(store (v1024i1 VecPredRegs128B:$src1), (i32 IntRegs:$addr)), 177 (V6_vS32b_ai_128B IntRegs:$addr, 0, 178 (v32i32 (V6_vandqrt_128B (v1024i1 VecPredRegs128B:$src1), 179 (A2_tfrsi 0x01010101))))>, 180 Requires<[UseHVXDbl]>; 181 182def : Pat <(v1024i1 (load (i32 IntRegs:$addr))), 183 (v1024i1 (V6_vandvrt_128B 184 (v32i32 (V6_vL32b_ai_128B IntRegs:$addr, 0)), 185 (A2_tfrsi 0x01010101)))>, 186 Requires<[UseHVXDbl]>; 187} 188 189multiclass T_R_pat <InstHexagon MI, Intrinsic IntID> { 190 def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>, 191 Requires<[UseHVXSgl]>; 192 def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1), 193 (!cast<InstHexagon>(MI#"_128B") IntRegs:$src1)>, 194 Requires<[UseHVXDbl]>; 195} 196 197multiclass T_V_pat <InstHexagon MI, Intrinsic IntID> { 198 def: Pat<(IntID VectorRegs:$src1), 199 (MI VectorRegs:$src1)>, 200 Requires<[UseHVXSgl]>; 201 202 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1), 203 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1)>, 204 Requires<[UseHVXDbl]>; 205} 206 207multiclass T_Q_pat <InstHexagon MI, Intrinsic IntID> { 208 def: Pat<(IntID VecPredRegs:$src1), 209 (MI VecPredRegs:$src1)>, 210 Requires<[UseHVXSgl]>; 211 212 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1), 213 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1)>, 214 Requires<[UseHVXDbl]>; 215} 216 217multiclass T_WR_pat <InstHexagon MI, Intrinsic IntID> { 218 def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2), 219 (MI VecDblRegs:$src1, IntRegs:$src2)>, 220 Requires<[UseHVXSgl]>; 221 222 def: Pat<(!cast<Intrinsic>(IntID#"_128B")VecDblRegs128B:$src1, IntRegs:$src2), 223 (!cast<InstHexagon>(MI#"_128B")VecDblRegs128B:$src1, IntRegs:$src2)>, 224 Requires<[UseHVXDbl]>; 225} 226 227multiclass T_VR_pat <InstHexagon MI, Intrinsic IntID> { 228 def: Pat<(IntID VectorRegs:$src1, IntRegs:$src2), 229 (MI VectorRegs:$src1, IntRegs:$src2)>, 230 Requires<[UseHVXSgl]>; 231 232 def: Pat<(!cast<Intrinsic>(IntID#"_128B")VectorRegs128B:$src1, IntRegs:$src2), 233 (!cast<InstHexagon>(MI#"_128B")VectorRegs128B:$src1, IntRegs:$src2)>, 234 Requires<[UseHVXDbl]>; 235} 236 237multiclass T_WV_pat <InstHexagon MI, Intrinsic IntID> { 238 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2), 239 (MI VecDblRegs:$src1, VectorRegs:$src2)>, 240 Requires<[UseHVXSgl]>; 241 242 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, 243 VectorRegs128B:$src2), 244 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, 245 VectorRegs128B:$src2)>, 246 Requires<[UseHVXDbl]>; 247} 248 249multiclass T_WW_pat <InstHexagon MI, Intrinsic IntID> { 250 def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2), 251 (MI VecDblRegs:$src1, VecDblRegs:$src2)>, 252 Requires<[UseHVXSgl]>; 253 254 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, 255 VecDblRegs128B:$src2), 256 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, 257 VecDblRegs128B:$src2)>, 258 Requires<[UseHVXDbl]>; 259} 260 261multiclass T_VV_pat <InstHexagon MI, Intrinsic IntID> { 262 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2), 263 (MI VectorRegs:$src1, VectorRegs:$src2)>, 264 Requires<[UseHVXSgl]>; 265 266 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, 267 VectorRegs128B:$src2), 268 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, 269 VectorRegs128B:$src2)>, 270 Requires<[UseHVXDbl]>; 271} 272 273multiclass T_QR_pat <InstHexagon MI, Intrinsic IntID> { 274 def: Pat<(IntID VecPredRegs:$src1, IntRegs:$src2), 275 (MI VecPredRegs:$src1, IntRegs:$src2)>, 276 Requires<[UseHVXSgl]>; 277 278 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1, 279 IntRegs:$src2), 280 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1, 281 IntRegs:$src2)>, 282 Requires<[UseHVXDbl]>; 283} 284 285multiclass T_QQ_pat <InstHexagon MI, Intrinsic IntID> { 286 def: Pat<(IntID VecPredRegs:$src1, VecPredRegs:$src2), 287 (MI VecPredRegs:$src1, VecPredRegs:$src2)>, 288 Requires<[UseHVXSgl]>; 289 290 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1, 291 VecPredRegs128B:$src2), 292 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1, 293 VecPredRegs128B:$src2)>, 294 Requires<[UseHVXDbl]>; 295} 296 297multiclass T_WWR_pat <InstHexagon MI, Intrinsic IntID> { 298 def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3), 299 (MI VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>, 300 Requires<[UseHVXSgl]>; 301 302 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, 303 VecDblRegs128B:$src2, 304 IntRegs:$src3), 305 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, 306 VecDblRegs128B:$src2, 307 IntRegs:$src3)>, 308 Requires<[UseHVXDbl]>; 309} 310 311multiclass T_VVR_pat <InstHexagon MI, Intrinsic IntID> { 312 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3), 313 (MI VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>, 314 Requires<[UseHVXSgl]>; 315 316 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, 317 VectorRegs128B:$src2, 318 IntRegs:$src3), 319 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, 320 VectorRegs128B:$src2, 321 IntRegs:$src3)>, 322 Requires<[UseHVXDbl]>; 323} 324 325multiclass T_WVR_pat <InstHexagon MI, Intrinsic IntID> { 326 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, IntRegs:$src3), 327 (MI VecDblRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>, 328 Requires<[UseHVXSgl]>; 329 330 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, 331 VectorRegs128B:$src2, 332 IntRegs:$src3), 333 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, 334 VectorRegs128B:$src2, 335 IntRegs:$src3)>, 336 Requires<[UseHVXDbl]>; 337} 338 339multiclass T_VWR_pat <InstHexagon MI, Intrinsic IntID> { 340 def: Pat<(IntID VectorRegs:$src1, VecDblRegs:$src2, IntRegs:$src3), 341 (MI VectorRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>, 342 Requires<[UseHVXSgl]>; 343 344 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, 345 VecDblRegs128B:$src2, 346 IntRegs:$src3), 347 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, 348 VecDblRegs128B:$src2, 349 IntRegs:$src3)>, 350 Requires<[UseHVXDbl]>; 351} 352 353multiclass T_VVV_pat <InstHexagon MI, Intrinsic IntID> { 354 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3), 355 (MI VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>, 356 Requires<[UseHVXSgl]>; 357 358 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, 359 VectorRegs128B:$src2, 360 VectorRegs128B:$src3), 361 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, 362 VectorRegs128B:$src2, 363 VectorRegs128B:$src3)>, 364 Requires<[UseHVXDbl]>; 365} 366 367multiclass T_WVV_pat <InstHexagon MI, Intrinsic IntID> { 368 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3), 369 (MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>, 370 Requires<[UseHVXSgl]>; 371 372 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, 373 VectorRegs128B:$src2, 374 VectorRegs128B:$src3), 375 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, 376 VectorRegs128B:$src2, 377 VectorRegs128B:$src3)>, 378 Requires<[UseHVXDbl]>; 379} 380 381multiclass T_QVV_pat <InstHexagon MI, Intrinsic IntID> { 382 def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3), 383 (MI VecPredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>, 384 Requires<[UseHVXSgl]>; 385 386 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1, 387 VectorRegs128B:$src2, 388 VectorRegs128B:$src3), 389 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1, 390 VectorRegs128B:$src2, 391 VectorRegs128B:$src3)>, 392 Requires<[UseHVXDbl]>; 393} 394 395multiclass T_VQR_pat <InstHexagon MI, Intrinsic IntID> { 396 def: Pat<(IntID VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3), 397 (MI VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3)>, 398 Requires<[UseHVXSgl]>; 399 400 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, 401 VecPredRegs128B:$src2, 402 IntRegs:$src3), 403 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, 404 VecPredRegs128B:$src2, 405 IntRegs:$src3)>, 406 Requires<[UseHVXDbl]>; 407} 408 409 410multiclass T_QVR_pat <InstHexagon MI, Intrinsic IntID> { 411 def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2, IntRegs:$src3), 412 (MI VecPredRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>, 413 Requires<[UseHVXSgl]>; 414 415 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1, 416 VectorRegs128B:$src2, 417 IntRegs:$src3), 418 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1, 419 VectorRegs128B:$src2, 420 IntRegs:$src3)>, 421 Requires<[UseHVXDbl]>; 422} 423 424multiclass T_VVI_pat <InstHexagon MI, Intrinsic IntID> { 425 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, imm:$src3), 426 (MI VectorRegs:$src1, VectorRegs:$src2, imm:$src3)>, 427 Requires<[UseHVXSgl]>; 428 429 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, 430 VectorRegs128B:$src2, imm:$src3), 431 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, 432 VectorRegs128B:$src2, imm:$src3)>, 433 Requires<[UseHVXDbl]>; 434} 435 436multiclass T_WRI_pat <InstHexagon MI, Intrinsic IntID> { 437 def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2, imm:$src3), 438 (MI VecDblRegs:$src1, IntRegs:$src2, imm:$src3)>, 439 Requires<[UseHVXSgl]>; 440 441 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, 442 IntRegs:$src2, imm:$src3), 443 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, 444 IntRegs:$src2, imm:$src3)>, 445 Requires<[UseHVXDbl]>; 446} 447 448multiclass T_WWRI_pat <InstHexagon MI, Intrinsic IntID> { 449 def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3, imm:$src4), 450 (MI VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3, imm:$src4)>, 451 Requires<[UseHVXSgl]>; 452 453 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, 454 VecDblRegs128B:$src2, 455 IntRegs:$src3, imm:$src4), 456 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, 457 VecDblRegs128B:$src2, 458 IntRegs:$src3, imm:$src4)>, 459 Requires<[UseHVXDbl]>; 460} 461 462multiclass T_VVVR_pat <InstHexagon MI, Intrinsic IntID> { 463 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, 464 IntRegs:$src4), 465 (MI VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, 466 IntRegs:$src4)>, 467 Requires<[UseHVXSgl]>; 468 469 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, 470 VectorRegs128B:$src2, 471 VectorRegs128B:$src3, 472 IntRegs:$src4), 473 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, 474 VectorRegs128B:$src2, 475 VectorRegs128B:$src3, 476 IntRegs:$src4)>, 477 Requires<[UseHVXDbl]>; 478} 479 480multiclass T_WVVR_pat <InstHexagon MI, Intrinsic IntID> { 481 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, 482 IntRegs:$src4), 483 (MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, 484 IntRegs:$src4)>, 485 Requires<[UseHVXSgl]>; 486 487 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, 488 VectorRegs128B:$src2, 489 VectorRegs128B:$src3, 490 IntRegs:$src4), 491 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, 492 VectorRegs128B:$src2, 493 VectorRegs128B:$src3, 494 IntRegs:$src4)>, 495 Requires<[UseHVXDbl]>; 496} 497 498defm : T_WR_pat<V6_vtmpyb, int_hexagon_V6_vtmpyb>; 499defm : T_WR_pat <V6_vtmpybus, int_hexagon_V6_vtmpybus>; 500defm : T_VR_pat <V6_vdmpyhb, int_hexagon_V6_vdmpyhb>; 501defm : T_VR_pat <V6_vrmpyub, int_hexagon_V6_vrmpyub>; 502defm : T_VR_pat <V6_vrmpybus, int_hexagon_V6_vrmpybus>; 503defm : T_WR_pat <V6_vdsaduh, int_hexagon_V6_vdsaduh>; 504defm : T_VR_pat <V6_vdmpybus, int_hexagon_V6_vdmpybus>; 505defm : T_WR_pat <V6_vdmpybus_dv, int_hexagon_V6_vdmpybus_dv>; 506defm : T_VR_pat <V6_vdmpyhsusat, int_hexagon_V6_vdmpyhsusat>; 507defm : T_WR_pat <V6_vdmpyhsuisat, int_hexagon_V6_vdmpyhsuisat>; 508defm : T_VR_pat <V6_vdmpyhsat, int_hexagon_V6_vdmpyhsat>; 509defm : T_WR_pat <V6_vdmpyhisat, int_hexagon_V6_vdmpyhisat>; 510defm : T_WR_pat <V6_vdmpyhb_dv, int_hexagon_V6_vdmpyhb_dv>; 511defm : T_VR_pat <V6_vmpybus, int_hexagon_V6_vmpybus>; 512defm : T_WR_pat <V6_vmpabus, int_hexagon_V6_vmpabus>; 513defm : T_WR_pat <V6_vmpahb, int_hexagon_V6_vmpahb>; 514defm : T_VR_pat <V6_vmpyh, int_hexagon_V6_vmpyh>; 515defm : T_VR_pat <V6_vmpyhss, int_hexagon_V6_vmpyhss>; 516defm : T_VR_pat <V6_vmpyhsrs, int_hexagon_V6_vmpyhsrs>; 517defm : T_VR_pat <V6_vmpyuh, int_hexagon_V6_vmpyuh>; 518defm : T_VR_pat <V6_vmpyihb, int_hexagon_V6_vmpyihb>; 519defm : T_VR_pat <V6_vror, int_hexagon_V6_vror>; 520defm : T_VR_pat <V6_vasrw, int_hexagon_V6_vasrw>; 521defm : T_VR_pat <V6_vasrh, int_hexagon_V6_vasrh>; 522defm : T_VR_pat <V6_vaslw, int_hexagon_V6_vaslw>; 523defm : T_VR_pat <V6_vaslh, int_hexagon_V6_vaslh>; 524defm : T_VR_pat <V6_vlsrw, int_hexagon_V6_vlsrw>; 525defm : T_VR_pat <V6_vlsrh, int_hexagon_V6_vlsrh>; 526defm : T_VR_pat <V6_vmpyiwh, int_hexagon_V6_vmpyiwh>; 527defm : T_VR_pat <V6_vmpyiwb, int_hexagon_V6_vmpyiwb>; 528defm : T_WR_pat <V6_vtmpyhb, int_hexagon_V6_vtmpyhb>; 529defm : T_VR_pat <V6_vmpyub, int_hexagon_V6_vmpyub>; 530 531defm : T_VV_pat <V6_vrmpyubv, int_hexagon_V6_vrmpyubv>; 532defm : T_VV_pat <V6_vrmpybv, int_hexagon_V6_vrmpybv>; 533defm : T_VV_pat <V6_vrmpybusv, int_hexagon_V6_vrmpybusv>; 534defm : T_VV_pat <V6_vdmpyhvsat, int_hexagon_V6_vdmpyhvsat>; 535defm : T_VV_pat <V6_vmpybv, int_hexagon_V6_vmpybv>; 536defm : T_VV_pat <V6_vmpyubv, int_hexagon_V6_vmpyubv>; 537defm : T_VV_pat <V6_vmpybusv, int_hexagon_V6_vmpybusv>; 538defm : T_VV_pat <V6_vmpyhv, int_hexagon_V6_vmpyhv>; 539defm : T_VV_pat <V6_vmpyuhv, int_hexagon_V6_vmpyuhv>; 540defm : T_VV_pat <V6_vmpyhvsrs, int_hexagon_V6_vmpyhvsrs>; 541defm : T_VV_pat <V6_vmpyhus, int_hexagon_V6_vmpyhus>; 542defm : T_WW_pat <V6_vmpabusv, int_hexagon_V6_vmpabusv>; 543defm : T_VV_pat <V6_vmpyih, int_hexagon_V6_vmpyih>; 544defm : T_VV_pat <V6_vand, int_hexagon_V6_vand>; 545defm : T_VV_pat <V6_vor, int_hexagon_V6_vor>; 546defm : T_VV_pat <V6_vxor, int_hexagon_V6_vxor>; 547defm : T_VV_pat <V6_vaddw, int_hexagon_V6_vaddw>; 548defm : T_VV_pat <V6_vaddubsat, int_hexagon_V6_vaddubsat>; 549defm : T_VV_pat <V6_vadduhsat, int_hexagon_V6_vadduhsat>; 550defm : T_VV_pat <V6_vaddhsat, int_hexagon_V6_vaddhsat>; 551defm : T_VV_pat <V6_vaddwsat, int_hexagon_V6_vaddwsat>; 552defm : T_VV_pat <V6_vsubb, int_hexagon_V6_vsubb>; 553defm : T_VV_pat <V6_vsubh, int_hexagon_V6_vsubh>; 554defm : T_VV_pat <V6_vsubw, int_hexagon_V6_vsubw>; 555defm : T_VV_pat <V6_vsububsat, int_hexagon_V6_vsububsat>; 556defm : T_VV_pat <V6_vsubuhsat, int_hexagon_V6_vsubuhsat>; 557defm : T_VV_pat <V6_vsubhsat, int_hexagon_V6_vsubhsat>; 558defm : T_VV_pat <V6_vsubwsat, int_hexagon_V6_vsubwsat>; 559defm : T_WW_pat <V6_vaddb_dv, int_hexagon_V6_vaddb_dv>; 560defm : T_WW_pat <V6_vaddh_dv, int_hexagon_V6_vaddh_dv>; 561defm : T_WW_pat <V6_vaddw_dv, int_hexagon_V6_vaddw_dv>; 562defm : T_WW_pat <V6_vaddubsat_dv, int_hexagon_V6_vaddubsat_dv>; 563defm : T_WW_pat <V6_vadduhsat_dv, int_hexagon_V6_vadduhsat_dv>; 564defm : T_WW_pat <V6_vaddhsat_dv, int_hexagon_V6_vaddhsat_dv>; 565defm : T_WW_pat <V6_vaddwsat_dv, int_hexagon_V6_vaddwsat_dv>; 566defm : T_WW_pat <V6_vsubb_dv, int_hexagon_V6_vsubb_dv>; 567defm : T_WW_pat <V6_vsubh_dv, int_hexagon_V6_vsubh_dv>; 568defm : T_WW_pat <V6_vsubw_dv, int_hexagon_V6_vsubw_dv>; 569defm : T_WW_pat <V6_vsububsat_dv, int_hexagon_V6_vsububsat_dv>; 570defm : T_WW_pat <V6_vsubuhsat_dv, int_hexagon_V6_vsubuhsat_dv>; 571defm : T_WW_pat <V6_vsubhsat_dv, int_hexagon_V6_vsubhsat_dv>; 572defm : T_WW_pat <V6_vsubwsat_dv, int_hexagon_V6_vsubwsat_dv>; 573defm : T_VV_pat <V6_vaddubh, int_hexagon_V6_vaddubh>; 574defm : T_VV_pat <V6_vadduhw, int_hexagon_V6_vadduhw>; 575defm : T_VV_pat <V6_vaddhw, int_hexagon_V6_vaddhw>; 576defm : T_VV_pat <V6_vsububh, int_hexagon_V6_vsububh>; 577defm : T_VV_pat <V6_vsubuhw, int_hexagon_V6_vsubuhw>; 578defm : T_VV_pat <V6_vsubhw, int_hexagon_V6_vsubhw>; 579defm : T_VV_pat <V6_vabsdiffub, int_hexagon_V6_vabsdiffub>; 580defm : T_VV_pat <V6_vabsdiffh, int_hexagon_V6_vabsdiffh>; 581defm : T_VV_pat <V6_vabsdiffuh, int_hexagon_V6_vabsdiffuh>; 582defm : T_VV_pat <V6_vabsdiffw, int_hexagon_V6_vabsdiffw>; 583defm : T_VV_pat <V6_vavgub, int_hexagon_V6_vavgub>; 584defm : T_VV_pat <V6_vavguh, int_hexagon_V6_vavguh>; 585defm : T_VV_pat <V6_vavgh, int_hexagon_V6_vavgh>; 586defm : T_VV_pat <V6_vavgw, int_hexagon_V6_vavgw>; 587defm : T_VV_pat <V6_vnavgub, int_hexagon_V6_vnavgub>; 588defm : T_VV_pat <V6_vnavgh, int_hexagon_V6_vnavgh>; 589defm : T_VV_pat <V6_vnavgw, int_hexagon_V6_vnavgw>; 590defm : T_VV_pat <V6_vavgubrnd, int_hexagon_V6_vavgubrnd>; 591defm : T_VV_pat <V6_vavguhrnd, int_hexagon_V6_vavguhrnd>; 592defm : T_VV_pat <V6_vavghrnd, int_hexagon_V6_vavghrnd>; 593defm : T_VV_pat <V6_vavgwrnd, int_hexagon_V6_vavgwrnd>; 594defm : T_WW_pat <V6_vmpabuuv, int_hexagon_V6_vmpabuuv>; 595 596defm : T_VVR_pat <V6_vdmpyhb_acc, int_hexagon_V6_vdmpyhb_acc>; 597defm : T_VVR_pat <V6_vrmpyub_acc, int_hexagon_V6_vrmpyub_acc>; 598defm : T_VVR_pat <V6_vrmpybus_acc, int_hexagon_V6_vrmpybus_acc>; 599defm : T_VVR_pat <V6_vdmpybus_acc, int_hexagon_V6_vdmpybus_acc>; 600defm : T_VVR_pat <V6_vdmpyhsusat_acc, int_hexagon_V6_vdmpyhsusat_acc>; 601defm : T_VVR_pat <V6_vdmpyhsat_acc, int_hexagon_V6_vdmpyhsat_acc>; 602defm : T_VVR_pat <V6_vmpyiwb_acc, int_hexagon_V6_vmpyiwb_acc>; 603defm : T_VVR_pat <V6_vmpyiwh_acc, int_hexagon_V6_vmpyiwh_acc>; 604defm : T_VVR_pat <V6_vmpyihb_acc, int_hexagon_V6_vmpyihb_acc>; 605defm : T_VVR_pat <V6_vaslw_acc, int_hexagon_V6_vaslw_acc>; 606defm : T_VVR_pat <V6_vasrw_acc, int_hexagon_V6_vasrw_acc>; 607 608defm : T_VWR_pat <V6_vdmpyhsuisat_acc, int_hexagon_V6_vdmpyhsuisat_acc>; 609defm : T_VWR_pat <V6_vdmpyhisat_acc, int_hexagon_V6_vdmpyhisat_acc>; 610 611defm : T_WVR_pat <V6_vmpybus_acc, int_hexagon_V6_vmpybus_acc>; 612defm : T_WVR_pat <V6_vmpyhsat_acc, int_hexagon_V6_vmpyhsat_acc>; 613defm : T_WVR_pat <V6_vmpyuh_acc, int_hexagon_V6_vmpyuh_acc>; 614defm : T_WVR_pat <V6_vmpyub_acc, int_hexagon_V6_vmpyub_acc>; 615 616defm : T_WWR_pat <V6_vtmpyb_acc, int_hexagon_V6_vtmpyb_acc>; 617defm : T_WWR_pat <V6_vtmpybus_acc, int_hexagon_V6_vtmpybus_acc>; 618defm : T_WWR_pat <V6_vtmpyhb_acc, int_hexagon_V6_vtmpyhb_acc>; 619defm : T_WWR_pat <V6_vdmpybus_dv_acc, int_hexagon_V6_vdmpybus_dv_acc>; 620defm : T_WWR_pat <V6_vdmpyhb_dv_acc, int_hexagon_V6_vdmpyhb_dv_acc>; 621defm : T_WWR_pat <V6_vmpabus_acc, int_hexagon_V6_vmpabus_acc>; 622defm : T_WWR_pat <V6_vmpahb_acc, int_hexagon_V6_vmpahb_acc>; 623defm : T_WWR_pat <V6_vdsaduh_acc, int_hexagon_V6_vdsaduh_acc>; 624 625defm : T_VVV_pat <V6_vdmpyhvsat_acc, int_hexagon_V6_vdmpyhvsat_acc>; 626defm : T_WVV_pat <V6_vmpybusv_acc, int_hexagon_V6_vmpybusv_acc>; 627defm : T_WVV_pat <V6_vmpybv_acc, int_hexagon_V6_vmpybv_acc>; 628defm : T_WVV_pat <V6_vmpyhus_acc, int_hexagon_V6_vmpyhus_acc>; 629defm : T_WVV_pat <V6_vmpyhv_acc, int_hexagon_V6_vmpyhv_acc>; 630defm : T_VVV_pat <V6_vmpyiewh_acc, int_hexagon_V6_vmpyiewh_acc>; 631defm : T_VVV_pat <V6_vmpyiewuh_acc, int_hexagon_V6_vmpyiewuh_acc>; 632defm : T_VVV_pat <V6_vmpyih_acc, int_hexagon_V6_vmpyih_acc>; 633defm : T_VVV_pat <V6_vmpyowh_rnd_sacc, int_hexagon_V6_vmpyowh_rnd_sacc>; 634defm : T_VVV_pat <V6_vmpyowh_sacc, int_hexagon_V6_vmpyowh_sacc>; 635defm : T_WVV_pat <V6_vmpyubv_acc, int_hexagon_V6_vmpyubv_acc>; 636defm : T_WVV_pat <V6_vmpyuhv_acc, int_hexagon_V6_vmpyuhv_acc>; 637defm : T_VVV_pat <V6_vrmpybusv_acc, int_hexagon_V6_vrmpybusv_acc>; 638defm : T_VVV_pat <V6_vrmpybv_acc, int_hexagon_V6_vrmpybv_acc>; 639defm : T_VVV_pat <V6_vrmpyubv_acc, int_hexagon_V6_vrmpyubv_acc>; 640 641// Compare instructions 642defm : T_QVV_pat <V6_veqb_and, int_hexagon_V6_veqb_and>; 643defm : T_QVV_pat <V6_veqh_and, int_hexagon_V6_veqh_and>; 644defm : T_QVV_pat <V6_veqw_and, int_hexagon_V6_veqw_and>; 645defm : T_QVV_pat <V6_vgtb_and, int_hexagon_V6_vgtb_and>; 646defm : T_QVV_pat <V6_vgth_and, int_hexagon_V6_vgth_and>; 647defm : T_QVV_pat <V6_vgtw_and, int_hexagon_V6_vgtw_and>; 648defm : T_QVV_pat <V6_vgtub_and, int_hexagon_V6_vgtub_and>; 649defm : T_QVV_pat <V6_vgtuh_and, int_hexagon_V6_vgtuh_and>; 650defm : T_QVV_pat <V6_vgtuw_and, int_hexagon_V6_vgtuw_and>; 651defm : T_QVV_pat <V6_veqb_or, int_hexagon_V6_veqb_or>; 652defm : T_QVV_pat <V6_veqh_or, int_hexagon_V6_veqh_or>; 653defm : T_QVV_pat <V6_veqw_or, int_hexagon_V6_veqw_or>; 654defm : T_QVV_pat <V6_vgtb_or, int_hexagon_V6_vgtb_or>; 655defm : T_QVV_pat <V6_vgth_or, int_hexagon_V6_vgth_or>; 656defm : T_QVV_pat <V6_vgtw_or, int_hexagon_V6_vgtw_or>; 657defm : T_QVV_pat <V6_vgtub_or, int_hexagon_V6_vgtub_or>; 658defm : T_QVV_pat <V6_vgtuh_or, int_hexagon_V6_vgtuh_or>; 659defm : T_QVV_pat <V6_vgtuw_or, int_hexagon_V6_vgtuw_or>; 660defm : T_QVV_pat <V6_veqb_xor, int_hexagon_V6_veqb_xor>; 661defm : T_QVV_pat <V6_veqh_xor, int_hexagon_V6_veqh_xor>; 662defm : T_QVV_pat <V6_veqw_xor, int_hexagon_V6_veqw_xor>; 663defm : T_QVV_pat <V6_vgtb_xor, int_hexagon_V6_vgtb_xor>; 664defm : T_QVV_pat <V6_vgth_xor, int_hexagon_V6_vgth_xor>; 665defm : T_QVV_pat <V6_vgtw_xor, int_hexagon_V6_vgtw_xor>; 666defm : T_QVV_pat <V6_vgtub_xor, int_hexagon_V6_vgtub_xor>; 667defm : T_QVV_pat <V6_vgtuh_xor, int_hexagon_V6_vgtuh_xor>; 668defm : T_QVV_pat <V6_vgtuw_xor, int_hexagon_V6_vgtuw_xor>; 669 670defm : T_VV_pat <V6_vminub, int_hexagon_V6_vminub>; 671defm : T_VV_pat <V6_vminuh, int_hexagon_V6_vminuh>; 672defm : T_VV_pat <V6_vminh, int_hexagon_V6_vminh>; 673defm : T_VV_pat <V6_vminw, int_hexagon_V6_vminw>; 674defm : T_VV_pat <V6_vmaxub, int_hexagon_V6_vmaxub>; 675defm : T_VV_pat <V6_vmaxuh, int_hexagon_V6_vmaxuh>; 676defm : T_VV_pat <V6_vmaxh, int_hexagon_V6_vmaxh>; 677defm : T_VV_pat <V6_vmaxw, int_hexagon_V6_vmaxw>; 678defm : T_VV_pat <V6_vdelta, int_hexagon_V6_vdelta>; 679defm : T_VV_pat <V6_vrdelta, int_hexagon_V6_vrdelta>; 680defm : T_VV_pat <V6_vdealb4w, int_hexagon_V6_vdealb4w>; 681defm : T_VV_pat <V6_vmpyowh_rnd, int_hexagon_V6_vmpyowh_rnd>; 682defm : T_VV_pat <V6_vshuffeb, int_hexagon_V6_vshuffeb>; 683defm : T_VV_pat <V6_vshuffob, int_hexagon_V6_vshuffob>; 684defm : T_VV_pat <V6_vshufeh, int_hexagon_V6_vshufeh>; 685defm : T_VV_pat <V6_vshufoh, int_hexagon_V6_vshufoh>; 686defm : T_VV_pat <V6_vshufoeh, int_hexagon_V6_vshufoeh>; 687defm : T_VV_pat <V6_vshufoeb, int_hexagon_V6_vshufoeb>; 688defm : T_VV_pat <V6_vcombine, int_hexagon_V6_vcombine>; 689defm : T_VV_pat <V6_vmpyieoh, int_hexagon_V6_vmpyieoh>; 690defm : T_VV_pat <V6_vsathub, int_hexagon_V6_vsathub>; 691defm : T_VV_pat <V6_vsatwh, int_hexagon_V6_vsatwh>; 692defm : T_VV_pat <V6_vroundwh, int_hexagon_V6_vroundwh>; 693defm : T_VV_pat <V6_vroundwuh, int_hexagon_V6_vroundwuh>; 694defm : T_VV_pat <V6_vroundhb, int_hexagon_V6_vroundhb>; 695defm : T_VV_pat <V6_vroundhub, int_hexagon_V6_vroundhub>; 696defm : T_VV_pat <V6_vasrwv, int_hexagon_V6_vasrwv>; 697defm : T_VV_pat <V6_vlsrwv, int_hexagon_V6_vlsrwv>; 698defm : T_VV_pat <V6_vlsrhv, int_hexagon_V6_vlsrhv>; 699defm : T_VV_pat <V6_vasrhv, int_hexagon_V6_vasrhv>; 700defm : T_VV_pat <V6_vaslwv, int_hexagon_V6_vaslwv>; 701defm : T_VV_pat <V6_vaslhv, int_hexagon_V6_vaslhv>; 702defm : T_VV_pat <V6_vaddb, int_hexagon_V6_vaddb>; 703defm : T_VV_pat <V6_vaddh, int_hexagon_V6_vaddh>; 704defm : T_VV_pat <V6_vmpyiewuh, int_hexagon_V6_vmpyiewuh>; 705defm : T_VV_pat <V6_vmpyiowh, int_hexagon_V6_vmpyiowh>; 706defm : T_VV_pat <V6_vpackeb, int_hexagon_V6_vpackeb>; 707defm : T_VV_pat <V6_vpackeh, int_hexagon_V6_vpackeh>; 708defm : T_VV_pat <V6_vpackhub_sat, int_hexagon_V6_vpackhub_sat>; 709defm : T_VV_pat <V6_vpackhb_sat, int_hexagon_V6_vpackhb_sat>; 710defm : T_VV_pat <V6_vpackwuh_sat, int_hexagon_V6_vpackwuh_sat>; 711defm : T_VV_pat <V6_vpackwh_sat, int_hexagon_V6_vpackwh_sat>; 712defm : T_VV_pat <V6_vpackob, int_hexagon_V6_vpackob>; 713defm : T_VV_pat <V6_vpackoh, int_hexagon_V6_vpackoh>; 714defm : T_VV_pat <V6_vmpyewuh, int_hexagon_V6_vmpyewuh>; 715defm : T_VV_pat <V6_vmpyowh, int_hexagon_V6_vmpyowh>; 716 717defm : T_QVV_pat <V6_vaddbq, int_hexagon_V6_vaddbq>; 718defm : T_QVV_pat <V6_vaddhq, int_hexagon_V6_vaddhq>; 719defm : T_QVV_pat <V6_vaddwq, int_hexagon_V6_vaddwq>; 720defm : T_QVV_pat <V6_vaddbnq, int_hexagon_V6_vaddbnq>; 721defm : T_QVV_pat <V6_vaddhnq, int_hexagon_V6_vaddhnq>; 722defm : T_QVV_pat <V6_vaddwnq, int_hexagon_V6_vaddwnq>; 723defm : T_QVV_pat <V6_vsubbq, int_hexagon_V6_vsubbq>; 724defm : T_QVV_pat <V6_vsubhq, int_hexagon_V6_vsubhq>; 725defm : T_QVV_pat <V6_vsubwq, int_hexagon_V6_vsubwq>; 726defm : T_QVV_pat <V6_vsubbnq, int_hexagon_V6_vsubbnq>; 727defm : T_QVV_pat <V6_vsubhnq, int_hexagon_V6_vsubhnq>; 728defm : T_QVV_pat <V6_vsubwnq, int_hexagon_V6_vsubwnq>; 729 730defm : T_V_pat <V6_vabsh, int_hexagon_V6_vabsh>; 731defm : T_V_pat <V6_vabsw, int_hexagon_V6_vabsw>; 732defm : T_V_pat <V6_vabsw_sat, int_hexagon_V6_vabsw_sat>; 733defm : T_V_pat <V6_vabsh_sat, int_hexagon_V6_vabsh_sat>; 734defm : T_V_pat <V6_vnot, int_hexagon_V6_vnot>; 735defm : T_V_pat <V6_vassign, int_hexagon_V6_vassign>; 736defm : T_V_pat <V6_vzb, int_hexagon_V6_vzb>; 737defm : T_V_pat <V6_vzh, int_hexagon_V6_vzh>; 738defm : T_V_pat <V6_vsb, int_hexagon_V6_vsb>; 739defm : T_V_pat <V6_vsh, int_hexagon_V6_vsh>; 740defm : T_V_pat <V6_vdealh, int_hexagon_V6_vdealh>; 741defm : T_V_pat <V6_vdealb, int_hexagon_V6_vdealb>; 742defm : T_V_pat <V6_vunpackub, int_hexagon_V6_vunpackub>; 743defm : T_V_pat <V6_vunpackuh, int_hexagon_V6_vunpackuh>; 744defm : T_V_pat <V6_vunpackb, int_hexagon_V6_vunpackb>; 745defm : T_V_pat <V6_vunpackh, int_hexagon_V6_vunpackh>; 746defm : T_V_pat <V6_vshuffh, int_hexagon_V6_vshuffh>; 747defm : T_V_pat <V6_vshuffb, int_hexagon_V6_vshuffb>; 748defm : T_V_pat <V6_vcl0w, int_hexagon_V6_vcl0w>; 749defm : T_V_pat <V6_vpopcounth, int_hexagon_V6_vpopcounth>; 750defm : T_V_pat <V6_vcl0h, int_hexagon_V6_vcl0h>; 751defm : T_V_pat <V6_vnormamtw, int_hexagon_V6_vnormamtw>; 752defm : T_V_pat <V6_vnormamth, int_hexagon_V6_vnormamth>; 753 754defm : T_WRI_pat <V6_vrmpybusi, int_hexagon_V6_vrmpybusi>; 755defm : T_WRI_pat <V6_vrsadubi, int_hexagon_V6_vrsadubi>; 756defm : T_WRI_pat <V6_vrmpyubi, int_hexagon_V6_vrmpyubi>; 757 758defm : T_WWRI_pat <V6_vrmpybusi_acc, int_hexagon_V6_vrmpybusi_acc>; 759defm : T_WWRI_pat <V6_vrsadubi_acc, int_hexagon_V6_vrsadubi_acc>; 760defm : T_WWRI_pat <V6_vrmpyubi_acc, int_hexagon_V6_vrmpyubi_acc>; 761 762// assembler mapped. 763//defm : T_V_pat <V6_vtran2x2, int_hexagon_V6_vtran2x2>; 764// not present earlier.. need to add intrinsic 765defm : T_VVR_pat <V6_valignb, int_hexagon_V6_valignb>; 766defm : T_VVR_pat <V6_vlalignb, int_hexagon_V6_vlalignb>; 767defm : T_VVR_pat <V6_vasrwh, int_hexagon_V6_vasrwh>; 768defm : T_VVR_pat <V6_vasrwhsat, int_hexagon_V6_vasrwhsat>; 769defm : T_VVR_pat <V6_vasrwhrndsat, int_hexagon_V6_vasrwhrndsat>; 770defm : T_VVR_pat <V6_vasrwuhsat, int_hexagon_V6_vasrwuhsat>; 771defm : T_VVR_pat <V6_vasrhubsat, int_hexagon_V6_vasrhubsat>; 772defm : T_VVR_pat <V6_vasrhubrndsat, int_hexagon_V6_vasrhubrndsat>; 773defm : T_VVR_pat <V6_vasrhbrndsat, int_hexagon_V6_vasrhbrndsat>; 774 775defm : T_VVR_pat <V6_vshuffvdd, int_hexagon_V6_vshuffvdd>; 776defm : T_VVR_pat <V6_vdealvdd, int_hexagon_V6_vdealvdd>; 777 778defm : T_WV_pat <V6_vunpackob, int_hexagon_V6_vunpackob>; 779defm : T_WV_pat <V6_vunpackoh, int_hexagon_V6_vunpackoh>; 780defm : T_VVI_pat <V6_valignbi, int_hexagon_V6_valignbi>; 781defm : T_VVI_pat <V6_vlalignbi, int_hexagon_V6_vlalignbi>; 782 783defm : T_QVV_pat <V6_vswap, int_hexagon_V6_vswap>; 784defm : T_QVV_pat <V6_vmux, int_hexagon_V6_vmux>; 785defm : T_QQ_pat <V6_pred_and, int_hexagon_V6_pred_and>; 786defm : T_QQ_pat <V6_pred_or, int_hexagon_V6_pred_or>; 787defm : T_Q_pat <V6_pred_not, int_hexagon_V6_pred_not>; 788defm : T_QQ_pat <V6_pred_xor, int_hexagon_V6_pred_xor>; 789defm : T_QQ_pat <V6_pred_or_n, int_hexagon_V6_pred_or_n>; 790defm : T_QQ_pat <V6_pred_and_n, int_hexagon_V6_pred_and_n>; 791defm : T_VV_pat <V6_veqb, int_hexagon_V6_veqb>; 792defm : T_VV_pat <V6_veqh, int_hexagon_V6_veqh>; 793defm : T_VV_pat <V6_veqw, int_hexagon_V6_veqw>; 794defm : T_VV_pat <V6_vgtb, int_hexagon_V6_vgtb>; 795defm : T_VV_pat <V6_vgth, int_hexagon_V6_vgth>; 796defm : T_VV_pat <V6_vgtw, int_hexagon_V6_vgtw>; 797defm : T_VV_pat <V6_vgtub, int_hexagon_V6_vgtub>; 798defm : T_VV_pat <V6_vgtuh, int_hexagon_V6_vgtuh>; 799defm : T_VV_pat <V6_vgtuw, int_hexagon_V6_vgtuw>; 800 801defm : T_VQR_pat <V6_vandqrt_acc, int_hexagon_V6_vandqrt_acc>; 802defm : T_QVR_pat <V6_vandvrt_acc, int_hexagon_V6_vandvrt_acc>; 803defm : T_QR_pat <V6_vandqrt, int_hexagon_V6_vandqrt>; 804defm : T_R_pat <V6_lvsplatw, int_hexagon_V6_lvsplatw>; 805defm : T_R_pat <V6_pred_scalar2, int_hexagon_V6_pred_scalar2>; 806defm : T_VR_pat <V6_vandvrt, int_hexagon_V6_vandvrt>; 807 808defm : T_VVR_pat <V6_vlutvvb, int_hexagon_V6_vlutvvb>; 809defm : T_VVR_pat <V6_vlutvwh, int_hexagon_V6_vlutvwh>; 810defm : T_VVVR_pat <V6_vlutvvb_oracc, int_hexagon_V6_vlutvvb_oracc>; 811defm : T_WVVR_pat <V6_vlutvwh_oracc, int_hexagon_V6_vlutvwh_oracc>; 812 813defm : T_QVR_pat <V6_vandvrt_acc, int_hexagon_V6_vandvrt_acc>; 814def : T_PI_pat <S6_rol_i_p, int_hexagon_S6_rol_i_p>; 815def : T_RI_pat <S6_rol_i_r, int_hexagon_S6_rol_i_r>; 816def : T_PPI_pat <S6_rol_i_p_nac, int_hexagon_S6_rol_i_p_nac>; 817def : T_PPI_pat <S6_rol_i_p_acc, int_hexagon_S6_rol_i_p_acc>; 818def : T_PPI_pat <S6_rol_i_p_and, int_hexagon_S6_rol_i_p_and>; 819def : T_PPI_pat <S6_rol_i_p_or, int_hexagon_S6_rol_i_p_or>; 820def : T_PPI_pat <S6_rol_i_p_xacc, int_hexagon_S6_rol_i_p_xacc>; 821def : T_RRI_pat <S6_rol_i_r_nac, int_hexagon_S6_rol_i_r_nac>; 822def : T_RRI_pat <S6_rol_i_r_acc, int_hexagon_S6_rol_i_r_acc>; 823def : T_RRI_pat <S6_rol_i_r_and, int_hexagon_S6_rol_i_r_and>; 824def : T_RRI_pat <S6_rol_i_r_or, int_hexagon_S6_rol_i_r_or>; 825def : T_RRI_pat <S6_rol_i_r_xacc, int_hexagon_S6_rol_i_r_xacc>; 826 827defm : T_VR_pat <V6_extractw, int_hexagon_V6_extractw>; 828defm : T_VR_pat <V6_vinsertwr, int_hexagon_V6_vinsertwr>; 829 830def : T_PPQ_pat <S2_cabacencbin, int_hexagon_S2_cabacencbin>; 831 832def: Pat<(v64i16 (trunc v64i32:$Vdd)), 833 (v64i16 (V6_vpackwh_sat_128B 834 (v32i32 (HEXAGON_V6_hi_128B VecDblRegs128B:$Vdd)), 835 (v32i32 (HEXAGON_V6_lo_128B VecDblRegs128B:$Vdd))))>, 836 Requires<[UseHVXDbl]>; 837 838 839