Lines Matching refs:v1024i1
124 def : Pat <(v1024i1 (bitconvert (v32i32 VectorRegs128B:$src1))),
125 (v1024i1 (V6_vandvrt_128B(v32i32 VectorRegs128B:$src1),
129 def : Pat <(v1024i1 (bitconvert (v64i16 VectorRegs128B:$src1))),
130 (v1024i1 (V6_vandvrt_128B(v64i16 VectorRegs128B:$src1),
134 def : Pat <(v1024i1 (bitconvert (v128i8 VectorRegs128B:$src1))),
135 (v1024i1 (V6_vandvrt_128B(v128i8 VectorRegs128B:$src1),
139 def : Pat <(v1024i1 (bitconvert (v16i64 VectorRegs128B:$src1))),
140 (v1024i1 (V6_vandvrt_128B(v16i64 VectorRegs128B:$src1),
144 def : Pat <(v32i32 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
145 (v32i32 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
149 def : Pat <(v64i16 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
150 (v64i16 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
154 def : Pat <(v128i8 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
155 (v128i8 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
159 def : Pat <(v16i64 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
160 (v16i64 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
176 def : Pat <(store (v1024i1 VecPredRegs128B:$src1), (i32 IntRegs:$addr)),
178 (v32i32 (V6_vandqrt_128B (v1024i1 VecPredRegs128B:$src1),
182 def : Pat <(v1024i1 (load (i32 IntRegs:$addr))),
183 (v1024i1 (V6_vandvrt_128B