Lines Matching full:offset
967 <reg32 offset="0x0800" name="CP_RB_BASE"/>
968 <reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
969 <reg32 offset="0x0802" name="CP_RB_CNTL"/>
970 <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR_LO"/>
971 <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
972 <reg32 offset="0x0806" name="CP_RB_RPTR"/>
973 <reg32 offset="0x0807" name="CP_RB_WPTR"/>
974 <reg32 offset="0x0808" name="CP_SQE_CNTL"/>
975 <reg32 offset="0x0812" name="CP_CP2GMU_STATUS">
978 <reg32 offset="0x0821" name="CP_HW_FAULT"/>
979 <reg32 offset="0x0823" name="CP_INTERRUPT_STATUS"/>
980 <reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>
981 <reg32 offset="0x0830" name="CP_SQE_INSTR_BASE_LO"/>
982 <reg32 offset="0x0831" name="CP_SQE_INSTR_BASE_HI"/>
983 <reg32 offset="0x0840" name="CP_MISC_CNTL"/>
984 <reg32 offset="0x0844" name="CP_APRIV_CNTL"/>
986 <reg32 offset="0x08C1" name="CP_ROQ_THRESHOLDS_1">
1001 <reg32 offset="0x08C2" name="CP_ROQ_THRESHOLDS_2">
1017 <reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE"/>
1018 <reg32 offset="0x0841" name="CP_CHICKEN_DBG"/>
1019 <reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1020 <reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/>
1021 <reg32 offset="0x084F" name="CP_PROTECT_CNTL"/>
1023 <array offset="0x0883" name="CP_SCRATCH" stride="1" length="8">
1024 <reg32 offset="0x0" name="REG" type="uint"/>
1026 <array offset="0x0850" name="CP_PROTECT" stride="1" length="32">
1027 <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
1030 <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/>
1031 <reg32 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO_LO"/>
1032 <reg32 offset="0x08A2" name="CP_CONTEXT_SWITCH_SMMU_INFO_HI"/>
1033 <reg32 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO"/>
1034 <reg32 offset="0x08A4" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI"/>
1035 <reg32 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO"/>
1036 <reg32 offset="0x08A6" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI"/>
1037 <reg32 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO"/>
1038 <reg32 offset="0x08A8" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI"/>
1039 <reg32 offset="0x08D0" name="CP_PERFCTR_CP_SEL_0"/>
1040 <reg32 offset="0x08D1" name="CP_PERFCTR_CP_SEL_1"/>
1041 <reg32 offset="0x08D2" name="CP_PERFCTR_CP_SEL_2"/>
1042 <reg32 offset="0x08D3" name="CP_PERFCTR_CP_SEL_3"/>
1043 <reg32 offset="0x08D4" name="CP_PERFCTR_CP_SEL_4"/>
1044 <reg32 offset="0x08D5" name="CP_PERFCTR_CP_SEL_5"/>
1045 <reg32 offset="0x08D6" name="CP_PERFCTR_CP_SEL_6"/>
1046 <reg32 offset="0x08D7" name="CP_PERFCTR_CP_SEL_7"/>
1047 <reg32 offset="0x08D8" name="CP_PERFCTR_CP_SEL_8"/>
1048 <reg32 offset="0x08D9" name="CP_PERFCTR_CP_SEL_9"/>
1049 <reg32 offset="0x08DA" name="CP_PERFCTR_CP_SEL_10"/>
1050 <reg32 offset="0x08DB" name="CP_PERFCTR_CP_SEL_11"/>
1051 <reg32 offset="0x08DC" name="CP_PERFCTR_CP_SEL_12"/>
1052 <reg32 offset="0x08DD" name="CP_PERFCTR_CP_SEL_13"/>
1053 <reg32 offset="0x0900" name="CP_CRASH_SCRIPT_BASE_LO"/>
1054 <reg32 offset="0x0901" name="CP_CRASH_SCRIPT_BASE_HI"/>
1055 <reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/>
1056 <reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/>
1057 <reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/>
1058 <reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/>
1059 <reg32 offset="0x090A" name="CP_DRAW_STATE_ADDR"/>
1060 <reg32 offset="0x090B" name="CP_DRAW_STATE_DATA"/>
1061 <reg32 offset="0x090C" name="CP_ROQ_DBG_ADDR"/>
1062 <reg32 offset="0x090D" name="CP_ROQ_DBG_DATA"/>
1063 <reg32 offset="0x090E" name="CP_MEM_POOL_DBG_ADDR"/>
1064 <reg32 offset="0x090F" name="CP_MEM_POOL_DBG_DATA"/>
1065 <reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/>
1066 <reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/>
1067 <reg32 offset="0x0928" name="CP_IB1_BASE"/>
1068 <reg32 offset="0x0929" name="CP_IB1_BASE_HI"/>
1069 <reg32 offset="0x092A" name="CP_IB1_REM_SIZE"/>
1070 <reg32 offset="0x092B" name="CP_IB2_BASE"/>
1071 <reg32 offset="0x092C" name="CP_IB2_BASE_HI"/>
1072 <reg32 offset="0x092D" name="CP_IB2_REM_SIZE"/>
1074 <reg32 offset="0x092e" name="CP_SDS_BASE"/>
1075 <reg32 offset="0x092f" name="CP_SDS_BASE_HI"/>
1076 <reg32 offset="0x0930" name="CP_SDS_REM_SIZE"/>
1078 <reg32 offset="0x0931" name="CP_MRB_BASE"/>
1079 <reg32 offset="0x0932" name="CP_MRB_BASE_HI"/>
1080 <reg32 offset="0x0933" name="CP_MRB_REM_SIZE"/>
1085 <reg32 offset="0x0934" name="CP_VSD_BASE"/>
1086 <reg32 offset="0x0935" name="CP_VSD_BASE_HI"/>
1087 <reg32 offset="0x0946" name="CP_MRB_DWORDS"/>
1088 <reg32 offset="0x0947" name="CP_VSD_DWORDS"/>
1093 <reg32 offset="0x0949" name="CP_CSQ_IB1_STAT">
1097 <reg32 offset="0x094a" name="CP_CSQ_IB2_STAT">
1101 <reg32 offset="0x094c" name="CP_MRQ_MRB_STAT">
1105 <reg32 offset="0x0980" name="CP_ALWAYS_ON_COUNTER_LO"/>
1106 <reg32 offset="0x0981" name="CP_ALWAYS_ON_COUNTER_HI"/>
1107 <reg32 offset="0x098D" name="CP_AHB_CNTL"/>
1108 <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST"/>
1109 <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD"/>
1110 <reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1111 <reg32 offset="0x0201" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK"/>
1112 <reg32 offset="0x0210" name="RBBM_STATUS">
1138 <reg32 offset="0x0213" name="RBBM_STATUS3">
1141 <reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/>
1142 <reg32 offset="0x0400" name="RBBM_PERFCTR_CP_0_LO"/>
1143 <reg32 offset="0x0401" name="RBBM_PERFCTR_CP_0_HI"/>
1144 <reg32 offset="0x0402" name="RBBM_PERFCTR_CP_1_LO"/>
1145 <reg32 offset="0x0403" name="RBBM_PERFCTR_CP_1_HI"/>
1146 <reg32 offset="0x0404" name="RBBM_PERFCTR_CP_2_LO"/>
1147 <reg32 offset="0x0405" name="RBBM_PERFCTR_CP_2_HI"/>
1148 <reg32 offset="0x0406" name="RBBM_PERFCTR_CP_3_LO"/>
1149 <reg32 offset="0x0407" name="RBBM_PERFCTR_CP_3_HI"/>
1150 <reg32 offset="0x0408" name="RBBM_PERFCTR_CP_4_LO"/>
1151 <reg32 offset="0x0409" name="RBBM_PERFCTR_CP_4_HI"/>
1152 <reg32 offset="0x040a" name="RBBM_PERFCTR_CP_5_LO"/>
1153 <reg32 offset="0x040b" name="RBBM_PERFCTR_CP_5_HI"/>
1154 <reg32 offset="0x040c" name="RBBM_PERFCTR_CP_6_LO"/>
1155 <reg32 offset="0x040d" name="RBBM_PERFCTR_CP_6_HI"/>
1156 <reg32 offset="0x040e" name="RBBM_PERFCTR_CP_7_LO"/>
1157 <reg32 offset="0x040f" name="RBBM_PERFCTR_CP_7_HI"/>
1158 <reg32 offset="0x0410" name="RBBM_PERFCTR_CP_8_LO"/>
1159 <reg32 offset="0x0411" name="RBBM_PERFCTR_CP_8_HI"/>
1160 <reg32 offset="0x0412" name="RBBM_PERFCTR_CP_9_LO"/>
1161 <reg32 offset="0x0413" name="RBBM_PERFCTR_CP_9_HI"/>
1162 <reg32 offset="0x0414" name="RBBM_PERFCTR_CP_10_LO"/>
1163 <reg32 offset="0x0415" name="RBBM_PERFCTR_CP_10_HI"/>
1164 <reg32 offset="0x0416" name="RBBM_PERFCTR_CP_11_LO"/>
1165 <reg32 offset="0x0417" name="RBBM_PERFCTR_CP_11_HI"/>
1166 <reg32 offset="0x0418" name="RBBM_PERFCTR_CP_12_LO"/>
1167 <reg32 offset="0x0419" name="RBBM_PERFCTR_CP_12_HI"/>
1168 <reg32 offset="0x041a" name="RBBM_PERFCTR_CP_13_LO"/>
1169 <reg32 offset="0x041b" name="RBBM_PERFCTR_CP_13_HI"/>
1170 <reg32 offset="0x041c" name="RBBM_PERFCTR_RBBM_0_LO"/>
1171 <reg32 offset="0x041d" name="RBBM_PERFCTR_RBBM_0_HI"/>
1172 <reg32 offset="0x041e" name="RBBM_PERFCTR_RBBM_1_LO"/>
1173 <reg32 offset="0x041f" name="RBBM_PERFCTR_RBBM_1_HI"/>
1174 <reg32 offset="0x0420" name="RBBM_PERFCTR_RBBM_2_LO"/>
1175 <reg32 offset="0x0421" name="RBBM_PERFCTR_RBBM_2_HI"/>
1176 <reg32 offset="0x0422" name="RBBM_PERFCTR_RBBM_3_LO"/>
1177 <reg32 offset="0x0423" name="RBBM_PERFCTR_RBBM_3_HI"/>
1178 <reg32 offset="0x0424" name="RBBM_PERFCTR_PC_0_LO"/>
1179 <reg32 offset="0x0425" name="RBBM_PERFCTR_PC_0_HI"/>
1180 <reg32 offset="0x0426" name="RBBM_PERFCTR_PC_1_LO"/>
1181 <reg32 offset="0x0427" name="RBBM_PERFCTR_PC_1_HI"/>
1182 <reg32 offset="0x0428" name="RBBM_PERFCTR_PC_2_LO"/>
1183 <reg32 offset="0x0429" name="RBBM_PERFCTR_PC_2_HI"/>
1184 <reg32 offset="0x042a" name="RBBM_PERFCTR_PC_3_LO"/>
1185 <reg32 offset="0x042b" name="RBBM_PERFCTR_PC_3_HI"/>
1186 <reg32 offset="0x042c" name="RBBM_PERFCTR_PC_4_LO"/>
1187 <reg32 offset="0x042d" name="RBBM_PERFCTR_PC_4_HI"/>
1188 <reg32 offset="0x042e" name="RBBM_PERFCTR_PC_5_LO"/>
1189 <reg32 offset="0x042f" name="RBBM_PERFCTR_PC_5_HI"/>
1190 <reg32 offset="0x0430" name="RBBM_PERFCTR_PC_6_LO"/>
1191 <reg32 offset="0x0431" name="RBBM_PERFCTR_PC_6_HI"/>
1192 <reg32 offset="0x0432" name="RBBM_PERFCTR_PC_7_LO"/>
1193 <reg32 offset="0x0433" name="RBBM_PERFCTR_PC_7_HI"/>
1194 <reg32 offset="0x0434" name="RBBM_PERFCTR_VFD_0_LO"/>
1195 <reg32 offset="0x0435" name="RBBM_PERFCTR_VFD_0_HI"/>
1196 <reg32 offset="0x0436" name="RBBM_PERFCTR_VFD_1_LO"/>
1197 <reg32 offset="0x0437" name="RBBM_PERFCTR_VFD_1_HI"/>
1198 <reg32 offset="0x0438" name="RBBM_PERFCTR_VFD_2_LO"/>
1199 <reg32 offset="0x0439" name="RBBM_PERFCTR_VFD_2_HI"/>
1200 <reg32 offset="0x043a" name="RBBM_PERFCTR_VFD_3_LO"/>
1201 <reg32 offset="0x043b" name="RBBM_PERFCTR_VFD_3_HI"/>
1202 <reg32 offset="0x043c" name="RBBM_PERFCTR_VFD_4_LO"/>
1203 <reg32 offset="0x043d" name="RBBM_PERFCTR_VFD_4_HI"/>
1204 <reg32 offset="0x043e" name="RBBM_PERFCTR_VFD_5_LO"/>
1205 <reg32 offset="0x043f" name="RBBM_PERFCTR_VFD_5_HI"/>
1206 <reg32 offset="0x0440" name="RBBM_PERFCTR_VFD_6_LO"/>
1207 <reg32 offset="0x0441" name="RBBM_PERFCTR_VFD_6_HI"/>
1208 <reg32 offset="0x0442" name="RBBM_PERFCTR_VFD_7_LO"/>
1209 <reg32 offset="0x0443" name="RBBM_PERFCTR_VFD_7_HI"/>
1210 <reg32 offset="0x0444" name="RBBM_PERFCTR_HLSQ_0_LO"/>
1211 <reg32 offset="0x0445" name="RBBM_PERFCTR_HLSQ_0_HI"/>
1212 <reg32 offset="0x0446" name="RBBM_PERFCTR_HLSQ_1_LO"/>
1213 <reg32 offset="0x0447" name="RBBM_PERFCTR_HLSQ_1_HI"/>
1214 <reg32 offset="0x0448" name="RBBM_PERFCTR_HLSQ_2_LO"/>
1215 <reg32 offset="0x0449" name="RBBM_PERFCTR_HLSQ_2_HI"/>
1216 <reg32 offset="0x044a" name="RBBM_PERFCTR_HLSQ_3_LO"/>
1217 <reg32 offset="0x044b" name="RBBM_PERFCTR_HLSQ_3_HI"/>
1218 <reg32 offset="0x044c" name="RBBM_PERFCTR_HLSQ_4_LO"/>
1219 <reg32 offset="0x044d" name="RBBM_PERFCTR_HLSQ_4_HI"/>
1220 <reg32 offset="0x044e" name="RBBM_PERFCTR_HLSQ_5_LO"/>
1221 <reg32 offset="0x044f" name="RBBM_PERFCTR_HLSQ_5_HI"/>
1222 <reg32 offset="0x0450" name="RBBM_PERFCTR_VPC_0_LO"/>
1223 <reg32 offset="0x0451" name="RBBM_PERFCTR_VPC_0_HI"/>
1224 <reg32 offset="0x0452" name="RBBM_PERFCTR_VPC_1_LO"/>
1225 <reg32 offset="0x0453" name="RBBM_PERFCTR_VPC_1_HI"/>
1226 <reg32 offset="0x0454" name="RBBM_PERFCTR_VPC_2_LO"/>
1227 <reg32 offset="0x0455" name="RBBM_PERFCTR_VPC_2_HI"/>
1228 <reg32 offset="0x0456" name="RBBM_PERFCTR_VPC_3_LO"/>
1229 <reg32 offset="0x0457" name="RBBM_PERFCTR_VPC_3_HI"/>
1230 <reg32 offset="0x0458" name="RBBM_PERFCTR_VPC_4_LO"/>
1231 <reg32 offset="0x0459" name="RBBM_PERFCTR_VPC_4_HI"/>
1232 <reg32 offset="0x045a" name="RBBM_PERFCTR_VPC_5_LO"/>
1233 <reg32 offset="0x045b" name="RBBM_PERFCTR_VPC_5_HI"/>
1234 <reg32 offset="0x045c" name="RBBM_PERFCTR_CCU_0_LO"/>
1235 <reg32 offset="0x045d" name="RBBM_PERFCTR_CCU_0_HI"/>
1236 <reg32 offset="0x045e" name="RBBM_PERFCTR_CCU_1_LO"/>
1237 <reg32 offset="0x045f" name="RBBM_PERFCTR_CCU_1_HI"/>
1238 <reg32 offset="0x0460" name="RBBM_PERFCTR_CCU_2_LO"/>
1239 <reg32 offset="0x0461" name="RBBM_PERFCTR_CCU_2_HI"/>
1240 <reg32 offset="0x0462" name="RBBM_PERFCTR_CCU_3_LO"/>
1241 <reg32 offset="0x0463" name="RBBM_PERFCTR_CCU_3_HI"/>
1242 <reg32 offset="0x0464" name="RBBM_PERFCTR_CCU_4_LO"/>
1243 <reg32 offset="0x0465" name="RBBM_PERFCTR_CCU_4_HI"/>
1244 <reg32 offset="0x0466" name="RBBM_PERFCTR_TSE_0_LO"/>
1245 <reg32 offset="0x0467" name="RBBM_PERFCTR_TSE_0_HI"/>
1246 <reg32 offset="0x0468" name="RBBM_PERFCTR_TSE_1_LO"/>
1247 <reg32 offset="0x0469" name="RBBM_PERFCTR_TSE_1_HI"/>
1248 <reg32 offset="0x046a" name="RBBM_PERFCTR_TSE_2_LO"/>
1249 <reg32 offset="0x046b" name="RBBM_PERFCTR_TSE_2_HI"/>
1250 <reg32 offset="0x046c" name="RBBM_PERFCTR_TSE_3_LO"/>
1251 <reg32 offset="0x046d" name="RBBM_PERFCTR_TSE_3_HI"/>
1252 <reg32 offset="0x046e" name="RBBM_PERFCTR_RAS_0_LO"/>
1253 <reg32 offset="0x046f" name="RBBM_PERFCTR_RAS_0_HI"/>
1254 <reg32 offset="0x0470" name="RBBM_PERFCTR_RAS_1_LO"/>
1255 <reg32 offset="0x0471" name="RBBM_PERFCTR_RAS_1_HI"/>
1256 <reg32 offset="0x0472" name="RBBM_PERFCTR_RAS_2_LO"/>
1257 <reg32 offset="0x0473" name="RBBM_PERFCTR_RAS_2_HI"/>
1258 <reg32 offset="0x0474" name="RBBM_PERFCTR_RAS_3_LO"/>
1259 <reg32 offset="0x0475" name="RBBM_PERFCTR_RAS_3_HI"/>
1260 <reg32 offset="0x0476" name="RBBM_PERFCTR_UCHE_0_LO"/>
1261 <reg32 offset="0x0477" name="RBBM_PERFCTR_UCHE_0_HI"/>
1262 <reg32 offset="0x0478" name="RBBM_PERFCTR_UCHE_1_LO"/>
1263 <reg32 offset="0x0479" name="RBBM_PERFCTR_UCHE_1_HI"/>
1264 <reg32 offset="0x047a" name="RBBM_PERFCTR_UCHE_2_LO"/>
1265 <reg32 offset="0x047b" name="RBBM_PERFCTR_UCHE_2_HI"/>
1266 <reg32 offset="0x047c" name="RBBM_PERFCTR_UCHE_3_LO"/>
1267 <reg32 offset="0x047d" name="RBBM_PERFCTR_UCHE_3_HI"/>
1268 <reg32 offset="0x047e" name="RBBM_PERFCTR_UCHE_4_LO"/>
1269 <reg32 offset="0x047f" name="RBBM_PERFCTR_UCHE_4_HI"/>
1270 <reg32 offset="0x0480" name="RBBM_PERFCTR_UCHE_5_LO"/>
1271 <reg32 offset="0x0481" name="RBBM_PERFCTR_UCHE_5_HI"/>
1272 <reg32 offset="0x0482" name="RBBM_PERFCTR_UCHE_6_LO"/>
1273 <reg32 offset="0x0483" name="RBBM_PERFCTR_UCHE_6_HI"/>
1274 <reg32 offset="0x0484" name="RBBM_PERFCTR_UCHE_7_LO"/>
1275 <reg32 offset="0x0485" name="RBBM_PERFCTR_UCHE_7_HI"/>
1276 <reg32 offset="0x0486" name="RBBM_PERFCTR_UCHE_8_LO"/>
1277 <reg32 offset="0x0487" name="RBBM_PERFCTR_UCHE_8_HI"/>
1278 <reg32 offset="0x0488" name="RBBM_PERFCTR_UCHE_9_LO"/>
1279 <reg32 offset="0x0489" name="RBBM_PERFCTR_UCHE_9_HI"/>
1280 <reg32 offset="0x048a" name="RBBM_PERFCTR_UCHE_10_LO"/>
1281 <reg32 offset="0x048b" name="RBBM_PERFCTR_UCHE_10_HI"/>
1282 <reg32 offset="0x048c" name="RBBM_PERFCTR_UCHE_11_LO"/>
1283 <reg32 offset="0x048d" name="RBBM_PERFCTR_UCHE_11_HI"/>
1284 <reg32 offset="0x048e" name="RBBM_PERFCTR_TP_0_LO"/>
1285 <reg32 offset="0x048f" name="RBBM_PERFCTR_TP_0_HI"/>
1286 <reg32 offset="0x0490" name="RBBM_PERFCTR_TP_1_LO"/>
1287 <reg32 offset="0x0491" name="RBBM_PERFCTR_TP_1_HI"/>
1288 <reg32 offset="0x0492" name="RBBM_PERFCTR_TP_2_LO"/>
1289 <reg32 offset="0x0493" name="RBBM_PERFCTR_TP_2_HI"/>
1290 <reg32 offset="0x0494" name="RBBM_PERFCTR_TP_3_LO"/>
1291 <reg32 offset="0x0495" name="RBBM_PERFCTR_TP_3_HI"/>
1292 <reg32 offset="0x0496" name="RBBM_PERFCTR_TP_4_LO"/>
1293 <reg32 offset="0x0497" name="RBBM_PERFCTR_TP_4_HI"/>
1294 <reg32 offset="0x0498" name="RBBM_PERFCTR_TP_5_LO"/>
1295 <reg32 offset="0x0499" name="RBBM_PERFCTR_TP_5_HI"/>
1296 <reg32 offset="0x049a" name="RBBM_PERFCTR_TP_6_LO"/>
1297 <reg32 offset="0x049b" name="RBBM_PERFCTR_TP_6_HI"/>
1298 <reg32 offset="0x049c" name="RBBM_PERFCTR_TP_7_LO"/>
1299 <reg32 offset="0x049d" name="RBBM_PERFCTR_TP_7_HI"/>
1300 <reg32 offset="0x049e" name="RBBM_PERFCTR_TP_8_LO"/>
1301 <reg32 offset="0x049f" name="RBBM_PERFCTR_TP_8_HI"/>
1302 <reg32 offset="0x04a0" name="RBBM_PERFCTR_TP_9_LO"/>
1303 <reg32 offset="0x04a1" name="RBBM_PERFCTR_TP_9_HI"/>
1304 <reg32 offset="0x04a2" name="RBBM_PERFCTR_TP_10_LO"/>
1305 <reg32 offset="0x04a3" name="RBBM_PERFCTR_TP_10_HI"/>
1306 <reg32 offset="0x04a4" name="RBBM_PERFCTR_TP_11_LO"/>
1307 <reg32 offset="0x04a5" name="RBBM_PERFCTR_TP_11_HI"/>
1308 <reg32 offset="0x04a6" name="RBBM_PERFCTR_SP_0_LO"/>
1309 <reg32 offset="0x04a7" name="RBBM_PERFCTR_SP_0_HI"/>
1310 <reg32 offset="0x04a8" name="RBBM_PERFCTR_SP_1_LO"/>
1311 <reg32 offset="0x04a9" name="RBBM_PERFCTR_SP_1_HI"/>
1312 <reg32 offset="0x04aa" name="RBBM_PERFCTR_SP_2_LO"/>
1313 <reg32 offset="0x04ab" name="RBBM_PERFCTR_SP_2_HI"/>
1314 <reg32 offset="0x04ac" name="RBBM_PERFCTR_SP_3_LO"/>
1315 <reg32 offset="0x04ad" name="RBBM_PERFCTR_SP_3_HI"/>
1316 <reg32 offset="0x04ae" name="RBBM_PERFCTR_SP_4_LO"/>
1317 <reg32 offset="0x04af" name="RBBM_PERFCTR_SP_4_HI"/>
1318 <reg32 offset="0x04b0" name="RBBM_PERFCTR_SP_5_LO"/>
1319 <reg32 offset="0x04b1" name="RBBM_PERFCTR_SP_5_HI"/>
1320 <reg32 offset="0x04b2" name="RBBM_PERFCTR_SP_6_LO"/>
1321 <reg32 offset="0x04b3" name="RBBM_PERFCTR_SP_6_HI"/>
1322 <reg32 offset="0x04b4" name="RBBM_PERFCTR_SP_7_LO"/>
1323 <reg32 offset="0x04b5" name="RBBM_PERFCTR_SP_7_HI"/>
1324 <reg32 offset="0x04b6" name="RBBM_PERFCTR_SP_8_LO"/>
1325 <reg32 offset="0x04b7" name="RBBM_PERFCTR_SP_8_HI"/>
1326 <reg32 offset="0x04b8" name="RBBM_PERFCTR_SP_9_LO"/>
1327 <reg32 offset="0x04b9" name="RBBM_PERFCTR_SP_9_HI"/>
1328 <reg32 offset="0x04ba" name="RBBM_PERFCTR_SP_10_LO"/>
1329 <reg32 offset="0x04bb" name="RBBM_PERFCTR_SP_10_HI"/>
1330 <reg32 offset="0x04bc" name="RBBM_PERFCTR_SP_11_LO"/>
1331 <reg32 offset="0x04bd" name="RBBM_PERFCTR_SP_11_HI"/>
1332 <reg32 offset="0x04be" name="RBBM_PERFCTR_SP_12_LO"/>
1333 <reg32 offset="0x04bf" name="RBBM_PERFCTR_SP_12_HI"/>
1334 <reg32 offset="0x04c0" name="RBBM_PERFCTR_SP_13_LO"/>
1335 <reg32 offset="0x04c1" name="RBBM_PERFCTR_SP_13_HI"/>
1336 <reg32 offset="0x04c2" name="RBBM_PERFCTR_SP_14_LO"/>
1337 <reg32 offset="0x04c3" name="RBBM_PERFCTR_SP_14_HI"/>
1338 <reg32 offset="0x04c4" name="RBBM_PERFCTR_SP_15_LO"/>
1339 <reg32 offset="0x04c5" name="RBBM_PERFCTR_SP_15_HI"/>
1340 <reg32 offset="0x04c6" name="RBBM_PERFCTR_SP_16_LO"/>
1341 <reg32 offset="0x04c7" name="RBBM_PERFCTR_SP_16_HI"/>
1342 <reg32 offset="0x04c8" name="RBBM_PERFCTR_SP_17_LO"/>
1343 <reg32 offset="0x04c9" name="RBBM_PERFCTR_SP_17_HI"/>
1344 <reg32 offset="0x04ca" name="RBBM_PERFCTR_SP_18_LO"/>
1345 <reg32 offset="0x04cb" name="RBBM_PERFCTR_SP_18_HI"/>
1346 <reg32 offset="0x04cc" name="RBBM_PERFCTR_SP_19_LO"/>
1347 <reg32 offset="0x04cd" name="RBBM_PERFCTR_SP_19_HI"/>
1348 <reg32 offset="0x04ce" name="RBBM_PERFCTR_SP_20_LO"/>
1349 <reg32 offset="0x04cf" name="RBBM_PERFCTR_SP_20_HI"/>
1350 <reg32 offset="0x04d0" name="RBBM_PERFCTR_SP_21_LO"/>
1351 <reg32 offset="0x04d1" name="RBBM_PERFCTR_SP_21_HI"/>
1352 <reg32 offset="0x04d2" name="RBBM_PERFCTR_SP_22_LO"/>
1353 <reg32 offset="0x04d3" name="RBBM_PERFCTR_SP_22_HI"/>
1354 <reg32 offset="0x04d4" name="RBBM_PERFCTR_SP_23_LO"/>
1355 <reg32 offset="0x04d5" name="RBBM_PERFCTR_SP_23_HI"/>
1356 <reg32 offset="0x04d6" name="RBBM_PERFCTR_RB_0_LO"/>
1357 <reg32 offset="0x04d7" name="RBBM_PERFCTR_RB_0_HI"/>
1358 <reg32 offset="0x04d8" name="RBBM_PERFCTR_RB_1_LO"/>
1359 <reg32 offset="0x04d9" name="RBBM_PERFCTR_RB_1_HI"/>
1360 <reg32 offset="0x04da" name="RBBM_PERFCTR_RB_2_LO"/>
1361 <reg32 offset="0x04db" name="RBBM_PERFCTR_RB_2_HI"/>
1362 <reg32 offset="0x04dc" name="RBBM_PERFCTR_RB_3_LO"/>
1363 <reg32 offset="0x04dd" name="RBBM_PERFCTR_RB_3_HI"/>
1364 <reg32 offset="0x04de" name="RBBM_PERFCTR_RB_4_LO"/>
1365 <reg32 offset="0x04df" name="RBBM_PERFCTR_RB_4_HI"/>
1366 <reg32 offset="0x04e0" name="RBBM_PERFCTR_RB_5_LO"/>
1367 <reg32 offset="0x04e1" name="RBBM_PERFCTR_RB_5_HI"/>
1368 <reg32 offset="0x04e2" name="RBBM_PERFCTR_RB_6_LO"/>
1369 <reg32 offset="0x04e3" name="RBBM_PERFCTR_RB_6_HI"/>
1370 <reg32 offset="0x04e4" name="RBBM_PERFCTR_RB_7_LO"/>
1371 <reg32 offset="0x04e5" name="RBBM_PERFCTR_RB_7_HI"/>
1372 <reg32 offset="0x04e6" name="RBBM_PERFCTR_VSC_0_LO"/>
1373 <reg32 offset="0x04e7" name="RBBM_PERFCTR_VSC_0_HI"/>
1374 <reg32 offset="0x04e8" name="RBBM_PERFCTR_VSC_1_LO"/>
1375 <reg32 offset="0x04e9" name="RBBM_PERFCTR_VSC_1_HI"/>
1376 <reg32 offset="0x04ea" name="RBBM_PERFCTR_LRZ_0_LO"/>
1377 <reg32 offset="0x04eb" name="RBBM_PERFCTR_LRZ_0_HI"/>
1378 <reg32 offset="0x04ec" name="RBBM_PERFCTR_LRZ_1_LO"/>
1379 <reg32 offset="0x04ed" name="RBBM_PERFCTR_LRZ_1_HI"/>
1380 <reg32 offset="0x04ee" name="RBBM_PERFCTR_LRZ_2_LO"/>
1381 <reg32 offset="0x04ef" name="RBBM_PERFCTR_LRZ_2_HI"/>
1382 <reg32 offset="0x04f0" name="RBBM_PERFCTR_LRZ_3_LO"/>
1383 <reg32 offset="0x04f1" name="RBBM_PERFCTR_LRZ_3_HI"/>
1384 <reg32 offset="0x04f2" name="RBBM_PERFCTR_CMP_0_LO"/>
1385 <reg32 offset="0x04f3" name="RBBM_PERFCTR_CMP_0_HI"/>
1386 <reg32 offset="0x04f4" name="RBBM_PERFCTR_CMP_1_LO"/>
1387 <reg32 offset="0x04f5" name="RBBM_PERFCTR_CMP_1_HI"/>
1388 <reg32 offset="0x04f6" name="RBBM_PERFCTR_CMP_2_LO"/>
1389 <reg32 offset="0x04f7" name="RBBM_PERFCTR_CMP_2_HI"/>
1390 <reg32 offset="0x04f8" name="RBBM_PERFCTR_CMP_3_LO"/>
1391 <reg32 offset="0x04f9" name="RBBM_PERFCTR_CMP_3_HI"/>
1392 <reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/>
1393 <reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/>
1394 <reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/>
1395 <reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2"/>
1396 <reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/>
1397 <reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
1398 <reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
1399 <reg32 offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL_0"/>
1400 <reg32 offset="0x0508" name="RBBM_PERFCTR_RBBM_SEL_1"/>
1401 <reg32 offset="0x0509" name="RBBM_PERFCTR_RBBM_SEL_2"/>
1402 <reg32 offset="0x050A" name="RBBM_PERFCTR_RBBM_SEL_3"/>
1403 <reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
1404 <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
1412 <reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/> <!-- vs vertices in -->
1413 <reg32 offset="0x0541" name="RBBM_PRIMCTR_0_HI"/>
1414 <reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/> <!-- vs primitives out -->
1415 <reg32 offset="0x0543" name="RBBM_PRIMCTR_1_HI"/>
1416 <reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/> <!-- hs vertices in -->
1417 <reg32 offset="0x0545" name="RBBM_PRIMCTR_2_HI"/>
1418 <reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/> <!-- hs patches out -->
1419 <reg32 offset="0x0547" name="RBBM_PRIMCTR_3_HI"/>
1420 <reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/> <!-- dss vertices in -->
1421 <reg32 offset="0x0549" name="RBBM_PRIMCTR_4_HI"/>
1422 <reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/> <!-- ds primitives out -->
1423 <reg32 offset="0x054b" name="RBBM_PRIMCTR_5_HI"/>
1424 <reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/> <!-- gs primitives in -->
1425 <reg32 offset="0x054d" name="RBBM_PRIMCTR_6_HI"/>
1426 <reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/> <!-- gs primitives out -->
1427 <reg32 offset="0x054f" name="RBBM_PRIMCTR_7_HI"/>
1428 <reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/> <!-- gs primitives out -->
1429 <reg32 offset="0x0551" name="RBBM_PRIMCTR_8_HI"/>
1430 <reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/> <!-- raster primitives in -->
1431 <reg32 offset="0x0553" name="RBBM_PRIMCTR_9_HI"/>
1432 <reg32 offset="0x0554" name="RBBM_PRIMCTR_10_LO"/>
1433 <reg32 offset="0x0555" name="RBBM_PRIMCTR_10_HI"/>
1435 <reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/>
1436 <reg32 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE_LO"/>
1437 <reg32 offset="0xF801" name="RBBM_SECVID_TSB_TRUSTED_BASE_HI"/>
1438 <reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
1439 <reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/>
1440 <reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1441 <reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/>
1442 <reg32 offset="0x00011" name="RBBM_GBIF_CLIENT_QOS_CNTL"/>
1443 <reg32 offset="0x0001c" name="RBBM_WAIT_FOR_GPU_IDLE_CMD">
1446 <reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
1447 <reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD" type="A6XX_RBBM_INT_0_MASK"/>
1448 <reg32 offset="0x00038" name="RBBM_INT_0_MASK"/>
1449 <reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/>
1450 <reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/>
1451 <reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/>
1452 <reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD"/>
1453 <reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2"/>
1454 <reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL"/>
1455 <reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0"/>
1456 <reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1"/>
1457 <reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2"/>
1458 <reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3"/>
1459 <reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0"/>
1460 <reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1"/>
1461 <reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2"/>
1462 <reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3"/>
1463 <reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0"/>
1464 <reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1"/>
1465 <reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2"/>
1466 <reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3"/>
1467 <reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0"/>
1468 <reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1"/>
1469 <reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2"/>
1470 <reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3"/>
1471 <reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0"/>
1472 <reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1"/>
1473 <reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2"/>
1474 <reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3"/>
1475 <reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0"/>
1476 <reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1"/>
1477 <reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2"/>
1478 <reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3"/>
1479 <reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0"/>
1480 <reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1"/>
1481 <reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2"/>
1482 <reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3"/>
1483 <reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0"/>
1484 <reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1"/>
1485 <reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2"/>
1486 <reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3"/>
1487 <reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0"/>
1488 <reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1"/>
1489 <reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2"/>
1490 <reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3"/>
1491 <reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0"/>
1492 <reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1"/>
1493 <reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2"/>
1494 <reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3"/>
1495 <reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0"/>
1496 <reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1"/>
1497 <reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2"/>
1498 <reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3"/>
1499 <reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0"/>
1500 <reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1"/>
1501 <reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2"/>
1502 <reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3"/>
1503 <reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0"/>
1504 <reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1"/>
1505 <reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2"/>
1506 <reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3"/>
1507 <reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0"/>
1508 <reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1"/>
1509 <reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2"/>
1510 <reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3"/>
1511 <reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0"/>
1512 <reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1"/>
1513 <reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2"/>
1514 <reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3"/>
1515 <reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0"/>
1516 <reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1"/>
1517 <reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2"/>
1518 <reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3"/>
1519 <reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0"/>
1520 <reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1"/>
1521 <reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2"/>
1522 <reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3"/>
1523 <reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0"/>
1524 <reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1"/>
1525 <reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2"/>
1526 <reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3"/>
1527 <reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0"/>
1528 <reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1"/>
1529 <reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2"/>
1530 <reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3"/>
1531 <reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0"/>
1532 <reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1"/>
1533 <reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2"/>
1534 <reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3"/>
1535 <reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC"/>
1536 <reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC"/>
1537 <reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC"/>
1538 <reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC"/>
1539 <reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
1540 <reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
1541 <reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
1542 <reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE"/>
1543 <reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE"/>
1544 <reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE"/>
1545 <reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE"/>
1546 <reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE"/>
1547 <reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE"/>
1548 <reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD"/>
1549 <reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD"/>
1550 <reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD"/>
1551 <reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC"/>
1552 <reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC"/>
1553 <reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC"/>
1554 <reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2"/>
1555 <reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX"/>
1556 <reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX"/>
1557 <reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX"/>
1558 <reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ"/>
1559 <reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ"/>
1560 <reg32 offset="0x0011d" name="RBBM_CLOCK_HYST_HLSQ"/>
1561 <reg32 offset="0x00120" name="RBBM_CLOCK_CNTL_TEX_FCHE"/>
1562 <reg32 offset="0x00121" name="RBBM_CLOCK_DELAY_TEX_FCHE"/>
1563 <reg32 offset="0x00122" name="RBBM_CLOCK_HYST_TEX_FCHE"/>
1565 <reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/>
1566 <reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/>
1567 <reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/>
1568 <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D">
1572 <reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT">
1577 <reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM">
1580 <reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/>
1581 <reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/>
1582 <reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/>
1583 <reg32 offset="0x060b" name="DBGC_CFG_DBGBUS_IVTL_3"/>
1584 <reg32 offset="0x060c" name="DBGC_CFG_DBGBUS_MASKL_0"/>
1585 <reg32 offset="0x060d" name="DBGC_CFG_DBGBUS_MASKL_1"/>
1586 <reg32 offset="0x060e" name="DBGC_CFG_DBGBUS_MASKL_2"/>
1587 <reg32 offset="0x060f" name="DBGC_CFG_DBGBUS_MASKL_3"/>
1588 <reg32 offset="0x0610" name="DBGC_CFG_DBGBUS_BYTEL_0">
1598 <reg32 offset="0x0611" name="DBGC_CFG_DBGBUS_BYTEL_1">
1608 <reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/>
1609 <reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/>
1610 <reg32 offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL_0"/>
1611 <reg32 offset="0x0CD9" name="VSC_PERFCTR_VSC_SEL_1"/>
1612 <reg32 offset="0xBE05" name="HLSQ_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1613 <reg32 offset="0xBE10" name="HLSQ_PERFCTR_HLSQ_SEL_0"/>
1614 <reg32 offset="0xBE11" name="HLSQ_PERFCTR_HLSQ_SEL_1"/>
1615 <reg32 offset="0xBE12" name="HLSQ_PERFCTR_HLSQ_SEL_2"/>
1616 <reg32 offset="0xBE13" name="HLSQ_PERFCTR_HLSQ_SEL_3"/>
1617 <reg32 offset="0xBE14" name="HLSQ_PERFCTR_HLSQ_SEL_4"/>
1618 <reg32 offset="0xBE15" name="HLSQ_PERFCTR_HLSQ_SEL_5"/>
1619 <reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/>
1620 <reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/>
1621 <reg32 offset="0xA601" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1622 <reg32 offset="0xA610" name="VFD_PERFCTR_VFD_SEL_0"/>
1623 <reg32 offset="0xA611" name="VFD_PERFCTR_VFD_SEL_1"/>
1624 <reg32 offset="0xA612" name="VFD_PERFCTR_VFD_SEL_2"/>
1625 <reg32 offset="0xA613" name="VFD_PERFCTR_VFD_SEL_3"/>
1626 <reg32 offset="0xA614" name="VFD_PERFCTR_VFD_SEL_4"/>
1627 <reg32 offset="0xA615" name="VFD_PERFCTR_VFD_SEL_5"/>
1628 <reg32 offset="0xA616" name="VFD_PERFCTR_VFD_SEL_6"/>
1629 <reg32 offset="0xA617" name="VFD_PERFCTR_VFD_SEL_7"/>
1630 <reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1631 <reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/>
1632 <reg32 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX_LO"/>
1633 <reg32 offset="0x0E06" name="UCHE_WRITE_RANGE_MAX_HI"/>
1634 <reg32 offset="0x0E07" name="UCHE_WRITE_THRU_BASE_LO"/>
1635 <reg32 offset="0x0E08" name="UCHE_WRITE_THRU_BASE_HI"/>
1636 <reg32 offset="0x0E09" name="UCHE_TRAP_BASE_LO"/>
1637 <reg32 offset="0x0E0A" name="UCHE_TRAP_BASE_HI"/>
1638 <reg32 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN_LO"/>
1639 <reg32 offset="0x0E0C" name="UCHE_GMEM_RANGE_MIN_HI"/>
1640 <reg32 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX_LO"/>
1641 <reg32 offset="0x0E0E" name="UCHE_GMEM_RANGE_MAX_HI"/>
1642 <reg32 offset="0x0E17" name="UCHE_CACHE_WAYS"/>
1643 <reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/>
1644 <reg32 offset="0x0E19" name="UCHE_CLIENT_PF">
1647 <reg32 offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL_0"/>
1648 <reg32 offset="0x0E1D" name="UCHE_PERFCTR_UCHE_SEL_1"/>
1649 <reg32 offset="0x0E1E" name="UCHE_PERFCTR_UCHE_SEL_2"/>
1650 <reg32 offset="0x0E1F" name="UCHE_PERFCTR_UCHE_SEL_3"/>
1651 <reg32 offset="0x0E20" name="UCHE_PERFCTR_UCHE_SEL_4"/>
1652 <reg32 offset="0x0E21" name="UCHE_PERFCTR_UCHE_SEL_5"/>
1653 <reg32 offset="0x0E22" name="UCHE_PERFCTR_UCHE_SEL_6"/>
1654 <reg32 offset="0x0E23" name="UCHE_PERFCTR_UCHE_SEL_7"/>
1655 <reg32 offset="0x0E24" name="UCHE_PERFCTR_UCHE_SEL_8"/>
1656 <reg32 offset="0x0E25" name="UCHE_PERFCTR_UCHE_SEL_9"/>
1657 <reg32 offset="0x0E26" name="UCHE_PERFCTR_UCHE_SEL_10"/>
1658 <reg32 offset="0x0E27" name="UCHE_PERFCTR_UCHE_SEL_11"/>
1659 <reg32 offset="0xAE01" name="SP_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1660 <reg32 offset="0xAE02" name="SP_NC_MODE_CNTL"/>
1661 <reg32 offset="0xAE10" name="SP_PERFCTR_SP_SEL_0"/>
1662 <reg32 offset="0xAE11" name="SP_PERFCTR_SP_SEL_1"/>
1663 <reg32 offset="0xAE12" name="SP_PERFCTR_SP_SEL_2"/>
1664 <reg32 offset="0xAE13" name="SP_PERFCTR_SP_SEL_3"/>
1665 <reg32 offset="0xAE14" name="SP_PERFCTR_SP_SEL_4"/>
1666 <reg32 offset="0xAE15" name="SP_PERFCTR_SP_SEL_5"/>
1667 <reg32 offset="0xAE16" name="SP_PERFCTR_SP_SEL_6"/>
1668 <reg32 offset="0xAE17" name="SP_PERFCTR_SP_SEL_7"/>
1669 <reg32 offset="0xAE18" name="SP_PERFCTR_SP_SEL_8"/>
1670 <reg32 offset="0xAE19" name="SP_PERFCTR_SP_SEL_9"/>
1671 <reg32 offset="0xAE1A" name="SP_PERFCTR_SP_SEL_10"/>
1672 <reg32 offset="0xAE1B" name="SP_PERFCTR_SP_SEL_11"/>
1673 <reg32 offset="0xAE1C" name="SP_PERFCTR_SP_SEL_12"/>
1674 <reg32 offset="0xAE1D" name="SP_PERFCTR_SP_SEL_13"/>
1675 <reg32 offset="0xAE1E" name="SP_PERFCTR_SP_SEL_14"/>
1676 <reg32 offset="0xAE1F" name="SP_PERFCTR_SP_SEL_15"/>
1677 <reg32 offset="0xAE20" name="SP_PERFCTR_SP_SEL_16"/>
1678 <reg32 offset="0xAE21" name="SP_PERFCTR_SP_SEL_17"/>
1679 <reg32 offset="0xAE22" name="SP_PERFCTR_SP_SEL_18"/>
1680 <reg32 offset="0xAE23" name="SP_PERFCTR_SP_SEL_19"/>
1681 <reg32 offset="0xAE24" name="SP_PERFCTR_SP_SEL_20"/>
1682 <reg32 offset="0xAE25" name="SP_PERFCTR_SP_SEL_21"/>
1683 <reg32 offset="0xAE26" name="SP_PERFCTR_SP_SEL_22"/>
1684 <reg32 offset="0xAE27" name="SP_PERFCTR_SP_SEL_23"/>
1685 <reg32 offset="0xB601" name="TPL1_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1686 <reg32 offset="0xB604" name="TPL1_NC_MODE_CNTL"/>
1687 <reg32 offset="0xB608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0"/>
1688 <reg32 offset="0xB609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1"/>
1689 <reg32 offset="0xB60A" name="TPL1_BICUBIC_WEIGHTS_TABLE_2"/>
1690 <reg32 offset="0xB60B" name="TPL1_BICUBIC_WEIGHTS_TABLE_3"/>
1691 <reg32 offset="0xB60C" name="TPL1_BICUBIC_WEIGHTS_TABLE_4"/>
1692 <reg32 offset="0xB610" name="TPL1_PERFCTR_TP_SEL_0"/>
1693 <reg32 offset="0xB611" name="TPL1_PERFCTR_TP_SEL_1"/>
1694 <reg32 offset="0xB612" name="TPL1_PERFCTR_TP_SEL_2"/>
1695 <reg32 offset="0xB613" name="TPL1_PERFCTR_TP_SEL_3"/>
1696 <reg32 offset="0xB614" name="TPL1_PERFCTR_TP_SEL_4"/>
1697 <reg32 offset="0xB615" name="TPL1_PERFCTR_TP_SEL_5"/>
1698 <reg32 offset="0xB616" name="TPL1_PERFCTR_TP_SEL_6"/>
1699 <reg32 offset="0xB617" name="TPL1_PERFCTR_TP_SEL_7"/>
1700 <reg32 offset="0xB618" name="TPL1_PERFCTR_TP_SEL_8"/>
1701 <reg32 offset="0xB619" name="TPL1_PERFCTR_TP_SEL_9"/>
1702 <reg32 offset="0xB61A" name="TPL1_PERFCTR_TP_SEL_10"/>
1703 <reg32 offset="0xB61B" name="TPL1_PERFCTR_TP_SEL_11"/>
1704 <reg32 offset="0x3000" name="VBIF_VERSION"/>
1705 <reg32 offset="0x3001" name="VBIF_CLKON">
1708 <reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN"/>
1709 <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/>
1710 <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
1711 <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>
1712 <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>
1713 <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1">
1716 <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>
1717 <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1">
1720 <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>
1721 <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/>
1722 <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/>
1723 <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/>
1724 <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/>
1725 <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
1726 <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
1727 <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
1728 <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
1729 <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
1730 <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
1731 <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
1732 <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
1733 <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
1734 <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
1735 <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
1736 <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
1737 <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
1738 <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
1739 <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
1740 <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
1741 <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
1743 <reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/>
1744 <reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/>
1745 <reg32 offset="0x3c04" name="GBIF_QSB_SIDE1"/>
1746 <reg32 offset="0x3c05" name="GBIF_QSB_SIDE2"/>
1747 <reg32 offset="0x3c06" name="GBIF_QSB_SIDE3"/>
1748 <reg32 offset="0x3c45" name="GBIF_HALT"/>
1749 <reg32 offset="0x3c46" name="GBIF_HALT_ACK"/>
1750 <reg32 offset="0x3cc0" name="GBIF_PERF_PWR_CNT_EN"/>
1751 <reg32 offset="0x3cc2" name="GBIF_PERF_CNT_SEL"/>
1752 <reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL"/>
1753 <reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0"/>
1754 <reg32 offset="0x3cc5" name="GBIF_PERF_CNT_LOW1"/>
1755 <reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LOW2"/>
1756 <reg32 offset="0x3cc7" name="GBIF_PERF_CNT_LOW3"/>
1757 <reg32 offset="0x3cc8" name="GBIF_PERF_CNT_HIGH0"/>
1758 <reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HIGH1"/>
1759 <reg32 offset="0x3cca" name="GBIF_PERF_CNT_HIGH2"/>
1760 <reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HIGH3"/>
1761 <reg32 offset="0x3ccc" name="GBIF_PWR_CNT_LOW0"/>
1762 <reg32 offset="0x3ccd" name="GBIF_PWR_CNT_LOW1"/>
1763 <reg32 offset="0x3cce" name="GBIF_PWR_CNT_LOW2"/>
1764 <reg32 offset="0x3ccf" name="GBIF_PWR_CNT_HIGH0"/>
1765 <reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1"/>
1766 <reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2"/>
1770 <reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="adreno_reg_xy"/>
1771 <reg32 offset="0xb307" name="SP_TP_WINDOW_OFFSET" type="adreno_reg_xy"/>
1773 <reg32 offset="0x0c02" name="VSC_BIN_SIZE">
1777 <reg32 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS_LO"/>
1778 <reg32 offset="0x0c04" name="VSC_DRAW_STRM_SIZE_ADDRESS_HI"/>
1779 <reg64 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS" type="waddress"/>
1780 <reg32 offset="0x0c06" name="VSC_BIN_COUNT">
1784 <array offset="0x0c10" name="VSC_PIPE_CONFIG" stride="1" length="32">
1785 <reg32 offset="0x0" name="REG">
1810 <reg32 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS_LO"/>
1811 <reg32 offset="0x0c31" name="VSC_PRIM_STRM_ADDRESS_HI"/>
1812 <reg64 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS" type="waddress"/>
1813 <reg32 offset="0x0c32" name="VSC_PRIM_STRM_PITCH"/>
1814 <reg32 offset="0x0c33" name="VSC_PRIM_STRM_LIMIT"/>
1815 <reg32 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS_LO"/>
1816 <reg32 offset="0x0c35" name="VSC_DRAW_STRM_ADDRESS_HI"/>
1817 <reg64 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS" type="waddress"/>
1818 <reg32 offset="0x0c36" name="VSC_DRAW_STRM_PITCH"/>
1819 <reg32 offset="0x0c37" name="VSC_DRAW_STRM_LIMIT"/>
1821 <array offset="0x0c38" name="VSC_STATE" stride="1" length="32">
1829 <reg32 offset="0x0" name="REG"/>
1832 <array offset="0x0c58" name="VSC_PRIM_STRM_SIZE" stride="1" length="32">
1837 <reg32 offset="0x0" name="REG"/>
1840 <array offset="0x0c78" name="VSC_DRAW_STRM_SIZE" stride="1" length="32">
1845 <reg32 offset="0x0" name="REG"/>
1849 <reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12"/>
1857 <reg32 offset="0x8000" name="GRAS_CL_CNTL">
1876 <reg32 offset="0x8001" name="GRAS_VS_CL_CNTL" type="a6xx_gras_xs_cl_cntl"/>
1877 <reg32 offset="0x8002" name="GRAS_DS_CL_CNTL" type="a6xx_gras_xs_cl_cntl"/>
1878 <reg32 offset="0x8003" name="GRAS_GS_CL_CNTL" type="a6xx_gras_xs_cl_cntl"/>
1879 <reg32 offset="0x8004" name="GRAS_MAX_LAYER_INDEX" low="0" high="10" type="uint"/>
1881 <reg32 offset="0x8005" name="GRAS_CNTL">
1889 b3 set for interpolateAt{Offset,Sample}() if not in per-sample
1894 <!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
1898 <reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ">
1903 <array offset="0x8010" name="GRAS_CL_VPORT" stride="6" length="16">
1904 <reg32 offset="0" name="XOFFSET" type="float"/>
1905 <reg32 offset="1" name="XSCALE" type="float"/>
1906 <reg32 offset="2" name="YOFFSET" type="float"/>
1907 <reg32 offset="3" name="YSCALE" type="float"/>
1908 <reg32 offset="4" name="ZOFFSET" type="float"/>
1909 <reg32 offset="5" name="ZSCALE" type="float"/>
1911 <array offset="0x8070" name="GRAS_CL_Z_CLAMP" stride="2" length="16">
1912 <reg32 offset="0" name="MIN" type="float"/>
1913 <reg32 offset="1" name="MAX" type="float"/>
1916 <reg32 offset="0x8090" name="GRAS_SU_CNTL">
1933 <reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX">
1937 <reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4"/>
1939 <reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL">
1942 <reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/>
1943 <reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/>
1944 <reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float"/>
1946 <reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO">
1951 <reg32 offset="0x8099" name="GRAS_UNKNOWN_8099" low="0" high="5"/>
1952 <reg32 offset="0x809a" name="GRAS_UNKNOWN_809A" low="0" high="1"/>
1958 <reg32 offset="0x809b" name="GRAS_VS_LAYER_CNTL" type="a6xx_gras_layer_cntl"/>
1959 <reg32 offset="0x809c" name="GRAS_GS_LAYER_CNTL" type="a6xx_gras_layer_cntl"/>
1960 <reg32 offset="0x809d" name="GRAS_DS_LAYER_CNTL" type="a6xx_gras_layer_cntl"/>
1962 <reg32 offset="0x80a0" name="GRAS_UNKNOWN_80A0" low="0" high="12"/>
1963 <reg32 offset="0x80a1" name="GRAS_BIN_CONTROL">
1973 <reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL">
1978 <reg32 offset="0x80a3" name="GRAS_DEST_MSAA_CNTL">
1999 <reg32 offset="0x80a4" name="GRAS_SAMPLE_CONFIG" type="a6xx_sample_config"/>
2000 <reg32 offset="0x80a5" name="GRAS_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
2001 <reg32 offset="0x80a6" name="GRAS_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
2003 <reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF" pos="0"/>
2009 <array offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR" stride="2" length="16">
2010 <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>
2011 <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>
2013 <array offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16">
2014 <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>
2015 <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>
2018 <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy"/>
2019 <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy"/>
2022 <reg32 offset="0x8100" name="GRAS_LRZ_CNTL">
2037 <reg32 offset="0x8101" name="GRAS_UNKNOWN_8101" low="0" high="2"/>
2038 <reg32 offset="0x8102" name="GRAS_2D_BLIT_INFO">
2041 <reg32 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE_LO"/>
2042 <reg32 offset="0x8104" name="GRAS_LRZ_BUFFER_BASE_HI"/>
2043 <reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress"/>
2044 <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH">
2080 <reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO"/>
2081 <reg32 offset="0x8107" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI"/>
2082 <reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" align="64" type="waddress"/>
2084 <reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL">
2087 <reg32 offset="0x810a" name="GRAS_UNKNOWN_810A">
2095 <reg32 offset="0x8110" name="GRAS_UNKNOWN_8110" low="0" high="1"/>
2123 <reg32 offset="0x8400" name="GRAS_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
2128 <reg32 offset="0x8401" name="GRAS_2D_SRC_TL_X" low="8" high="24" type="int"/>
2129 <reg32 offset="0x8402" name="GRAS_2D_SRC_BR_X" low="8" high="24" type="int"/>
2130 <reg32 offset="0x8403" name="GRAS_2D_SRC_TL_Y" low="8" high="24" type="int"/>
2131 <reg32 offset="0x8404" name="GRAS_2D_SRC_BR_Y" low="8" high="24" type="int"/>
2132 <reg32 offset="0x8405" name="GRAS_2D_DST_TL" type="a6xx_reg_xy"/>
2133 <reg32 offset="0x8406" name="GRAS_2D_DST_BR" type="a6xx_reg_xy"/>
2134 <reg32 offset="0x8407" name="GRAS_2D_UNKNOWN_8407" low="0" high="31"/>
2135 <reg32 offset="0x8408" name="GRAS_2D_UNKNOWN_8408" low="0" high="31"/>
2136 <reg32 offset="0x8409" name="GRAS_2D_UNKNOWN_8409" low="0" high="31"/>
2137 <reg32 offset="0x840a" name="GRAS_2D_RESOLVE_CNTL_1" type="a6xx_reg_xy"/>
2138 <reg32 offset="0x840b" name="GRAS_2D_RESOLVE_CNTL_2" type="a6xx_reg_xy"/>
2142 <reg32 offset="0x8600" name="GRAS_UNKNOWN_8600" low="0" high="12" />
2143 <reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
2144 <reg32 offset="0x8610" name="GRAS_PERFCTR_TSE_SEL_0"/>
2145 <reg32 offset="0x8611" name="GRAS_PERFCTR_TSE_SEL_1"/>
2146 <reg32 offset="0x8612" name="GRAS_PERFCTR_TSE_SEL_2"/>
2147 <reg32 offset="0x8613" name="GRAS_PERFCTR_TSE_SEL_3"/>
2148 <reg32 offset="0x8614" name="GRAS_PERFCTR_RAS_SEL_0"/>
2149 <reg32 offset="0x8615" name="GRAS_PERFCTR_RAS_SEL_1"/>
2150 <reg32 offset="0x8616" name="GRAS_PERFCTR_RAS_SEL_2"/>
2151 <reg32 offset="0x8617" name="GRAS_PERFCTR_RAS_SEL_3"/>
2152 <reg32 offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL_0"/>
2153 <reg32 offset="0x8619" name="GRAS_PERFCTR_LRZ_SEL_1"/>
2154 <reg32 offset="0x861A" name="GRAS_PERFCTR_LRZ_SEL_2"/>
2155 <reg32 offset="0x861B" name="GRAS_PERFCTR_LRZ_SEL_3"/>
2162 <reg32 offset="0x8800" name="RB_BIN_CONTROL">
2171 <reg32 offset="0x8801" name="RB_RENDER_CNTL">
2184 <reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL">
2189 <reg32 offset="0x8803" name="RB_DEST_MSAA_CNTL">
2194 <reg32 offset="0x8804" name="RB_SAMPLE_CONFIG" type="a6xx_sample_config"/>
2195 <reg32 offset="0x8805" name="RB_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
2196 <reg32 offset="0x8806" name="RB_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
2202 <reg32 offset="0x8809" name="RB_RENDER_CONTROL0">
2210 b3 set for interpolateAt{Offset,Sample}() if not in per-sample
2215 <!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
2220 <reg32 offset="0x880a" name="RB_RENDER_CONTROL1">
2234 <reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0">
2240 <reg32 offset="0x880c" name="RB_FS_OUTPUT_CNTL1">
2243 <reg32 offset="0x880d" name="RB_RENDER_COMPONENTS">
2253 <reg32 offset="0x880e" name="RB_DITHER_CNTL">
2263 <reg32 offset="0x880f" name="RB_SRGB_CNTL">
2275 <reg32 offset="0x8810" name="RB_SAMPLE_CNTL">
2278 <reg32 offset="0x8811" name="RB_UNKNOWN_8811" low="4" high="6"/>
2281 <reg32 offset="0x8818" name="RB_UNKNOWN_8818" low="0" high="6"/>
2283 <reg32 offset="0x8819" name="RB_UNKNOWN_8819"/>
2284 <reg32 offset="0x881a" name="RB_UNKNOWN_881A"/>
2285 <reg32 offset="0x881b" name="RB_UNKNOWN_881B"/>
2286 <reg32 offset="0x881c" name="RB_UNKNOWN_881C"/>
2287 <reg32 offset="0x881d" name="RB_UNKNOWN_881D"/>
2288 <reg32 offset="0x881e" name="RB_UNKNOWN_881E"/>
2290 <array offset="0x8820" name="RB_MRT" stride="8" length="8">
2291 <reg32 offset="0x0" name="CONTROL">
2298 <reg32 offset="0x1" name="BLEND_CONTROL">
2306 <reg32 offset="0x2" name="BUF_INFO">
2316 <reg32 offset="0x3" name="PITCH" shr="6" high="15" type="uint"/>
2317 <reg32 offset="0x4" name="ARRAY_PITCH" shr="6" high="28" type="uint"/>
2324 <reg32 offset="0x5" name="BASE_LO"/>
2325 <reg32 offset="0x6" name="BASE_HI"/>
2328 <reg64 offset="0x5" name="BASE" type="waddress" align="1"/>
2330 <reg32 offset="0x7" name="BASE_GMEM" low="12" high="31" shr="12"/>
2333 <reg32 offset="0x8860" name="RB_BLEND_RED_F32" type="float"/>
2334 <reg32 offset="0x8861" name="RB_BLEND_GREEN_F32" type="float"/>
2335 <reg32 offset="0x8862" name="RB_BLEND_BLUE_F32" type="float"/>
2336 <reg32 offset="0x8863" name="RB_BLEND_ALPHA_F32" type="float"/>
2337 <reg32 offset="0x8864" name="RB_ALPHA_CONTROL">
2342 <reg32 offset="0x8865" name="RB_BLEND_CNTL">
2352 <reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL">
2356 <reg32 offset="0x8871" name="RB_DEPTH_CNTL">
2369 <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO">
2373 <reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" low="0" high="13" shr="6" type="uint"/>
2374 <reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" low="0" high="27" shr="6" type="uint"/>
2375 <reg32 offset="0x8875" name="RB_DEPTH_BUFFER_BASE_LO"/>
2376 <reg32 offset="0x8876" name="RB_DEPTH_BUFFER_BASE_HI"/>
2377 <reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress" align="64"/>
2378 <reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM" low="12" high="31" shr="12"/>
2380 <reg32 offset="0x8878" name="RB_Z_BOUNDS_MIN" type="float"/>
2381 <reg32 offset="0x8879" name="RB_Z_BOUNDS_MAX" type="float"/>
2383 <reg32 offset="0x8880" name="RB_STENCIL_CONTROL">
2402 <reg32 offset="0x8881" name="RB_STENCIL_INFO">
2406 <reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" low="0" high="11" shr="6" type="uint"/>
2407 <reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" low="0" high="23" shr="6" type="uint"/>
2408 <reg32 offset="0x8884" name="RB_STENCIL_BUFFER_BASE_LO"/>
2409 <reg32 offset="0x8885" name="RB_STENCIL_BUFFER_BASE_HI"/>
2410 <reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress" align="64"/>
2411 <reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM" low="12" high="31" shr="12"/>
2412 <reg32 offset="0x8887" name="RB_STENCILREF">
2416 <reg32 offset="0x8888" name="RB_STENCILMASK">
2420 <reg32 offset="0x8889" name="RB_STENCILWRMASK">
2425 <reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="a6xx_reg_xy"/>
2426 <reg32 offset="0x8891" name="RB_SAMPLE_COUNT_CONTROL">
2431 <reg32 offset="0x8898" name="RB_LRZ_CNTL">
2436 <reg32 offset="0x88c0" name="RB_Z_CLAMP_MIN" type="float"/>
2437 <reg32 offset="0x88c1" name="RB_Z_CLAMP_MAX" type="float"/>
2439 <reg32 offset="0x88d0" name="RB_UNKNOWN_88D0">
2443 <reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="a6xx_reg_xy"/>
2444 <reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="a6xx_reg_xy"/>
2446 <reg32 offset="0x88d3" name="RB_BIN_CONTROL2">
2450 <reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="a6xx_reg_xy"/>
2451 <reg32 offset="0x88d5" name="RB_MSAA_CNTL">
2454 <reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM" low="12" high="31" shr="12"/>
2456 <reg32 offset="0x88d7" name="RB_BLIT_DST_INFO">
2464 <reg64 offset="0x88d8" name="RB_BLIT_DST" type="waddress" align="64"/>
2465 <reg32 offset="0x88d8" name="RB_BLIT_DST_LO"/>
2466 <reg32 offset="0x88d9" name="RB_BLIT_DST_HI"/>
2467 <reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" low="0" high="15" shr="6" type="uint"/>
2469 <reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" low="0" high="28" shr="6" type="uint"/>
2470 <reg64 offset="0x88dc" name="RB_BLIT_FLAG_DST" type="waddress" align="64"/>
2471 <reg32 offset="0x88dc" name="RB_BLIT_FLAG_DST_LO"/>
2472 <reg32 offset="0x88dd" name="RB_BLIT_FLAG_DST_HI"/>
2473 <reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH">
2478 <reg32 offset="0x88df" name="RB_BLIT_CLEAR_COLOR_DW0"/>
2479 <reg32 offset="0x88e0" name="RB_BLIT_CLEAR_COLOR_DW1"/>
2480 <reg32 offset="0x88e1" name="RB_BLIT_CLEAR_COLOR_DW2"/>
2481 <reg32 offset="0x88e2" name="RB_BLIT_CLEAR_COLOR_DW3"/>
2484 <reg32 offset="0x88e3" name="RB_BLIT_INFO">
2503 <reg32 offset="0x88f0" name="RB_UNKNOWN_88F0" low="0" high="11"/>
2505 <reg64 offset="0x88f1" name="RB_UNK_FLAG_BUFFER_BASE" type="waddress" align="64"/>
2506 <reg32 offset="0x88f3" name="RB_UNK_FLAG_BUFFER_PITCH">
2510 <reg32 offset="0x88f4" name="RB_UNKNOWN_88F4" low="0" high="2"/>
2512 <reg32 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE_LO"/>
2513 <reg32 offset="0x8901" name="RB_DEPTH_FLAG_BUFFER_BASE_HI"/>
2514 <reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress" align="64"/>
2515 <reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH">
2521 <array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8">
2522 <reg32 offset="0" name="ADDR_LO"/>
2523 <reg32 offset="1" name="ADDR_HI"/>
2524 <reg64 offset="0" name="ADDR" type="waddress" align="64"/>
2525 <reg32 offset="2" name="PITCH">
2531 <reg32 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR_LO"/>
2532 <reg32 offset="0x8928" name="RB_SAMPLE_COUNT_ADDR_HI"/>
2533 <reg64 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR" type="waddress" align="16"/>
2538 <reg32 offset="0x8c00" name="RB_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
2539 <reg32 offset="0x8c01" name="RB_2D_UNKNOWN_8C01" low="0" high="31"/>
2557 <reg32 offset="0x8c17" name="RB_2D_DST_INFO" type="a6xx_2d_surf_info"/>
2558 <reg32 offset="0x8c18" name="RB_2D_DST_LO"/>
2559 <reg32 offset="0x8c19" name="RB_2D_DST_HI"/>
2560 <reg64 offset="0x8c18" name="RB_2D_DST" type="waddress" align="64"/>
2561 <reg32 offset="0x8c1a" name="RB_2D_DST_PITCH" low="0" high="15" shr="6" type="uint"/>
2563 <reg64 offset="0x8c1b" name="RB_2D_DST_PLANE1" type="waddress" align="64"/>
2564 <reg32 offset="0x8c1d" name="RB_2D_DST_PLANE_PITCH" low="0" high="15" shr="6" type="uint"/>
2565 <reg64 offset="0x8c1e" name="RB_2D_DST_PLANE2" type="waddress" align="64"/>
2567 <reg32 offset="0x8c20" name="RB_2D_DST_FLAGS_LO"/>
2568 <reg32 offset="0x8c21" name="RB_2D_DST_FLAGS_HI"/>
2569 <reg64 offset="0x8c20" name="RB_2D_DST_FLAGS" type="waddress" align="64"/>
2570 <reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH" low="0" high="7" shr="6" type="uint"/>
2572 <reg64 offset="0x8c23" name="RB_2D_DST_FLAGS_PLANE" type="waddress" align="64"/>
2573 <reg32 offset="0x8c25" name="RB_2D_DST_FLAGS_PLANE_PITCH" low="0" high="7" shr="6" type="uint"/>
2577 <reg32 offset="0x8c2c" name="RB_2D_SRC_SOLID_C0"/>
2578 <reg32 offset="0x8c2d" name="RB_2D_SRC_SOLID_C1"/>
2579 <reg32 offset="0x8c2e" name="RB_2D_SRC_SOLID_C2"/>
2580 <reg32 offset="0x8c2f" name="RB_2D_SRC_SOLID_C3"/>
2584 <reg32 offset="0x8e01" name="RB_UNKNOWN_8E01"/>
2586 <reg32 offset="0x8e04" name="RB_UNKNOWN_8E04"/> <!-- TODO: valid mask 0xfffffeff -->
2587 <reg32 offset="0x8e05" name="RB_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
2589 <reg32 offset="0x8e07" name="RB_CCU_CNTL">
2590 <!-- offset into GMEM for something.
2592 BLIT_OP_SCALE also writes to GMEM at this offset for GMEM store
2599 <bitfield name="OFFSET" low="23" high="31" shr="12" type="hex"/>
2603 <reg32 offset="0x8e08" name="RB_NC_MODE_CNTL">
2613 <reg32 offset="0x8e10" name="RB_PERFCTR_RB_SEL_0"/>
2614 <reg32 offset="0x8e11" name="RB_PERFCTR_RB_SEL_1"/>
2615 <reg32 offset="0x8e12" name="RB_PERFCTR_RB_SEL_2"/>
2616 <reg32 offset="0x8e13" name="RB_PERFCTR_RB_SEL_3"/>
2617 <reg32 offset="0x8e14" name="RB_PERFCTR_RB_SEL_4"/>
2618 <reg32 offset="0x8e15" name="RB_PERFCTR_RB_SEL_5"/>
2619 <reg32 offset="0x8e16" name="RB_PERFCTR_RB_SEL_6"/>
2620 <reg32 offset="0x8e17" name="RB_PERFCTR_RB_SEL_7"/>
2621 <reg32 offset="0x8e18" name="RB_PERFCTR_CCU_SEL_0"/>
2622 <reg32 offset="0x8e19" name="RB_PERFCTR_CCU_SEL_1"/>
2623 <reg32 offset="0x8e1a" name="RB_PERFCTR_CCU_SEL_2"/>
2624 <reg32 offset="0x8e1b" name="RB_PERFCTR_CCU_SEL_3"/>
2625 <reg32 offset="0x8e1c" name="RB_PERFCTR_CCU_SEL_4"/>
2629 <reg32 offset="0x8e28" name="RB_UNKNOWN_8E28" low="0" high="10"/>
2631 <reg32 offset="0x8e2c" name="RB_PERFCTR_CMP_SEL_0"/>
2632 <reg32 offset="0x8e2d" name="RB_PERFCTR_CMP_SEL_1"/>
2633 <reg32 offset="0x8e2e" name="RB_PERFCTR_CMP_SEL_2"/>
2634 <reg32 offset="0x8e2f" name="RB_PERFCTR_CMP_SEL_3"/>
2635 <reg32 offset="0x8e3b" name="RB_RB_SUB_BLOCK_SEL_CNTL_HOST"/>
2636 <reg32 offset="0x8e3d" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/>
2639 <reg32 offset="0x8e50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE" pos="0" type="boolean"/>
2641 <reg32 offset="0x8e51" name="RB_UNKNOWN_8E51" type="waddress" align="1"/>
2649 <reg32 offset="0x9100" name="VPC_UNKNOWN_9100" low="0" high="7"/>
2660 <reg32 offset="0x9101" name="VPC_VS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl"/>
2661 <reg32 offset="0x9102" name="VPC_GS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl"/>
2662 <reg32 offset="0x9103" name="VPC_DS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl"/>
2669 <reg32 offset="0x9104" name="VPC_VS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl"/>
2670 <reg32 offset="0x9105" name="VPC_GS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl"/>
2671 <reg32 offset="0x9106" name="VPC_DS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl"/>
2673 <reg32 offset="0x9107" name="VPC_UNKNOWN_9107">
2678 <reg32 offset="0x9108" name="VPC_POLYGON_MODE">
2682 <array offset="0x9200" name="VPC_VARYING_INTERP" stride="1" length="8">
2683 <reg32 offset="0x0" name="MODE"/>
2685 <array offset="0x9208" name="VPC_VARYING_PS_REPL" stride="1" length="8">
2686 <reg32 offset="0x0" name="MODE"/>
2690 <reg32 offset="0x9210" name="VPC_UNKNOWN_9210" low="0" high="31"/>
2691 <reg32 offset="0x9211" name="VPC_UNKNOWN_9211" low="0" high="31"/>
2693 <array offset="0x9212" name="VPC_VAR" stride="1" length="4">
2695 <reg32 offset="0" name="DISABLE"/>
2698 <reg32 offset="0x9216" name="VPC_SO_CNTL">
2727 <reg32 offset="0x9217" name="VPC_SO_PROG">
2736 <reg32 offset="0x9218" name="VPC_SO_STREAM_COUNTS_LO"/>
2737 <reg32 offset="0x9219" name="VPC_SO_STREAM_COUNTS_HI"/>
2738 <reg32 offset="0x9218" name="VPC_SO_STREAM_COUNTS" type="waddress" align="32"/>
2740 <array offset="0x921a" name="VPC_SO" stride="7" length="4">
2741 <reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/>
2742 <reg32 offset="0" name="BUFFER_BASE_LO"/>
2743 <reg32 offset="1" name="BUFFER_BASE_HI"/>
2744 <reg32 offset="2" name="BUFFER_SIZE" low="2" high="31" shr="2"/>
2745 <reg32 offset="3" name="NCOMP" low="0" high="9"/> <!-- component count -->
2746 <reg32 offset="4" name="BUFFER_OFFSET" low="2" high="31" shr="2"/>
2747 <reg64 offset="5" name="FLUSH_BASE" type="waddress" align="32"/>
2748 <reg32 offset="5" name="FLUSH_BASE_LO"/>
2749 <reg32 offset="6" name="FLUSH_BASE_HI"/>
2752 <reg32 offset="0x9236" name="VPC_POINT_COORD_INVERT">
2757 <reg32 offset="0x9300" name="VPC_UNKNOWN_9300" low="0" high="2"/>
2776 <reg32 offset="0x9301" name="VPC_VS_PACK" type="a6xx_vpc_xs_pack"/>
2777 <reg32 offset="0x9302" name="VPC_GS_PACK" type="a6xx_vpc_xs_pack"/>
2778 <reg32 offset="0x9303" name="VPC_DS_PACK" type="a6xx_vpc_xs_pack"/>
2780 <reg32 offset="0x9304" name="VPC_CNTL_0">
2799 <reg32 offset="0x9305" name="VPC_SO_STREAM_CNTL">
2801 It's offset by 1, and 0 means "disabled"
2809 <reg32 offset="0x9306" name="VPC_SO_DISABLE">
2815 <reg32 offset="0x9600" name="VPC_UNKNOWN_9600"/> <!-- always 0x0 ? TODO: 0x1fbf37ff valid mask -->
2816 <reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
2817 <reg32 offset="0x9602" name="VPC_UNKNOWN_9602" pos="0"/> <!-- always 0x0 ? -->
2818 <reg32 offset="0x9603" name="VPC_UNKNOWN_9603" low="0" high="26"/>
2819 <reg32 offset="0x9604" name="VPC_PERFCTR_VPC_SEL_0"/>
2820 <reg32 offset="0x9605" name="VPC_PERFCTR_VPC_SEL_1"/>
2821 <reg32 offset="0x9606" name="VPC_PERFCTR_VPC_SEL_2"/>
2822 <reg32 offset="0x9607" name="VPC_PERFCTR_VPC_SEL_3"/>
2823 <reg32 offset="0x9608" name="VPC_PERFCTR_VPC_SEL_4"/>
2824 <reg32 offset="0x9609" name="VPC_PERFCTR_VPC_SEL_5"/>
2829 <reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX" low="0" high="5" type="uint"/>
2832 <reg32 offset="0x9801" name="PC_HS_INPUT_SIZE">
2848 <reg32 offset="0x9802" name="PC_TESS_CNTL">
2853 <reg32 offset="0x9803" name="PC_RESTART_INDEX" low="0" high="31" type="uint"/>
2854 <reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7"/>
2857 <reg32 offset="0x9805" name="PC_UNKNOWN_9805" low="0" high="2"/>
2860 <reg32 offset="0x9806" name="PC_PRIMID_PASSTHRU" pos="0" type="boolean"/>
2864 <reg32 offset="0x9840" name="PC_DRAW_CMD">
2868 <reg32 offset="0x9841" name="PC_DISPATCH_CMD">
2872 <reg32 offset="0x9842" name="PC_EVENT_CMD">
2880 <reg32 offset="0x9981" name="PC_POLYGON_MODE">
2884 <reg32 offset="0x9980" name="PC_RASTER_CNTL">
2893 <reg32 offset="0x9b00" name="PC_PRIMITIVE_CNTL_0">
2916 <reg32 offset="0x9b01" name="PC_VS_OUT_CNTL" type="a6xx_xs_out_cntl"/>
2917 <reg32 offset="0x9b02" name="PC_GS_OUT_CNTL" type="a6xx_xs_out_cntl"/>
2918 <reg32 offset="0x9b03" name="PC_PRIMITIVE_CNTL_3" pos="11"/>
2919 <reg32 offset="0x9b04" name="PC_DS_OUT_CNTL" type="a6xx_xs_out_cntl"/>
2921 <reg32 offset="0x9b05" name="PC_PRIMITIVE_CNTL_5">
2932 <reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6">
2953 <reg32 offset="0x9b07" name="PC_MULTIVIEW_CNTL" type="a6xx_multiview_cntl"/>
2955 <reg32 offset="0x9b08" name="PC_MULTIVIEW_MASK" type="hex" low="0" high="15"/>
2957 <reg32 offset="0x9c00" name="PC_2D_EVENT_CMD">
2964 <reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL"/>
2965 <reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
2966 <reg32 offset="0x9e08" name="PC_TESSFACTOR_ADDR_LO"/>
2967 <reg32 offset="0x9e09" name="PC_TESSFACTOR_ADDR_HI"/>
2968 <reg32 offset="0x9e08" name="PC_TESSFACTOR_ADDR" type="waddress" align="32"/>
2971 <reg32 offset="0x9e11" name="PC_VSTREAM_CONTROL">
2976 <reg64 offset="0x9e12" name="PC_BIN_PRIM_STRM" type="waddress" align="32"/>
2977 <reg64 offset="0x9e14" name="PC_BIN_DRAW_STRM" type="waddress" align="32"/>
2979 <reg32 offset="0x9e34" name="PC_PERFCTR_PC_SEL_0"/>
2980 <reg32 offset="0x9e35" name="PC_PERFCTR_PC_SEL_1"/>
2981 <reg32 offset="0x9e36" name="PC_PERFCTR_PC_SEL_2"/>
2982 <reg32 offset="0x9e37" name="PC_PERFCTR_PC_SEL_3"/>
2983 <reg32 offset="0x9e38" name="PC_PERFCTR_PC_SEL_4"/>
2984 <reg32 offset="0x9e39" name="PC_PERFCTR_PC_SEL_5"/>
2985 <reg32 offset="0x9e3a" name="PC_PERFCTR_PC_SEL_6"/>
2986 <reg32 offset="0x9e3b" name="PC_PERFCTR_PC_SEL_7"/>
2989 <reg32 offset="0x9e72" name="PC_UNKNOWN_9E72"/>
2991 <reg32 offset="0xa000" name="VFD_CONTROL_0">
2995 <reg32 offset="0xa001" name="VFD_CONTROL_1">
3002 <reg32 offset="0xa002" name="VFD_CONTROL_2">
3006 <reg32 offset="0xa003" name="VFD_CONTROL_3">
3011 <reg32 offset="0xa004" name="VFD_CONTROL_4">
3013 <reg32 offset="0xa005" name="VFD_CONTROL_5">
3016 <reg32 offset="0xa006" name="VFD_CONTROL_6">
3025 <reg32 offset="0xa007" name="VFD_MODE_CNTL">
3029 <reg32 offset="0xa008" name="VFD_MULTIVIEW_CNTL" type="a6xx_multiview_cntl"/>
3030 <reg32 offset="0xa009" name="VFD_ADD_OFFSET">
3037 <reg32 offset="0xa00e" name="VFD_INDEX_OFFSET"/>
3038 <reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET"/>
3039 <array offset="0xa010" name="VFD_FETCH" stride="4" length="32">
3040 <reg64 offset="0x0" name="BASE" type="address"/>
3041 <reg32 offset="0x0" name="BASE_LO"/>
3042 <reg32 offset="0x1" name="BASE_HI"/>
3043 <reg32 offset="0x2" name="SIZE" type="uint"/>
3044 <reg32 offset="0x3" name="STRIDE" type="uint"/>
3046 <array offset="0xa090" name="VFD_DECODE" stride="2" length="32">
3047 <reg32 offset="0x0" name="INSTR">
3048 <!-- IDX and byte OFFSET into VFD_FETCH -->
3050 <bitfield name="OFFSET" low="5" high="16"/>
3057 <reg32 offset="0x1" name="STEP_RATE"/>
3059 <array offset="0xa0d0" name="VFD_DEST_CNTL" stride="1" length="32">
3060 <reg32 offset="0x0" name="INSTR">
3067 <reg32 offset="0xa0f8" name="SP_UNKNOWN_A0F8"/>
3116 <reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
3117 <reg32 offset="0xa801" name="SP_VS_BRANCH_COND" type="hex">
3123 <reg32 offset="0xa802" name="SP_VS_PRIMITIVE_CNTL">
3127 <array offset="0xa803" name="SP_VS_OUT" stride="1" length="16">
3128 <reg32 offset="0x0" name="REG">
3142 <array offset="0xa813" name="SP_VS_VPC_DST" stride="1" length="8">
3143 <reg32 offset="0x0" name="REG">
3151 <reg32 offset="0xa81b" name="SP_UNKNOWN_A81B"/>
3152 <reg32 offset="0xa81c" name="SP_VS_OBJ_START_LO"/>
3153 <reg32 offset="0xa81d" name="SP_VS_OBJ_START_HI"/>
3154 <reg32 offset="0xa822" name="SP_VS_TEX_COUNT" type="uint"/>
3155 <reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config"/>
3156 <reg32 offset="0xa824" name="SP_VS_INSTRLEN" type="uint"/>
3158 <reg32 offset="0xa830" name="SP_HS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
3159 <reg32 offset="0xa831" name="SP_HS_UNKNOWN_A831"/>
3160 <reg32 offset="0xa833" name="SP_HS_UNKNOWN_A833"/>
3161 <reg32 offset="0xa834" name="SP_HS_OBJ_START_LO"/>
3162 <reg32 offset="0xa835" name="SP_HS_OBJ_START_HI"/>
3163 <reg32 offset="0xa83a" name="SP_HS_TEX_COUNT" type="uint"/>
3164 <reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config"/>
3165 <reg32 offset="0xa83c" name="SP_HS_INSTRLEN" type="uint"/>
3167 <reg32 offset="0xa840" name="SP_DS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
3168 <reg32 offset="0xa842" name="SP_DS_PRIMITIVE_CNTL">
3172 <array offset="0xa843" name="SP_DS_OUT" stride="1" length="16">
3173 <reg32 offset="0x0" name="REG">
3180 <array offset="0xa853" name="SP_DS_VPC_DST" stride="1" length="8">
3181 <reg32 offset="0x0" name="REG">
3189 <reg32 offset="0xa85b" name="SP_DS_UNKNOWN_A85B"/>
3190 <reg32 offset="0xa85c" name="SP_DS_OBJ_START_LO"/>
3191 <reg32 offset="0xa85d" name="SP_DS_OBJ_START_HI"/>
3192 <reg32 offset="0xa862" name="SP_DS_TEX_COUNT" type="uint"/>
3193 <reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config"/>
3194 <reg32 offset="0xa864" name="SP_DS_INSTRLEN" type="uint"/>
3196 <reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
3197 <reg32 offset="0xa871" name="SP_GS_PRIM_SIZE">
3200 <reg32 offset="0xa872" name="SP_GS_BRANCH_COND" type="hex">
3207 <reg32 offset="0xa873" name="SP_GS_PRIMITIVE_CNTL">
3213 <array offset="0xa874" name="SP_GS_OUT" stride="1" length="16">
3214 <reg32 offset="0x0" name="REG">
3222 <array offset="0xa884" name="SP_GS_VPC_DST" stride="1" length="8">
3223 <reg32 offset="0x0" name="REG">
3231 <reg32 offset="0xa88d" name="SP_GS_OBJ_START_LO"/>
3232 <reg32 offset="0xa88e" name="SP_GS_OBJ_START_HI"/>
3233 <reg32 offset="0xa893" name="SP_GS_TEX_COUNT" type="uint"/>
3234 <reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config"/>
3235 <reg32 offset="0xa895" name="SP_GS_INSTRLEN" type="uint"/>
3237 <reg32 offset="0xa8a0" name="SP_VS_TEX_SAMP_LO"/>
3238 <reg32 offset="0xa8a1" name="SP_VS_TEX_SAMP_HI"/>
3239 <reg32 offset="0xa8a2" name="SP_HS_TEX_SAMP_LO"/>
3240 <reg32 offset="0xa8a3" name="SP_HS_TEX_SAMP_HI"/>
3241 <reg32 offset="0xa8a4" name="SP_DS_TEX_SAMP_LO"/>
3242 <reg32 offset="0xa8a5" name="SP_DS_TEX_SAMP_HI"/>
3243 <reg32 offset="0xa8a6" name="SP_GS_TEX_SAMP_LO"/>
3244 <reg32 offset="0xa8a7" name="SP_GS_TEX_SAMP_HI"/>
3245 <reg32 offset="0xa8a8" name="SP_VS_TEX_CONST_LO"/>
3246 <reg32 offset="0xa8a9" name="SP_VS_TEX_CONST_HI"/>
3247 <reg32 offset="0xa8aa" name="SP_HS_TEX_CONST_LO"/>
3248 <reg32 offset="0xa8ab" name="SP_HS_TEX_CONST_HI"/>
3249 <reg32 offset="0xa8ac" name="SP_DS_TEX_CONST_LO"/>
3250 <reg32 offset="0xa8ad" name="SP_DS_TEX_CONST_HI"/>
3251 <reg32 offset="0xa8ae" name="SP_GS_TEX_CONST_LO"/>
3252 <reg32 offset="0xa8af" name="SP_GS_TEX_CONST_HI"/>
3254 <reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
3255 <reg32 offset="0xa981" name="SP_FS_BRANCH_COND" type="hex">
3261 <reg32 offset="0xa982" name="SP_UNKNOWN_A982"/>
3262 <reg32 offset="0xa983" name="SP_FS_OBJ_START_LO"/>
3263 <reg32 offset="0xa984" name="SP_FS_OBJ_START_HI"/>
3265 <reg32 offset="0xa989" name="SP_BLEND_CNTL">
3271 <reg32 offset="0xa98a" name="SP_SRGB_CNTL">
3282 <reg32 offset="0xa98b" name="SP_FS_RENDER_COMPONENTS">
3292 <reg32 offset="0xa98c" name="SP_FS_OUTPUT_CNTL0">
3298 <reg32 offset="0xa98d" name="SP_FS_OUTPUT_CNTL1">
3302 <array offset="0xa996" name="SP_FS_MRT" stride="1" length="8">
3303 <reg32 offset="0" name="REG">
3310 <reg32 offset="0xa99e" name="SP_FS_PREFETCH_CNTL">
3317 <array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4">
3318 <reg32 offset="0" name="CMD">
3337 <array offset="0xa9a3" name="SP_FS_BINDLESS_PREFETCH" stride="1" length="4">
3338 <reg32 offset="0" name="CMD">
3344 <reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" type="uint"/>
3347 <reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8"/>
3350 <reg32 offset="0xa9b1" name="SP_CS_UNKNOWN_A9B1" type="uint">
3353 the ldl/stl offset seems to be rewritten to 0 when it is beyond
3362 <reg32 offset="0xa9b3" name="SP_CS_UNKNOWN_A9B3" type="uint"/>
3364 <reg32 offset="0xa9ba" name="SP_CS_TEX_COUNT" type="uint"/>
3366 <reg32 offset="0xa9e0" name="SP_FS_TEX_SAMP_LO"/>
3367 <reg32 offset="0xa9e1" name="SP_FS_TEX_SAMP_HI"/>
3368 <reg32 offset="0xa9e2" name="SP_CS_TEX_SAMP_LO"/>
3369 <reg32 offset="0xa9e3" name="SP_CS_TEX_SAMP_HI"/>
3370 <reg32 offset="0xa9e4" name="SP_FS_TEX_CONST_LO"/>
3371 <reg32 offset="0xa9e5" name="SP_FS_TEX_CONST_HI"/>
3372 <reg32 offset="0xa9e6" name="SP_CS_TEX_CONST_LO"/>
3373 <reg32 offset="0xa9e7" name="SP_CS_TEX_CONST_HI"/>
3375 <array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="5">
3376 <reg64 offset="0" name="ADDR" type="waddress"/>
3379 <array offset="0xa98e" name="SP_FS_OUTPUT" stride="1" length="8">
3381 <reg32 offset="0x0" name="REG">
3387 <reg32 offset="0xa9b0" name="SP_CS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
3388 <reg32 offset="0xa9b4" name="SP_CS_OBJ_START_LO"/>
3389 <reg32 offset="0xa9b5" name="SP_CS_OBJ_START_HI"/>
3390 <reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config"/>
3391 <reg32 offset="0xa9bc" name="SP_CS_INSTRLEN" type="uint"/>
3396 <reg32 offset="0xa9f2" name="SP_CS_IBO_LO"/>
3397 <reg32 offset="0xa9f3" name="SP_CS_IBO_HI"/>
3398 <reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" type="uint"/>
3401 <reg32 offset="0xab00" name="SP_MODE_CONTROL">
3413 <reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config"/>
3414 <reg32 offset="0xab05" name="SP_FS_INSTRLEN" type="uint"/>
3416 <array offset="0xab10" name="SP_BINDLESS_BASE" stride="2" length="5">
3417 <reg64 offset="0" name="ADDR" type="waddress"/>
3424 <reg32 offset="0xab1a" name="SP_IBO_LO"/>
3425 <reg32 offset="0xab1b" name="SP_IBO_HI"/>
3426 <reg32 offset="0xab20" name="SP_IBO_COUNT" type="uint"/>
3428 <reg32 offset="0xacc0" name="SP_2D_DST_FORMAT">
3442 <reg32 offset="0xae00" name="SP_UNKNOWN_AE00"/>
3444 <reg32 offset="0xae03" name="SP_UNKNOWN_AE03"/>
3445 <reg32 offset="0xae04" name="SP_UNKNOWN_AE04"/>
3448 <reg32 offset="0xae0f" name="SP_UNKNOWN_AE0F"/>
3455 <reg64 offset="0xb180" name="SP_PS_TP_BORDER_COLOR_BASE_ADDR" type="address"/>
3457 <reg32 offset="0xb182" name="SP_UNKNOWN_B182"/>
3458 <reg32 offset="0xb183" name="SP_UNKNOWN_B183"/>
3462 <reg32 offset="0xb300" name="SP_TP_RAS_MSAA_CNTL">
3465 <reg32 offset="0xb301" name="SP_TP_DEST_MSAA_CNTL">
3471 <reg64 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR" type="address"/>
3472 <reg32 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR_LO"/>
3473 <reg32 offset="0xb303" name="SP_TP_BORDER_COLOR_BASE_ADDR_HI"/>
3474 <reg32 offset="0xb304" name="SP_TP_SAMPLE_CONFIG" type="a6xx_sample_config"/>
3475 <reg32 offset="0xb305" name="SP_TP_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
3476 <reg32 offset="0xb306" name="SP_TP_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
3478 <reg32 offset="0xb309" name="SP_TP_UNKNOWN_B309"/>
3485 <reg32 offset="0xb4c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_surf_info"/>
3486 <reg32 offset="0xb4c1" name="SP_PS_2D_SRC_SIZE">
3490 <reg32 offset="0xb4c2" name="SP_PS_2D_SRC_LO"/>
3491 <reg32 offset="0xb4c3" name="SP_PS_2D_SRC_HI"/>
3492 <reg64 offset="0xb4c2" name="SP_PS_2D_SRC" type="waddress"/>
3493 <reg32 offset="0xb4c4" name="SP_PS_2D_SRC_PITCH">
3497 <reg32 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS_LO"/>
3498 <reg32 offset="0xb4cb" name="SP_PS_2D_SRC_FLAGS_HI"/>
3499 <reg64 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS" type="waddress"/>
3500 <reg32 offset="0xb4cc" name="SP_PS_2D_SRC_FLAGS_PITCH">
3506 <reg32 offset="0xb600" name="SP_UNKNOWN_B600"/>
3509 <reg32 offset="0xb605" name="SP_UNKNOWN_B605"/>
3516 <reg32 offset="0xb800" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3517 <reg32 offset="0xb801" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3518 <reg32 offset="0xb802" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3519 <reg32 offset="0xb803" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3521 <reg32 offset="0xb820" name="HLSQ_LOAD_STATE_GEOM_CMD"/>
3522 <reg64 offset="0xb821" name="HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR"/>
3523 <reg32 offset="0xb823" name="HLSQ_LOAD_STATE_GEOM_DATA"/>
3525 <reg32 offset="0xb980" name="HLSQ_UNKNOWN_B980"/>
3527 <reg32 offset="0xb982" name="HLSQ_CONTROL_1_REG">
3530 <reg32 offset="0xb983" name="HLSQ_CONTROL_2_REG">
3542 <reg32 offset="0xb984" name="HLSQ_CONTROL_3_REG">
3549 <reg32 offset="0xb985" name="HLSQ_CONTROL_4_REG">
3555 <reg32 offset="0xb986" name="HLSQ_CONTROL_5_REG">
3558 <reg32 offset="0xb987" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3560 <reg32 offset="0xb990" name="HLSQ_CS_NDRANGE_0">
3567 <reg32 offset="0xb991" name="HLSQ_CS_NDRANGE_1">
3570 <reg32 offset="0xb992" name="HLSQ_CS_NDRANGE_2">
3573 <reg32 offset="0xb993" name="HLSQ_CS_NDRANGE_3">
3576 <reg32 offset="0xb994" name="HLSQ_CS_NDRANGE_4">
3579 <reg32 offset="0xb995" name="HLSQ_CS_NDRANGE_5">
3582 <reg32 offset="0xb996" name="HLSQ_CS_NDRANGE_6">
3585 <reg32 offset="0xb997" name="HLSQ_CS_CNTL_0">
3591 <reg32 offset="0xb998" name="HLSQ_CS_UNKNOWN_B998"/> <!-- always 0x2fc -->
3592 <reg32 offset="0xb999" name="HLSQ_CS_KERNEL_GROUP_X"/>
3593 <reg32 offset="0xb99a" name="HLSQ_CS_KERNEL_GROUP_Y"/>
3594 <reg32 offset="0xb99b" name="HLSQ_CS_KERNEL_GROUP_Z"/>
3596 <reg32 offset="0xb9a0" name="HLSQ_LOAD_STATE_FRAG_CMD"/>
3597 <reg64 offset="0xb9a1" name="HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR"/>
3598 <reg32 offset="0xb9a3" name="HLSQ_LOAD_STATE_FRAG_DATA"/>
3601 <array offset="0xb9c0" name="HLSQ_CS_BINDLESS_BASE" stride="2" length="5">
3602 <reg64 offset="0" name="ADDR" type="waddress"/>
3605 <reg32 offset="0xbb00" name="HLSQ_DRAW_CMD">
3609 <reg32 offset="0xbb01" name="HLSQ_DISPATCH_CMD">
3613 <reg32 offset="0xbb02" name="HLSQ_EVENT_CMD">
3619 <reg32 offset="0xbb08" name="HLSQ_INVALIDATE_CMD">
3646 <reg32 offset="0xbb10" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl"/>
3648 <reg32 offset="0xbb11" name="HLSQ_SHARED_CONSTS">
3671 <array offset="0xbb20" name="HLSQ_BINDLESS_BASE" stride="2" length="5">
3672 <reg64 offset="0" name="ADDR" type="waddress"/>
3675 <reg32 offset="0xbd80" name="HLSQ_2D_EVENT_CMD">
3681 <reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00"/>
3683 <reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01"/>
3685 <reg32 offset="0xbe04" name="HLSQ_UNKNOWN_BE04"/>
3699 <reg32 offset="0xd600" name="CP_EVENT_START">
3702 <reg32 offset="0xd601" name="CP_EVENT_END">
3705 <reg32 offset="0xd700" name="CP_2D_EVENT_START">
3708 <reg32 offset="0xd701" name="CP_2D_EVENT_END">
3742 <reg32 offset="0" name="0">
3752 <reg32 offset="1" name="1">
3762 <reg32 offset="2" name="2">
3767 <reg32 offset="3" name="3"/>
3786 <reg32 offset="0" name="0">
3801 <reg32 offset="1" name="1">
3805 <reg32 offset="2" name="2">
3821 <reg32 offset="3" name="3">
3842 <reg32 offset="4" name="4">
3845 <reg32 offset="5" name="5">
3849 <reg32 offset="6" name="6">
3854 <reg32 offset="7" name="7">
3857 <reg32 offset="8" name="8">
3861 <reg32 offset="9" name="9">
3864 <reg32 offset="10" name="10">
3870 <reg32 offset="11" name="11"/>
3871 <reg32 offset="12" name="12"/>
3872 <reg32 offset="13" name="13"/>
3873 <reg32 offset="14" name="14"/>
3874 <reg32 offset="15" name="15"/>
3883 <reg32 offset="0" name="0">
3891 <reg32 offset="1" name="1">
3895 <reg32 offset="2" name="2">
3906 <reg32 offset="3" name="3">
3917 <reg32 offset="4" name="4">
3920 <reg32 offset="5" name="5">
3924 <reg32 offset="6" name="6">
3926 <reg32 offset="7" name="7">
3928 <reg32 offset="8" name="8">
3930 <reg32 offset="9" name="9">
3933 <reg32 offset="10" name="10">
3943 <reg32 offset="0" name="0">
3946 <reg32 offset="1" name="1">
3953 <reg32 offset="0x1140" name="GPU_ENABLE_PDC"/>
3954 <reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/>
3955 <reg32 offset="0x1540" name="GPU_TCS0_CONTROL"/>
3956 <reg32 offset="0x1541" name="GPU_TCS0_CMD_ENABLE_BANK"/>
3957 <reg32 offset="0x1542" name="GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK"/>
3958 <reg32 offset="0x1543" name="GPU_TCS0_CMD0_MSGID"/>
3959 <reg32 offset="0x1544" name="GPU_TCS0_CMD0_ADDR"/>
3960 <reg32 offset="0x1545" name="GPU_TCS0_CMD0_DATA"/>
3961 <reg32 offset="0x1572" name="GPU_TCS1_CONTROL"/>
3962 <reg32 offset="0x1573" name="GPU_TCS1_CMD_ENABLE_BANK"/>
3963 <reg32 offset="0x1574" name="GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK"/>
3964 <reg32 offset="0x1575" name="GPU_TCS1_CMD0_MSGID"/>
3965 <reg32 offset="0x1576" name="GPU_TCS1_CMD0_ADDR"/>
3966 <reg32 offset="0x1577" name="GPU_TCS1_CMD0_DATA"/>
3967 <reg32 offset="0x15A4" name="GPU_TCS2_CONTROL"/>
3968 <reg32 offset="0x15A5" name="GPU_TCS2_CMD_ENABLE_BANK"/>
3969 <reg32 offset="0x15A6" name="GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK"/>
3970 <reg32 offset="0x15A7" name="GPU_TCS2_CMD0_MSGID"/>
3971 <reg32 offset="0x15A8" name="GPU_TCS2_CMD0_ADDR"/>
3972 <reg32 offset="0x15A9" name="GPU_TCS2_CMD0_DATA"/>
3973 <reg32 offset="0x15D6" name="GPU_TCS3_CONTROL"/>
3974 <reg32 offset="0x15D7" name="GPU_TCS3_CMD_ENABLE_BANK"/>
3975 <reg32 offset="0x15D8" name="GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK"/>
3976 <reg32 offset="0x15D9" name="GPU_TCS3_CMD0_MSGID"/>
3977 <reg32 offset="0x15DA" name="GPU_TCS3_CMD0_ADDR"/>
3978 <reg32 offset="0x15DB" name="GPU_TCS3_CMD0_DATA"/>
3982 <reg32 offset="0x0" name="MEM_0"/>
3986 <reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A">
3990 <reg32 offset="0x0001" name="CFG_DBGBUS_SEL_B"/>
3991 <reg32 offset="0x0002" name="CFG_DBGBUS_SEL_C"/>
3992 <reg32 offset="0x0003" name="CFG_DBGBUS_SEL_D"/>
3993 <reg32 offset="0x0004" name="CFG_DBGBUS_CNTLT">
3998 <reg32 offset="0x0005" name="CFG_DBGBUS_CNTLM">
4001 <reg32 offset="0x0008" name="CFG_DBGBUS_IVTL_0"/>
4002 <reg32 offset="0x0009" name="CFG_DBGBUS_IVTL_1"/>
4003 <reg32 offset="0x000a" name="CFG_DBGBUS_IVTL_2"/>
4004 <reg32 offset="0x000b" name="CFG_DBGBUS_IVTL_3"/>
4005 <reg32 offset="0x000c" name="CFG_DBGBUS_MASKL_0"/>
4006 <reg32 offset="0x000d" name="CFG_DBGBUS_MASKL_1"/>
4007 <reg32 offset="0x000e" name="CFG_DBGBUS_MASKL_2"/>
4008 <reg32 offset="0x000f" name="CFG_DBGBUS_MASKL_3"/>
4009 <reg32 offset="0x0010" name="CFG_DBGBUS_BYTEL_0">
4019 <reg32 offset="0x0011" name="CFG_DBGBUS_BYTEL_1">
4030 <reg32 offset="0x002f" name="CFG_DBGBUS_TRACE_BUF1"/>
4031 <reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/>
4035 <reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/>
4036 <reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/>