| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FlagsCopyLowering.cpp | 786 unsigned &CondReg = CondRegs[Cond]; in getCondOrInverseInReg() local
841 unsigned &CondReg = CondRegs[Cond]; in rewriteArithmetic() local
868 unsigned CondReg; in rewriteCMov() local
894 unsigned CondReg; in rewriteFCMov() local
936 unsigned CondReg; in rewriteCondJmp() local
1042 unsigned &CondReg = CondRegs[X86::COND_B]; in rewriteSetCarryExtended() local
1096 unsigned &CondReg = CondRegs[Cond]; in rewriteSetCC() local
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| D | X86FastISel.cpp | 2102 unsigned CondReg = getRegForValue(Cond); in X86FastEmitCMoveSelect() local
2320 unsigned CondReg = getRegForValue(Cond); in X86FastEmitPseudoSelect() local
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| D | X86InstructionSelector.cpp | 1408 const Register CondReg = I.getOperand(0).getReg(); in selectCondBranch() local
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86FlagsCopyLowering.cpp | 771 unsigned &CondReg = CondRegs[Cond]; in getCondOrInverseInReg() local
827 unsigned &CondReg = CondRegs[Cond]; in rewriteArithmetic() local
854 unsigned CondReg; in rewriteCMov() local
880 unsigned CondReg; in rewriteFCMov() local
922 unsigned CondReg; in rewriteCondJmp() local
958 unsigned &CondReg = CondRegs[Cond]; in rewriteSetCC() local
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| D | X86InstructionSelector.cpp | 1363 const Register CondReg = I.getOperand(0).getReg(); in selectCondBranch() local
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| D | X86FastISel.cpp | 2118 Register CondReg = getRegForValue(Cond); in X86FastEmitCMoveSelect() local
2336 Register CondReg = getRegForValue(Cond); in X86FastEmitPseudoSelect() local
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIPreEmitPeephole.cpp | 69 const unsigned CondReg = TRI->getVCC(); in optimizeVccBranch() local
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| D | SIOptimizeExecMaskingPreRA.cpp | 40 MCRegister CondReg; member in __anon70e184e00111::SIOptimizeExecMaskingPreRA
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInsertSkips.cpp | 348 const unsigned CondReg = TRI->getVCC(); in optimizeVccBranch() local
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| D | SIOptimizeExecMaskingPreRA.cpp | 198 const unsigned CondReg = Wave32 ? AMDGPU::VCC_LO : AMDGPU::VCC; in optimizeVcndVcmpPair() local
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| D | AMDGPURegisterBankInfo.cpp | 835 Register CondReg; in executeInWaterfallLoop() local
1620 Register CondReg = MI.getOperand(0).getReg(); in applyMappingImpl() local
|
| /external/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFastISel.cpp | 898 unsigned CondReg = getRegForI1Value(Select->getCondition(), Not); in selectSelect() local
1298 unsigned CondReg = getRegForI1Value(Br->getCondition(), Not); in selectBr() local
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFastISel.cpp | 720 unsigned CondReg = getRegForI1Value(Select->getCondition(), Not); in selectSelect() local
1096 unsigned CondReg = getRegForI1Value(Br->getCondition(), Not); in selectBr() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFastISel.cpp | 891 unsigned CondReg = getRegForI1Value(Select->getCondition(), Not); in selectSelect() local
1281 unsigned CondReg = getRegForI1Value(Br->getCondition(), Not); in selectBr() local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 926 unsigned CondReg = createResultReg(&Mips::GPR32RegClass); in selectBranch() local
996 unsigned CondReg = getRegForValue(Cond); in selectSelect() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 970 unsigned CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
1049 unsigned CondReg = getRegForValue(Cond); in selectSelect() local
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 968 unsigned CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
1047 unsigned CondReg = getRegForValue(Cond); in selectSelect() local
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 2381 unsigned CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
2395 unsigned CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
2621 unsigned CondReg = getRegForValue(Cond); in selectSelect() local
2673 unsigned CondReg = getRegForValue(Cond); in selectSelect() local
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 2510 unsigned CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
2524 unsigned CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
2750 unsigned CondReg = getRegForValue(Cond); in selectSelect() local
2802 unsigned CondReg = getRegForValue(Cond); in selectSelect() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 2512 unsigned CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
2526 unsigned CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
2752 unsigned CondReg = getRegForValue(Cond); in selectSelect() local
2804 unsigned CondReg = getRegForValue(Cond); in selectSelect() local
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| D | AArch64InstructionSelector.cpp | 983 const Register CondReg = I.getOperand(0).getReg(); in selectCompareBranch() local
1500 const Register CondReg = I.getOperand(0).getReg(); in select() local
2260 const Register CondReg = I.getOperand(1).getReg(); in select() local
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 774 auto CondReg = MIB.getReg(1); in selectSelect() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 776 auto CondReg = MIB->getOperand(1).getReg(); in selectSelect() local
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 2023 unsigned CondReg = getRegForValue(Cond); in X86FastEmitCMoveSelect() local
2196 unsigned CondReg = getRegForValue(Cond); in X86FastEmitPseudoSelect() local
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 783 unsigned CondReg = createResultReg(&PPC::CRRCRegClass); in SelectBranch() local
|