| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 145 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, in getDPRLaneFromSPR() local
434 const DebugLoc &DL, unsigned DReg, unsigned Lane, in createExtractSubreg()
479 const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) { in createInsertSubreg()
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| D | ARMBaseInstrInfo.cpp | 4904 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); in getCorrespondingDRegAndLane() local
4933 MachineInstr &MI, unsigned DReg, in getImplicitSPRUseForDPRUse()
4961 unsigned DstReg, SrcReg, DReg; in setExecutionDomain() local
5215 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0, in getPartialRegUpdateClearance() local
5237 unsigned DReg = Reg; in breakPartialRegDependency() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 145 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, in getDPRLaneFromSPR() local
434 const DebugLoc &DL, unsigned DReg, unsigned Lane, in createExtractSubreg()
479 const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) { in createInsertSubreg()
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| D | ARMBaseInstrInfo.cpp | 4868 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); in getCorrespondingDRegAndLane() local
4897 MachineInstr &MI, unsigned DReg, in getImplicitSPRUseForDPRUse()
4925 unsigned DstReg, SrcReg, DReg; in setExecutionDomain() local
5179 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0, in getPartialRegUpdateClearance() local
5201 unsigned DReg = Reg; in breakPartialRegDependency() local
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| /external/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 148 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, in getDPRLaneFromSPR() local
446 const DebugLoc &DL, unsigned DReg, unsigned Lane, in createExtractSubreg()
493 const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) { in createInsertSubreg()
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| D | ARMBaseInstrInfo.cpp | 4219 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); in getCorrespondingDRegAndLane() local
4248 MachineInstr &MI, unsigned DReg, in getImplicitSPRUseForDPRUse()
4276 unsigned DstReg, SrcReg, DReg; in setExecutionDomain() local
4530 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0, in getPartialRegUpdateClearance() local
4552 unsigned DReg = Reg; in breakPartialRegDependency() local
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | Mips16FrameLowering.cpp | 79 unsigned DReg = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | Mips16FrameLowering.cpp | 79 unsigned DReg = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
|
| /external/llvm/lib/Target/Mips/ |
| D | Mips16FrameLowering.cpp | 73 unsigned DReg = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86FloatingPoint.cpp | 907 unsigned DReg = countTrailingZeros(Defs); in adjustLiveRegs() local
939 unsigned DReg = countTrailingZeros(Defs); in adjustLiveRegs() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FloatingPoint.cpp | 907 unsigned DReg = countTrailingZeros(Defs); in adjustLiveRegs() local
939 unsigned DReg = countTrailingZeros(Defs); in adjustLiveRegs() local
|
| /external/llvm/lib/Target/X86/ |
| D | X86FloatingPoint.cpp | 860 unsigned DReg = countTrailingZeros(Defs); in adjustLiveRegs() local
891 unsigned DReg = countTrailingZeros(Defs); in adjustLiveRegs() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonSubtarget.cpp | 347 Register DReg = DstInst->getOperand(0).getReg(); in adjustSchedDependency() local
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonSubtarget.cpp | 418 Register DReg = DstInst->getOperand(0).getReg(); in adjustSchedDependency() local
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3386 unsigned DReg = Inst.getOperand(0).getReg(); in expandRotation() local
3451 unsigned DReg = Inst.getOperand(0).getReg(); in expandRotationImm() local
3515 unsigned DReg = Inst.getOperand(0).getReg(); in expandDRotation() local
3580 unsigned DReg = Inst.getOperand(0).getReg(); in expandDRotationImm() local
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| /external/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 4860 unsigned DReg = Inst.getOperand(0).getReg(); in expandRotation() local
4923 unsigned DReg = Inst.getOperand(0).getReg(); in expandRotationImm() local
4985 unsigned DReg = Inst.getOperand(0).getReg(); in expandDRotation() local
5048 unsigned DReg = Inst.getOperand(0).getReg(); in expandDRotationImm() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 4750 unsigned DReg = Inst.getOperand(0).getReg(); in expandRotation() local
4813 unsigned DReg = Inst.getOperand(0).getReg(); in expandRotationImm() local
4875 unsigned DReg = Inst.getOperand(0).getReg(); in expandDRotation() local
4938 unsigned DReg = Inst.getOperand(0).getReg(); in expandDRotationImm() local
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| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 3377 unsigned DReg = RISCV::F0_D + RegNo; in getRegForInlineAsmConstraint() local
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerARM32.cpp | 199 IValueT DReg = EncodedQReg << 1; in mapQRegToDReg() local
|