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1 /**************************************************************************
2  *
3  * Copyright 2010-2012 VMware, Inc.
4  * All Rights Reserved.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the
8  * "Software"), to deal in the Software without restriction, including
9  * without limitation the rights to use, copy, modify, merge, publish,
10  * distribute, sub license, and/or sell copies of the Software, and to
11  * permit persons to whom the Software is furnished to do so, subject to
12  * the following conditions:
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
18  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
19  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * The above copyright notice and this permission notice (including the
23  * next paragraph) shall be included in all copies or substantial portions
24  * of the Software.
25  *
26  **************************************************************************/
27 
28 
29 #ifndef LP_BLD_LIMITS_H_
30 #define LP_BLD_LIMITS_H_
31 
32 
33 #include <limits.h>
34 
35 #include "pipe/p_state.h"
36 #include "pipe/p_defines.h"
37 
38 
39 /*
40  * TGSI translation limits.
41  *
42  * Some are slightly above SM 3.0 requirements to give some wiggle room to
43  * the gallium frontends.
44  */
45 
46 #define LP_MAX_TGSI_TEMPS 4096
47 
48 #define LP_MAX_TGSI_ADDRS 16
49 
50 #define LP_MAX_TGSI_IMMEDIATES 4096
51 
52 #define LP_MAX_TGSI_CONSTS 4096
53 
54 #define LP_MAX_TGSI_CONST_BUFFERS 16
55 
56 #define LP_MAX_TGSI_CONST_BUFFER_SIZE (LP_MAX_TGSI_CONSTS * sizeof(float[4]))
57 
58 #define LP_MAX_TGSI_SHADER_BUFFERS 16
59 
60 #define LP_MAX_TGSI_SHADER_BUFFER_SIZE (1 << 27)
61 
62 #define LP_MAX_TGSI_SHADER_IMAGES 16
63 
64 /*
65  * For quick access we cache registers in statically
66  * allocated arrays. Here we define the maximum size
67  * for those arrays.
68  */
69 #define LP_MAX_INLINED_TEMPS 256
70 
71 #define LP_MAX_INLINED_IMMEDIATES 256
72 
73 /**
74  * Maximum control flow nesting
75  *
76  * SM4.0 requires 64 (per subroutine actually, subroutine nesting itself is 32)
77  * SM3.0 requires 24 (most likely per subroutine too)
78  * add 2 more (some translation could add one more)
79  */
80 #define LP_MAX_TGSI_NESTING 66
81 
82 /**
83  * Maximum iterations before loop termination
84  * Shared between every loop in a TGSI shader
85  */
86 #define LP_MAX_TGSI_LOOP_ITERATIONS 65535
87 
88 
89 /**
90  * Some of these limits are actually infinite (i.e., only limited by available
91  * memory), however advertising INT_MAX would cause some test problems to
92  * actually try to allocate the maximum and run out of memory and crash.  So
93  * stick with something reasonable here.
94  */
95 static inline int
gallivm_get_shader_param(enum pipe_shader_cap param)96 gallivm_get_shader_param(enum pipe_shader_cap param)
97 {
98    switch(param) {
99    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
100    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
101    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
102    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
103       return 1 * 1024 * 1024;
104    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
105       return LP_MAX_TGSI_NESTING;
106    case PIPE_SHADER_CAP_MAX_INPUTS:
107       return 32;
108    case PIPE_SHADER_CAP_MAX_OUTPUTS:
109       return 32;
110    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
111       return LP_MAX_TGSI_CONST_BUFFER_SIZE;
112    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
113       return LP_MAX_TGSI_CONST_BUFFERS;
114    case PIPE_SHADER_CAP_MAX_TEMPS:
115       return LP_MAX_TGSI_TEMPS;
116    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
117       return 1;
118    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
119    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
120    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
121    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
122       return 1;
123    case PIPE_SHADER_CAP_SUBROUTINES:
124       return 1;
125    case PIPE_SHADER_CAP_INTEGERS:
126       return 1;
127    case PIPE_SHADER_CAP_INT64_ATOMICS:
128    case PIPE_SHADER_CAP_FP16:
129    case PIPE_SHADER_CAP_FP16_DERIVATIVES:
130    case PIPE_SHADER_CAP_INT16:
131    case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
132       return 0;
133    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
134       return PIPE_MAX_SAMPLERS;
135    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
136       return PIPE_MAX_SHADER_SAMPLER_VIEWS;
137    case PIPE_SHADER_CAP_PREFERRED_IR:
138       return PIPE_SHADER_IR_TGSI;
139    case PIPE_SHADER_CAP_SUPPORTED_IRS:
140       return (1 << PIPE_SHADER_IR_TGSI) | (1 << PIPE_SHADER_IR_NIR);
141    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
142    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
143       return 1;
144    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
145    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
146    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
147    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
148    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
149    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
150    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
151    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
152       return 0;
153    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
154       return 32;
155    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
156       return LP_MAX_TGSI_SHADER_BUFFERS;
157    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
158       return LP_MAX_TGSI_SHADER_IMAGES;
159    }
160    /* if we get here, we missed a shader cap above (and should have seen
161     * a compiler warning.)
162     */
163    return 0;
164 }
165 
166 
167 #endif /* LP_BLD_LIMITS_H_ */
168