| /external/llvm-project/llvm/unittests/CodeGen/ |
| D | MachineInstrTest.cpp | 61 auto MI1 = MF->CreateMachineInstr(MCID, DebugLoc()); in TEST() local
99 void checkHashAndIsEqualMatch(MachineInstr *MI1, MachineInstr *MI2) { in checkHashAndIsEqualMatch()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MicroMipsSizeReduction.cpp | 398 static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2) { in ConsecutiveInstr()
464 MachineInstr *MI1 = Arguments->MI; in ReduceXWtoXWP() local
621 MachineInstr *MI1 = Arguments->MI; in ReduceMoveToMovep() local
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MicroMipsSizeReduction.cpp | 398 static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2) { in ConsecutiveInstr()
464 MachineInstr *MI1 = Arguments->MI; in ReduceXWtoXWP() local
621 MachineInstr *MI1 = Arguments->MI; in ReduceMoveToMovep() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | DFAPacketizer.cpp | 301 bool VLIWPacketizerList::alias(const MachineInstr &MI1, in alias()
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| D | TargetInstrInfo.cpp | 420 const MachineInstr &MI1, in produceSameValue()
676 MachineInstr *MI1 = nullptr; in hasReassociableOperands() local
691 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg()); in hasReassociableSibling() local
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | DFAPacketizer.cpp | 301 bool VLIWPacketizerList::alias(const MachineInstr &MI1, in alias()
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| D | TargetInstrInfo.cpp | 430 const MachineInstr &MI1, in produceSameValue()
711 MachineInstr *MI1 = nullptr; in hasReassociableOperands() local
726 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg()); in hasReassociableSibling() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64CollectLOH.cpp | 285 const MachineInstr *MI1; ///< Second instruction involved in the LOH member
|
| /external/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 386 const MachineInstr &MI1, in produceSameValue()
570 MachineInstr *MI1 = nullptr; in hasReassociableOperands() local
585 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg()); in hasReassociableSibling() local
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| D | MachineInstr.cpp | 905 static bool hasIdenticalMMOs(const MachineInstr &MI1, const MachineInstr &MI2) { in hasIdenticalMMOs()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64CollectLOH.cpp | 285 const MachineInstr *MI1; ///< Second instruction involved in the LOH member
|
| /external/python/pybind11/tests/ |
| D | test_multiple_inheritance.py | 60 class MI1(m.Base1, m.Base2): class
|
| /external/llvm/lib/Target/X86/ |
| D | X86OptimizeLEAs.cpp | 364 int64_t OptimizeLEAPass::getAddrDispShift(const MachineInstr &MI1, unsigned N1, in getAddrDispShift()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86OptimizeLEAs.cpp | 399 int64_t X86OptimizeLEAPass::getAddrDispShift(const MachineInstr &MI1, in getAddrDispShift()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86OptimizeLEAs.cpp | 399 int64_t X86OptimizeLEAPass::getAddrDispShift(const MachineInstr &MI1, in getAddrDispShift()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonSubtarget.cpp | 146 MachineInstr &MI1 = *SU.getInstr(); in apply() local
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| D | HexagonVLIWPacketizer.cpp | 959 bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1, in arePredicatesComplements()
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| D | HexagonInstrInfo.cpp | 2615 bool HexagonInstrInfo::isToBeScheduledASAP(const MachineInstr &MI1, in isToBeScheduledASAP()
2934 bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1, in addLatencyToSchedule()
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonSubtarget.cpp | 216 MachineInstr &MI1 = *SU.getInstr(); in apply() local
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| D | HexagonVLIWPacketizer.cpp | 967 bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1, in arePredicatesComplements()
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| D | HexagonInstrInfo.cpp | 2643 bool HexagonInstrInfo::isToBeScheduledASAP(const MachineInstr &MI1, in isToBeScheduledASAP()
2964 bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1, in addLatencyToSchedule()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIFixSGPRCopies.cpp | 457 MachineInstr *MI1 = *I1; in hoistAndMergeSGPRInits() local
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| D | AMDGPUSubtarget.cpp | 779 MachineInstr &MI1 = *SUa->getInstr(); in apply() local
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIFixSGPRCopies.cpp | 451 MachineInstr *MI1 = *I1; in hoistAndMergeSGPRInits() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonVLIWPacketizer.cpp | 844 bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1, in arePredicatesComplements()
|