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Searched defs:PhysReg (Results 1 – 25 of 96) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DReachingDefAnalysis.cpp172 int ReachingDefAnalysis::getReachingDef(MachineInstr *MI, int PhysReg) { in getReachingDef()
191 MachineInstr* ReachingDefAnalysis::getReachingMIDef(MachineInstr *MI, int PhysReg) { in getReachingMIDef()
196 int PhysReg) { in hasSameReachingDef()
222 int ReachingDefAnalysis::getClearance(MachineInstr *MI, MCPhysReg PhysReg) { in getClearance()
227 void ReachingDefAnalysis::getReachingLocalUses(MachineInstr *Def, int PhysReg, in getReachingLocalUses()
248 unsigned ReachingDefAnalysis::getNumUses(MachineInstr *Def, int PhysReg) { in getNumUses()
254 bool ReachingDefAnalysis::isRegUsedAfter(MachineInstr *MI, int PhysReg) { in isRegUsedAfter()
273 bool ReachingDefAnalysis::isReachingDefLiveOut(MachineInstr *MI, int PhysReg) { in isReachingDefLiveOut()
294 int PhysReg) { in getLocalLiveOutMIDef()
310 int PhysReg) { in getInstWithUseBefore()
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DLiveRegMatrix.cpp81 LiveInterval &VRegInterval, unsigned PhysReg, in foreachUnit()
104 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign()
122 Register PhysReg = VRM->getPhys(VirtReg.reg); in unassign() local
147 unsigned PhysReg) { in checkRegMaskInterference()
165 unsigned PhysReg) { in checkRegUnitInterference()
186 LiveRegMatrix::checkInterference(LiveInterval &VirtReg, unsigned PhysReg) { in checkInterference()
210 unsigned PhysReg) { in checkInterference()
DRegAllocFast.cpp87 MCPhysReg PhysReg = 0; ///< Currently held here. member
143 void markRegUsedInInstr(MCPhysReg PhysReg) { in markRegUsedInInstr()
242 void RegAllocFast::setPhysRegState(MCPhysReg PhysReg, unsigned NewState) { in setPhysRegState()
344 MCPhysReg PhysReg) { in reload()
459 Register PhysReg = MO.getReg(); in usePhysReg() local
522 MCPhysReg PhysReg, RegState NewState) { in definePhysReg()
611 void RegAllocFast::assignVirtToPhysReg(LiveReg &LR, MCPhysReg PhysReg) { in assignVirtToPhysReg()
717 for (MCPhysReg PhysReg : AllocationOrder) { in allocVirtReg() local
758 MCPhysReg PhysReg; in allocVirtRegUndef() local
857 MCPhysReg PhysReg) { in setPhysReg()
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DRegAllocGreedy.cpp323 void addEviction(unsigned PhysReg, unsigned Evictor, unsigned Evictee) { in addEviction()
357 unsigned PhysReg; member
531 unsigned PhysReg; member
767 unsigned PhysReg; in tryAssign() local
811 unsigned PhysReg; in canReassign() local
872 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, in canEvictInterference()
970 unsigned PhysReg, SlotIndex Start, in canEvictInterferenceInRange()
1032 for (auto PhysReg : Order.getOrder()) { in getCheapestEvicteeWeight() local
1048 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg, in evictInterference()
1145 while (unsigned PhysReg = Order.next(OrderLimit)) { in tryEvict() local
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DRegisterClassInfo.cpp111 unsigned PhysReg = RawOrder[i]; in compute() local
134 unsigned PhysReg = CSRAlias[i]; in compute() local
DRegAllocBasic.cpp204 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, in spillInterferences()
263 while (unsigned PhysReg = Order.next()) { in selectOrSplit() local
DAllocationOrder.h90 bool isHint(unsigned PhysReg) const { return is_contained(Hints, PhysReg); } in isHint()
DInterferenceCache.h47 unsigned PhysReg = 0; variable
212 void setPhysReg(InterferenceCache &Cache, unsigned PhysReg) { in setPhysReg()
/external/llvm-project/llvm/lib/CodeGen/
DLiveRegMatrix.cpp81 LiveInterval &VRegInterval, MCRegister PhysReg, in foreachUnit()
104 void LiveRegMatrix::assign(LiveInterval &VirtReg, MCRegister PhysReg) { in assign()
122 Register PhysReg = VRM->getPhys(VirtReg.reg()); in unassign() local
147 MCRegister PhysReg) { in checkRegMaskInterference()
165 MCRegister PhysReg) { in checkRegUnitInterference()
186 LiveRegMatrix::checkInterference(LiveInterval &VirtReg, MCRegister PhysReg) { in checkInterference()
210 MCRegister PhysReg) { in checkInterference()
DRegAllocFast.cpp91 MCPhysReg PhysReg = 0; ///< Currently held here. member
152 void markRegUsedInInstr(MCPhysReg PhysReg) { in markRegUsedInInstr()
158 bool isRegUsedInInstr(MCPhysReg PhysReg, bool LookAtPhysRegUses) const { in isRegUsedInInstr()
170 void markPhysRegUsedInInstr(MCPhysReg PhysReg) { in markPhysRegUsedInInstr()
176 void unmarkRegUsedInInstr(MCPhysReg PhysReg) { in unmarkRegUsedInInstr()
277 void RegAllocFast::setPhysRegState(MCPhysReg PhysReg, unsigned NewState) { in setPhysRegState()
434 MCPhysReg PhysReg) { in reload()
494 MCPhysReg PhysReg = LR.PhysReg; in reloadAtBegin() local
536 bool RegAllocFast::displacePhysReg(MachineInstr &MI, MCPhysReg PhysReg) { in displacePhysReg()
566 void RegAllocFast::freePhysReg(MCPhysReg PhysReg) { in freePhysReg()
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DRegAllocGreedy.cpp318 void addEviction(MCRegister PhysReg, Register Evictor, Register Evictee) { in addEviction()
352 MCRegister PhysReg; member
532 MCRegister PhysReg; member
766 Register PhysReg; in tryAssign() local
819 MCRegister PhysReg; in canReassign() local
880 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, MCRegister PhysReg, in canEvictInterference()
979 MCRegister PhysReg, SlotIndex Start, in canEvictInterferenceInRange()
1039 for (MCRegister PhysReg : Order.getOrder()) { in getCheapestEvicteeWeight() local
1055 void RAGreedy::evictInterference(LiveInterval &VirtReg, MCRegister PhysReg, in evictInterference()
1152 MCRegister PhysReg = *I; in tryEvict() local
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DReachingDefAnalysis.cpp32 static bool isValidRegUseOf(const MachineOperand &MO, MCRegister PhysReg) { in isValidRegUseOf()
40 static bool isValidRegDefOf(const MachineOperand &MO, MCRegister PhysReg) { in isValidRegDefOf()
325 MCRegister PhysReg, in getReachingLocalUses()
350 MCRegister PhysReg, in getLiveInUses()
368 void ReachingDefAnalysis::getGlobalUses(MachineInstr *MI, MCRegister PhysReg, in getGlobalUses()
398 MCRegister PhysReg, in getGlobalReachingDefs()
410 MCRegister PhysReg, InstSet &Defs) const { in getLiveOuts()
416 MCRegister PhysReg, InstSet &Defs, in getLiveOuts()
649 auto IsDead = [this, &Dead](MachineInstr *Def, MCRegister PhysReg) { in collectKilledOperands()
687 bool ReachingDefAnalysis::isSafeToDefRegAt(MachineInstr *MI, MCRegister PhysReg, in isSafeToDefRegAt()
DRegisterClassInfo.cpp111 unsigned PhysReg = RawOrder[i]; in compute() local
134 unsigned PhysReg = CSRAlias[i]; in compute() local
DRegAllocBasic.cpp209 bool RABasic::spillInterferences(LiveInterval &VirtReg, MCRegister PhysReg, in spillInterferences()
269 for (MCRegister PhysReg : Order) { in selectOrSplit() local
DInterferenceCache.h47 MCRegister PhysReg = 0; variable
208 void setPhysReg(InterferenceCache &Cache, MCRegister PhysReg) { in setPhysReg()
/external/llvm/lib/CodeGen/
DLiveRegMatrix.cpp75 unsigned PhysReg, Callable Func) { in foreachUnit()
97 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign()
115 unsigned PhysReg = VRM->getPhys(VirtReg.reg); in unassign() local
140 unsigned PhysReg) { in checkRegMaskInterference()
158 unsigned PhysReg) { in checkRegUnitInterference()
179 LiveRegMatrix::checkInterference(LiveInterval &VirtReg, unsigned PhysReg) { in checkInterference()
DRegAllocFast.cpp72 unsigned PhysReg; // Currently held here. member
123 void markRegUsedInInstr(unsigned PhysReg) { in markRegUsedInInstr()
349 unsigned PhysReg = MO.getReg(); in usePhysReg() local
416 void RAFast::definePhysReg(MachineInstr &MI, unsigned PhysReg, in definePhysReg()
507 void RAFast::assignVirtToPhysReg(LiveReg &LR, unsigned PhysReg) { in assignVirtToPhysReg()
516 RAFast::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) { in assignVirtToPhysReg()
556 unsigned PhysReg = *I; in allocVirtReg() local
685 bool RAFast::setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) { in setPhysReg()
759 unsigned PhysReg = LRI->PhysReg; in handleThroughOperands() local
782 unsigned PhysReg = LRI->PhysReg; in handleThroughOperands() local
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DRegAllocGreedy.cpp263 unsigned PhysReg; member
411 unsigned PhysReg; member
622 unsigned PhysReg; in tryAssign() local
664 unsigned PhysReg; in canReassign() local
725 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, in canEvictInterference()
807 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg, in evictInterference()
894 while (unsigned PhysReg = Order.next(OrderLimit)) { in tryEvict() local
1390 while (unsigned PhysReg = Order.next()) { in calculateRegionSplitCost() local
1647 void RAGreedy::calcGapWeights(unsigned PhysReg, in calcGapWeights()
1810 while (unsigned PhysReg = Order.next()) { in tryLocalSplit() local
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DRegisterClassInfo.cpp99 unsigned PhysReg = RawOrder[i]; in compute() local
121 unsigned PhysReg = CSRAlias[i]; in compute() local
DRegAllocBasic.cpp166 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, in spillInterferences()
227 while (unsigned PhysReg = Order.next()) { in selectOrSplit() local
DAllocationOrder.h82 bool isHint(unsigned PhysReg) const { in isHint()
/external/llvm-project/llvm/tools/llvm-exegesis/lib/
DRegisterAliasing.cpp17 for (const size_t PhysReg : SourceBits.set_bits()) { in getAliasedBits() local
35 for (MCPhysReg PhysReg : RegClass) in RegisterAliasingTracker() local
42 const MCPhysReg PhysReg) in RegisterAliasingTracker()
51 for (const size_t PhysReg : SourceBits.set_bits()) { in FillOriginAndAliasedBits() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIPreAllocateWWMRegs.cpp107 for (unsigned PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) { in processDef() local
135 Register PhysReg = VRM->getPhys(VirtReg); in rewriteRegs() local
153 const Register PhysReg = VRM->getPhys(Reg); in rewriteRegs() local
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIPreAllocateWWMRegs.cpp106 for (MCRegister PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) { in processDef() local
134 Register PhysReg = VRM->getPhys(VirtReg); in rewriteRegs() local
152 const Register PhysReg = VRM->getPhys(Reg); in rewriteRegs() local
/external/llvm-project/llvm/include/llvm/CodeGen/
DLiveIntervalCalc.h54 void extendToUses(LiveRange &LR, MCRegister PhysReg) { in extendToUses()

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