1 //===- SIPreAllocateWWMRegs.cpp - WWM Register Pre-allocation -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Pass to pre-allocated WWM registers
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "AMDGPU.h"
15 #include "AMDGPUSubtarget.h"
16 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
17 #include "SIInstrInfo.h"
18 #include "SIMachineFunctionInfo.h"
19 #include "SIRegisterInfo.h"
20 #include "llvm/ADT/PostOrderIterator.h"
21 #include "llvm/CodeGen/LiveInterval.h"
22 #include "llvm/CodeGen/LiveIntervals.h"
23 #include "llvm/CodeGen/LiveRegMatrix.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/RegisterClassInfo.h"
27 #include "llvm/CodeGen/VirtRegMap.h"
28 #include "llvm/InitializePasses.h"
29
30 using namespace llvm;
31
32 #define DEBUG_TYPE "si-pre-allocate-wwm-regs"
33
34 namespace {
35
36 class SIPreAllocateWWMRegs : public MachineFunctionPass {
37 private:
38 const SIInstrInfo *TII;
39 const SIRegisterInfo *TRI;
40 MachineRegisterInfo *MRI;
41 LiveIntervals *LIS;
42 LiveRegMatrix *Matrix;
43 VirtRegMap *VRM;
44 RegisterClassInfo RegClassInfo;
45
46 std::vector<unsigned> RegsToRewrite;
47
48 public:
49 static char ID;
50
SIPreAllocateWWMRegs()51 SIPreAllocateWWMRegs() : MachineFunctionPass(ID) {
52 initializeSIPreAllocateWWMRegsPass(*PassRegistry::getPassRegistry());
53 }
54
55 bool runOnMachineFunction(MachineFunction &MF) override;
56
getAnalysisUsage(AnalysisUsage & AU) const57 void getAnalysisUsage(AnalysisUsage &AU) const override {
58 AU.addRequired<LiveIntervals>();
59 AU.addPreserved<LiveIntervals>();
60 AU.addRequired<VirtRegMap>();
61 AU.addRequired<LiveRegMatrix>();
62 AU.addPreserved<SlotIndexes>();
63 AU.setPreservesCFG();
64 MachineFunctionPass::getAnalysisUsage(AU);
65 }
66
67 private:
68 bool processDef(MachineOperand &MO);
69 void rewriteRegs(MachineFunction &MF);
70 };
71
72 } // End anonymous namespace.
73
74 INITIALIZE_PASS_BEGIN(SIPreAllocateWWMRegs, DEBUG_TYPE,
75 "SI Pre-allocate WWM Registers", false, false)
76 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
77 INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
78 INITIALIZE_PASS_DEPENDENCY(LiveRegMatrix)
79 INITIALIZE_PASS_END(SIPreAllocateWWMRegs, DEBUG_TYPE,
80 "SI Pre-allocate WWM Registers", false, false)
81
82 char SIPreAllocateWWMRegs::ID = 0;
83
84 char &llvm::SIPreAllocateWWMRegsID = SIPreAllocateWWMRegs::ID;
85
createSIPreAllocateWWMRegsPass()86 FunctionPass *llvm::createSIPreAllocateWWMRegsPass() {
87 return new SIPreAllocateWWMRegs();
88 }
89
processDef(MachineOperand & MO)90 bool SIPreAllocateWWMRegs::processDef(MachineOperand &MO) {
91 if (!MO.isReg())
92 return false;
93
94 Register Reg = MO.getReg();
95 if (Reg.isPhysical())
96 return false;
97
98 if (!TRI->isVGPR(*MRI, Reg))
99 return false;
100
101 if (VRM->hasPhys(Reg))
102 return false;
103
104 LiveInterval &LI = LIS->getInterval(Reg);
105
106 for (MCRegister PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) {
107 if (!MRI->isPhysRegUsed(PhysReg) &&
108 Matrix->checkInterference(LI, PhysReg) == LiveRegMatrix::IK_Free) {
109 Matrix->assign(LI, PhysReg);
110 assert(PhysReg != 0);
111 RegsToRewrite.push_back(Reg);
112 return true;
113 }
114 }
115
116 llvm_unreachable("physreg not found for WWM expression");
117 return false;
118 }
119
rewriteRegs(MachineFunction & MF)120 void SIPreAllocateWWMRegs::rewriteRegs(MachineFunction &MF) {
121 for (MachineBasicBlock &MBB : MF) {
122 for (MachineInstr &MI : MBB) {
123 for (MachineOperand &MO : MI.operands()) {
124 if (!MO.isReg())
125 continue;
126
127 const Register VirtReg = MO.getReg();
128 if (VirtReg.isPhysical())
129 continue;
130
131 if (!VRM->hasPhys(VirtReg))
132 continue;
133
134 Register PhysReg = VRM->getPhys(VirtReg);
135 const unsigned SubReg = MO.getSubReg();
136 if (SubReg != 0) {
137 PhysReg = TRI->getSubReg(PhysReg, SubReg);
138 MO.setSubReg(0);
139 }
140
141 MO.setReg(PhysReg);
142 MO.setIsRenamable(false);
143 }
144 }
145 }
146
147 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
148
149 for (unsigned Reg : RegsToRewrite) {
150 LIS->removeInterval(Reg);
151
152 const Register PhysReg = VRM->getPhys(Reg);
153 assert(PhysReg != 0);
154 MFI->ReserveWWMRegister(PhysReg);
155 }
156
157 RegsToRewrite.clear();
158
159 // Update the set of reserved registers to include WWM ones.
160 MRI->freezeReservedRegs(MF);
161 }
162
runOnMachineFunction(MachineFunction & MF)163 bool SIPreAllocateWWMRegs::runOnMachineFunction(MachineFunction &MF) {
164 LLVM_DEBUG(dbgs() << "SIPreAllocateWWMRegs: function " << MF.getName() << "\n");
165
166 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
167
168 TII = ST.getInstrInfo();
169 TRI = &TII->getRegisterInfo();
170 MRI = &MF.getRegInfo();
171
172 LIS = &getAnalysis<LiveIntervals>();
173 Matrix = &getAnalysis<LiveRegMatrix>();
174 VRM = &getAnalysis<VirtRegMap>();
175
176 RegClassInfo.runOnMachineFunction(MF);
177
178 bool RegsAssigned = false;
179
180 // We use a reverse post-order traversal of the control-flow graph to
181 // guarantee that we visit definitions in dominance order. Since WWM
182 // expressions are guaranteed to never involve phi nodes, and we can only
183 // escape WWM through the special WWM instruction, this means that this is a
184 // perfect elimination order, so we can never do any better.
185 ReversePostOrderTraversal<MachineFunction*> RPOT(&MF);
186
187 for (MachineBasicBlock *MBB : RPOT) {
188 bool InWWM = false;
189 for (MachineInstr &MI : *MBB) {
190 if (MI.getOpcode() == AMDGPU::V_SET_INACTIVE_B32 ||
191 MI.getOpcode() == AMDGPU::V_SET_INACTIVE_B64)
192 RegsAssigned |= processDef(MI.getOperand(0));
193
194 if (MI.getOpcode() == AMDGPU::ENTER_WWM) {
195 LLVM_DEBUG(dbgs() << "entering WWM region: " << MI << "\n");
196 InWWM = true;
197 continue;
198 }
199
200 if (MI.getOpcode() == AMDGPU::EXIT_WWM) {
201 LLVM_DEBUG(dbgs() << "exiting WWM region: " << MI << "\n");
202 InWWM = false;
203 }
204
205 if (!InWWM)
206 continue;
207
208 LLVM_DEBUG(dbgs() << "processing " << MI << "\n");
209
210 for (MachineOperand &DefOpnd : MI.defs()) {
211 RegsAssigned |= processDef(DefOpnd);
212 }
213 }
214 }
215
216 if (!RegsAssigned)
217 return false;
218
219 rewriteRegs(MF);
220 return true;
221 }
222