| /external/crosvm/hypervisor/src/ |
| D | x86_64.rs | 58 fn get_regs(&self) -> Result<Regs>; in get_regs()
473 pub struct Regs { struct
474 pub rax: u64,
475 pub rbx: u64,
476 pub rcx: u64,
477 pub rdx: u64,
478 pub rsi: u64,
479 pub rdi: u64,
480 pub rsp: u64,
481 pub rbp: u64,
[all …]
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| /external/llvm-project/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 83 const unsigned *Regs, unsigned Size) { in decodeRegisterClass()
292 const unsigned *Regs) { in decodeBDAddr12Operand()
302 const unsigned *Regs) { in decodeBDAddr20Operand()
312 const unsigned *Regs) { in decodeBDXAddr12Operand()
324 const unsigned *Regs) { in decodeBDXAddr20Operand()
336 const unsigned *Regs) { in decodeBDLAddr12Len4Operand()
348 const unsigned *Regs) { in decodeBDLAddr12Len8Operand()
360 const unsigned *Regs) { in decodeBDRAddr12Operand()
372 const unsigned *Regs) { in decodeBDVAddr12Operand()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 83 const unsigned *Regs, unsigned Size) { in decodeRegisterClass()
292 const unsigned *Regs) { in decodeBDAddr12Operand()
302 const unsigned *Regs) { in decodeBDAddr20Operand()
312 const unsigned *Regs) { in decodeBDXAddr12Operand()
324 const unsigned *Regs) { in decodeBDXAddr20Operand()
336 const unsigned *Regs) { in decodeBDLAddr12Len4Operand()
348 const unsigned *Regs) { in decodeBDLAddr12Len8Operand()
360 const unsigned *Regs) { in decodeBDRAddr12Operand()
372 const unsigned *Regs) { in decodeBDVAddr12Operand()
|
| /external/capstone/arch/SystemZ/ |
| D | SystemZDisassembler.c | 39 static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo, const unsigned *Regs) in decodeRegisterClass()
258 const unsigned *Regs) in decodeBDAddr12Operand()
271 const unsigned *Regs) in decodeBDAddr20Operand()
283 const unsigned *Regs) in decodeBDXAddr12Operand()
298 const unsigned *Regs) in decodeBDXAddr20Operand()
313 const unsigned *Regs) in decodeBDLAddr12Len8Operand()
328 const unsigned *Regs) in decodeBDRAddr12Operand()
343 const unsigned *Regs) in decodeBDVAddr12Operand()
|
| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 78 const unsigned *Regs, unsigned Size) { in decodeRegisterClass()
269 const unsigned *Regs) { in decodeBDAddr12Operand()
279 const unsigned *Regs) { in decodeBDAddr20Operand()
289 const unsigned *Regs) { in decodeBDXAddr12Operand()
301 const unsigned *Regs) { in decodeBDXAddr20Operand()
313 const unsigned *Regs) { in decodeBDLAddr12Len8Operand()
325 const unsigned *Regs) { in decodeBDVAddr12Operand()
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86CallLowering.cpp | 212 [&](ArrayRef<Register> Regs) { in lowerReturn()
354 [&](ArrayRef<Register> Regs) { in lowerFormalArguments()
415 [&](ArrayRef<Register> Regs) { in lowerCall()
465 [&](ArrayRef<Register> Regs) { in lowerCall()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86CallLowering.cpp | 212 [&](ArrayRef<Register> Regs) { in lowerReturn()
357 [&](ArrayRef<Register> Regs) { in lowerFormalArguments()
418 [&](ArrayRef<Register> Regs) { in lowerCall()
468 [&](ArrayRef<Register> Regs) { in lowerCall()
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 336 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
370 MCPhysReg AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
384 MCPhysReg AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock()
411 MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 332 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
359 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
373 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock()
400 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 344 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
371 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
385 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock()
412 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
|
| /external/llvm-project/llvm/include/llvm/MCA/ |
| D | HWEventListener.h | 74 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent()
95 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MCA/ |
| D | HWEventListener.h | 74 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent()
95 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent()
|
| /external/llvm/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 200 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure() local
338 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables()
461 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping()
822 const auto &Regs = RegBank.getRegisters(); in runMCDesc() local
1361 const auto &Regs = RegBank.getRegisters(); in runTargetDesc() local
1459 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); in runTargetDesc() local
|
| /external/llvm-project/clang/lib/StaticAnalyzer/Checkers/ |
| D | Taint.cpp | 136 TaintedSubRegions Regs = SavedRegs ? *SavedRegs : F.getEmptyMap(); in addPartialTaint() local
202 if (const TaintedSubRegions *Regs = in isTainted() local
|
| /external/llvm-project/llvm/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 218 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure() local
385 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables()
520 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping()
884 const auto &Regs = RegBank.getRegisters(); in runMCDesc() local
1451 const auto &Regs = RegBank.getRegisters(); in runTargetDesc() local
1551 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); in runTargetDesc() local
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegisterInfo.cpp | 127 static const unsigned Regs[2][2] = { in getFrameRegister() local
|
| /external/llvm-project/llvm/tools/llvm-exegesis/lib/ |
| D | RegisterAliasing.cpp | 82 std::string debugString(const MCRegisterInfo &RegInfo, const BitVector &Regs) { in debugString()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegisterInfo.cpp | 135 static const unsigned Regs[2][2] = { in getFrameRegister() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Utils/ |
| D | AMDGPUPALMetadata.cpp | 161 auto Regs = getRegisters(); in getRegister() local
555 auto Regs = getRegisters(); in toString() local
|
| /external/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegisterInfo.cpp | 144 static const unsigned Regs[2][2] = { in getFrameRegister() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | RDFRegisters.cpp | 324 auto AliasedRegs = [this] (uint32_t Unit, BitVector &Regs) { in makeRegRef()
334 BitVector Regs(PRI.getTRI().getNumRegs()); in makeRegRef() local
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| D | AMDGPUPALMetadata.cpp | 164 auto Regs = getRegisters(); in getRegister() local
616 auto Regs = getRegisters(); in toString() local
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 972 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { in createDTuple()
981 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple()
990 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, in createTuple()
1028 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off, in SelectTable() local
1194 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStore() local
1212 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStore() local
1266 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectLoadLane() local
1305 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostLoadLane() local
1360 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStoreLane() local
1390 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStoreLane() local
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallLowering.cpp | 439 int VTSplitIdx) { in lowerReturnVal()
706 ArrayRef<Register> Regs, in packSplitRegsToOrigType()
867 LLT LLTy, LLT PartLLT, int VTSplitIdx) { in lowerFormalArguments()
1170 int VTSplitIdx) { in lowerCall()
1275 LLT LLTy, LLT PartLLT, int VTSplitIdx) { in lowerCall()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1117 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { in createDTuple()
1126 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple()
1135 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, in createTuple()
1173 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off, in SelectTable() local
1344 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStore() local
1366 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStore() local
1420 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectLoadLane() local
1459 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostLoadLane() local
1514 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStoreLane() local
1543 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStoreLane() local
|