| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonAsmPrinter.cpp | 330 MCOperand &Rt = Inst.getOperand(3); in HexagonProcessInstruction() local
341 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local
353 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local
554 MCOperand &Rt = Inst.getOperand(1); in HexagonProcessInstruction() local
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| /external/llvm-project/compiler-rt/lib/xray/ |
| D | xray_mips.cpp | 41 uint32_t Rt, in encodeInstruction()
47 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction()
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| D | xray_mips64.cpp | 42 uint32_t Rt, in encodeInstruction()
48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction()
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| /external/llvm-project/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 676 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeAddiGroupBranch() local
704 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP35GroupBranchMMR6() local
749 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeDaddiGroupBranch() local
777 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP37GroupBranchMMR6() local
818 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP65GroupBranchMMR6() local
857 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP75GroupBranchMMR6() local
901 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBlezlGroupBranch() local
946 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBgtzlGroupBranch() local
988 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBgtzGroupBranch() local
1037 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBlezGroupBranch() local
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 676 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeAddiGroupBranch() local
704 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP35GroupBranchMMR6() local
749 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeDaddiGroupBranch() local
777 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP37GroupBranchMMR6() local
818 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP65GroupBranchMMR6() local
857 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP75GroupBranchMMR6() local
901 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBlezlGroupBranch() local
946 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBgtzlGroupBranch() local
988 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBgtzGroupBranch() local
1037 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBlezGroupBranch() local
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonAsmPrinter.cpp | 374 MCOperand &Rt = Inst.getOperand(3); in HexagonProcessInstruction() local
385 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local
397 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local
594 MCOperand &Rt = Inst.getOperand(1); in HexagonProcessInstruction() local
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonAsmPrinter.cpp | 374 MCOperand &Rt = Inst.getOperand(3); in HexagonProcessInstruction() local
385 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local
397 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local
594 MCOperand &Rt = Inst.getOperand(1); in HexagonProcessInstruction() local
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerMIPS32.cpp | 210 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitRsRt() local
221 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitRtRsImm16() local
236 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitRtRsImm16Rel() local
272 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitRdRtSa() local
286 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitRdRsRt() local
346 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitCOP1FmtRtFsFd() local
359 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitCOP1MovRtFs() local
668 const IValueT Rt = encodeGPRegister(OpRt, "Rt", "lui"); in lui() local
687 const IValueT Rt = encodeFPRegister(OpRt, "Ft", "ldc1"); in ldc1() local
749 const IValueT Rt = encodeFPRegister(OpRt, "Ft", "lwc1"); in lwc1() local
[all …]
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| /external/eigen/Eigen/src/Geometry/ |
| D | Umeyama.h | 134 TransformationMatrixType Rt = TransformationMatrixType::Identity(m+1,m+1); variable
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| /external/capstone/arch/ARM/ |
| D | ARMDisassembler.c | 1526 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); in DecodeAddrMode2IdxInstruction() local
1675 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); in DecodeAddrMode3Instruction() local
3345 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); in DecodeT2LoadShift() local
3426 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); in DecodeT2LoadImm8() local
3509 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); in DecodeT2LoadImm12() local
3588 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); in DecodeT2LoadT() local
3627 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); in DecodeT2LoadLabel() local
3785 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); in DecodeT2LdStPre() local
4196 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); in DecodeDoubleRegLoad() local
4219 unsigned Rt = fieldFromInstruction_4(Insn, 0, 4); in DecodeDoubleRegStore() local
[all …]
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| /external/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 603 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeAddiGroupBranch() local
631 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP35GroupBranchMMR6() local
673 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeDaddiGroupBranch() local
701 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP37GroupBranchMMR6() local
744 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBlezlGroupBranch() local
789 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBgtzlGroupBranch() local
831 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBgtzGroupBranch() local
880 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBlezGroupBranch() local
1808 unsigned Rt = fieldFromInstruction(Insn, 16, 5); in DecodeSpecial3LlSc() local
2286 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodeBgtzGroupBranchMMR6() local
[all …]
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1476 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode2IdxInstruction() local
1624 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode3Instruction() local
3360 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadShift() local
3443 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadImm8() local
3527 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadImm12() local
3607 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadT() local
3645 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadLabel() local
3801 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LdStPre() local
4231 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeDoubleRegLoad() local
4253 unsigned Rt = fieldFromInstruction(Insn, 0, 4); in DecodeDoubleRegStore() local
[all …]
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| /external/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1849 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode2IdxInstruction() local
1997 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode3Instruction() local
3788 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadShift() local
3872 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadImm8() local
3956 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadImm12() local
4036 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadT() local
4074 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadLabel() local
4311 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LdStPre() local
4774 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeDoubleRegLoad() local
4797 unsigned Rt = fieldFromInstruction(Insn, 0, 4); in DecodeDoubleRegStore() local
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1828 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode2IdxInstruction() local
1976 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode3Instruction() local
3767 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadShift() local
3851 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadImm8() local
3935 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadImm12() local
4015 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadT() local
4053 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LoadLabel() local
4290 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeT2LdStPre() local
4751 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeDoubleRegLoad() local
4774 unsigned Rt = fieldFromInstruction(Insn, 0, 4); in DecodeDoubleRegStore() local
[all …]
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| /external/capstone/arch/Mips/ |
| D | MipsDisassembler.c | 590 uint32_t Rt = fieldFromInstruction(insn, 16, 5); in DecodeAddiGroupBranch_4() local
626 uint32_t Rt = fieldFromInstruction(insn, 16, 5); in DecodeDaddiGroupBranch_4() local
663 uint32_t Rt = fieldFromInstruction(insn, 16, 5); in DecodeBlezlGroupBranch_4() local
705 uint32_t Rt = fieldFromInstruction(insn, 16, 5); in DecodeBgtzlGroupBranch_4() local
743 uint32_t Rt = fieldFromInstruction(insn, 16, 5); in DecodeBgtzGroupBranch_4() local
789 uint32_t Rt = fieldFromInstruction(insn, 16, 5); in DecodeBlezGroupBranch_4() local
1328 unsigned Rt = fieldFromInstruction(Insn, 16, 5); in DecodeSpecial3LlSc() local
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| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 838 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeUnsignedLdStInstruction() local
899 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeSignedLdStInstruction() local
1084 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeExclusiveLdStInstruction() local
1167 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodePairLdStInstruction() local
1536 uint64_t Rt = fieldFromInstruction(insn, 0, 5); in DecodeTestAndBranch() local
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| /external/capstone/arch/AArch64/ |
| D | AArch64Disassembler.c | 935 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeUnsignedLdStInstruction() local
999 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeSignedLdStInstruction() local
1185 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeExclusiveLdStInstruction() local
1261 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodePairLdStInstruction() local
1628 uint32_t Rt = fieldFromInstruction(insn, 0, 5); in DecodeTestAndBranch() local
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| /external/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 1034 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeUnsignedLdStInstruction() local
1095 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeSignedLdStInstruction() local
1293 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeExclusiveLdStInstruction() local
1376 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodePairLdStInstruction() local
1510 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeAuthLoadInstruction() local
1789 uint64_t Rt = fieldFromInstruction(insn, 0, 5); in DecodeTestAndBranch() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVMergeBaseOffset.cpp | 139 Register Rt = TailAdd.getOperand(2).getReg(); in matchLargeOffset() local
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| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVMergeBaseOffset.cpp | 139 Register Rt = TailAdd.getOperand(2).getReg(); in matchLargeOffset() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCompound.cpp | 200 MCOperand Rs, Rt; in getCompoundInsn() local
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| /external/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCompound.cpp | 201 MCOperand Rs, Rt; in getCompoundInsn() local
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCompound.cpp | 207 MCOperand Rs, Rt; in getCompoundInsn() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 2820 unsigned Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
2827 unsigned Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
2857 unsigned Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
2869 unsigned Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
2892 unsigned Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
2907 unsigned Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
2933 unsigned Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
2943 unsigned Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
2980 unsigned Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 1031 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeUnsignedLdStInstruction() local
1092 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeSignedLdStInstruction() local
1290 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeExclusiveLdStInstruction() local
1373 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodePairLdStInstruction() local
1753 uint64_t Rt = fieldFromInstruction(insn, 0, 5); in DecodeTestAndBranch() local
|