| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 414 Register Src0Reg = I.getOperand(2).getReg(); in selectG_UADDO_USUBO_UADDE_USUBE() local
589 Register Src0Reg = I.getOperand(1).getReg(); in selectG_INSERT() local
652 Register Src0Reg = I.getOperand(2).getReg(); in selectG_INTRINSIC() local
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| D | R600InstrInfo.cpp | 1241 unsigned Src0Reg, in buildDefaultInstruction()
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| D | AMDGPURegisterBankInfo.cpp | 2994 Register Src0Reg = MI.getOperand(2).getReg(); in getInstrMapping() local
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| D | SIInstrInfo.cpp | 4114 Register Src0Reg = Src0.getReg(); in legalizeOperandsVOP2() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 4482 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectRem() local
4546 unsigned Src0Reg = getRegForValue(Src0); in selectMul() local
4560 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectMul() local
4761 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectSDiv() local
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 4654 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectRem() local
4718 unsigned Src0Reg = getRegForValue(Src0); in selectMul() local
4732 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectMul() local
4933 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectSDiv() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 4661 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectRem() local
4725 unsigned Src0Reg = getRegForValue(Src0); in selectMul() local
4739 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectMul() local
4940 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectSDiv() local
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 422 Register Src0Reg = I.getOperand(2).getReg(); in selectG_UADDO_USUBO_UADDE_USUBE() local
698 Register Src0Reg = I.getOperand(1).getReg(); in selectG_INSERT() local
910 Register Src0Reg = I.getOperand(2).getReg(); in selectG_INTRINSIC() local
2778 Register Src0Reg = MI.getOperand(1).getReg(); in selectG_SHUFFLE_VECTOR() local
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| D | R600InstrInfo.cpp | 1242 unsigned Src0Reg, in buildDefaultInstruction()
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| D | AMDGPURegisterBankInfo.cpp | 4107 Register Src0Reg = MI.getOperand(2).getReg(); in getInstrMapping() local
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| D | AMDGPULegalizerInfo.cpp | 1920 Register Src0Reg = MI.getOperand(1).getReg(); in legalizeFrem() local
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| D | SIInstrInfo.cpp | 4603 Register Src0Reg = Src0.getReg(); in legalizeOperandsVOP2() local
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | R600InstrInfo.cpp | 1264 unsigned Src0Reg, in buildDefaultInstruction()
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| D | SIInstrInfo.cpp | 2108 unsigned Src0Reg = Src0.getReg(); in legalizeOperandsVOP2() local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1684 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectDivRem() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1941 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectDivRem() local
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1939 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectDivRem() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 2595 Register Src0Reg = MI.getOperand(2).getReg(); in fewerElementsVectorCmp() local
4199 Register Src0Reg = MI.getOperand(1).getReg(); in lowerShuffleVector() local
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 3367 Register Src0Reg = MI.getOperand(2).getReg(); in fewerElementsVectorCmp() local
5558 Register Src0Reg = MI.getOperand(1).getReg(); in lowerMergeValues() local
5693 Register Src0Reg = MI.getOperand(1).getReg(); in lowerShuffleVector() local
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