| /external/llvm-project/llvm/test/MC/AArch64/SVE2/ |
| D | sqrdmulh-diagnostics.s | 7 sqrdmulh z0.h, z1.h, z8.h[0] label
12 sqrdmulh z0.s, z1.s, z8.s[0] label
17 sqrdmulh z0.d, z1.d, z16.d[0] label
26 sqrdmulh z0.h, z1.h, z2.h[-1] label
31 sqrdmulh z0.h, z1.h, z2.h[8] label
36 sqrdmulh z0.s, z1.s, z2.s[-1] label
41 sqrdmulh z0.s, z1.s, z2.s[4] label
46 sqrdmulh z0.d, z1.d, z2.d[-1] label
51 sqrdmulh z0.d, z1.d, z2.d[2] label
59 sqrdmulh z0.b, z1.h, z2.h label
[all …]
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| D | sqrdmulh.s | 10 sqrdmulh z0.b, z1.b, z2.b label
16 sqrdmulh z0.h, z1.h, z2.h label
22 sqrdmulh z29.s, z30.s, z31.s label
28 sqrdmulh z31.d, z31.d, z31.d label
34 sqrdmulh z0.h, z1.h, z7.h[7] label
40 sqrdmulh z0.s, z1.s, z7.s[3] label
46 sqrdmulh z0.d, z1.d, z15.d[1] label
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 1595 __ sqrdmulh(h7, h24, h0); in GenerateTestSequenceNEON() local
1596 __ sqrdmulh(h14, h3, v4.H(), 6); in GenerateTestSequenceNEON() local
1597 __ sqrdmulh(s27, s19, s24); in GenerateTestSequenceNEON() local
1598 __ sqrdmulh(s31, s21, v4.S(), 0); in GenerateTestSequenceNEON() local
1599 __ sqrdmulh(v18.V2S(), v25.V2S(), v1.V2S()); in GenerateTestSequenceNEON() local
1600 __ sqrdmulh(v22.V2S(), v5.V2S(), v13.S(), 0); in GenerateTestSequenceNEON() local
1601 __ sqrdmulh(v22.V4H(), v24.V4H(), v9.V4H()); in GenerateTestSequenceNEON() local
1602 __ sqrdmulh(v13.V4H(), v2.V4H(), v12.H(), 6); in GenerateTestSequenceNEON() local
1603 __ sqrdmulh(v9.V4S(), v27.V4S(), v2.V4S()); in GenerateTestSequenceNEON() local
1604 __ sqrdmulh(v3.V4S(), v23.V4S(), v7.S(), 1); in GenerateTestSequenceNEON() local
[all …]
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| /external/vixl/src/aarch64/ |
| D | logic-aarch64.cc | 1034 LogicVRegister Simulator::sqrdmulh(VectorFormat vform, in sqrdmulh() function in vixl::aarch64::Simulator
3942 LogicVRegister Simulator::sqrdmulh(VectorFormat vform, in sqrdmulh() function in vixl::aarch64::Simulator
|