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/external/angle/third_party/vulkan-deps/glslang/src/Test/baseResults/
Dspv.vulkan100.subgroupPartitioned.comp.out2 ERROR: 0:19: 'subgroup op' : requires SPIR-V 1.3
3 ERROR: 0:21: 'subgroup op' : requires SPIR-V 1.3
4 ERROR: 0:22: 'subgroup op' : requires SPIR-V 1.3
5 ERROR: 0:23: 'subgroup op' : requires SPIR-V 1.3
6 ERROR: 0:24: 'subgroup op' : requires SPIR-V 1.3
7 ERROR: 0:26: 'subgroup op' : requires SPIR-V 1.3
8 ERROR: 0:27: 'subgroup op' : requires SPIR-V 1.3
9 ERROR: 0:28: 'subgroup op' : requires SPIR-V 1.3
10 ERROR: 0:29: 'subgroup op' : requires SPIR-V 1.3
11 ERROR: 0:31: 'subgroup op' : requires SPIR-V 1.3
[all …]
Dspv.vulkan100.subgroupArithmetic.comp.out2 ERROR: 0:19: 'subgroup op' : requires SPIR-V 1.3
3 ERROR: 0:20: 'subgroup op' : requires SPIR-V 1.3
4 ERROR: 0:21: 'subgroup op' : requires SPIR-V 1.3
5 ERROR: 0:22: 'subgroup op' : requires SPIR-V 1.3
6 ERROR: 0:24: 'subgroup op' : requires SPIR-V 1.3
7 ERROR: 0:25: 'subgroup op' : requires SPIR-V 1.3
8 ERROR: 0:26: 'subgroup op' : requires SPIR-V 1.3
9 ERROR: 0:27: 'subgroup op' : requires SPIR-V 1.3
10 ERROR: 0:29: 'subgroup op' : requires SPIR-V 1.3
11 ERROR: 0:30: 'subgroup op' : requires SPIR-V 1.3
[all …]
/external/deqp-deps/glslang/Test/baseResults/
Dspv.vulkan100.subgroupPartitioned.comp.out2 ERROR: 0:19: 'subgroup op' : requires SPIR-V 1.3
3 ERROR: 0:21: 'subgroup op' : requires SPIR-V 1.3
4 ERROR: 0:22: 'subgroup op' : requires SPIR-V 1.3
5 ERROR: 0:23: 'subgroup op' : requires SPIR-V 1.3
6 ERROR: 0:24: 'subgroup op' : requires SPIR-V 1.3
7 ERROR: 0:26: 'subgroup op' : requires SPIR-V 1.3
8 ERROR: 0:27: 'subgroup op' : requires SPIR-V 1.3
9 ERROR: 0:28: 'subgroup op' : requires SPIR-V 1.3
10 ERROR: 0:29: 'subgroup op' : requires SPIR-V 1.3
11 ERROR: 0:31: 'subgroup op' : requires SPIR-V 1.3
[all …]
Dspv.vulkan100.subgroupArithmetic.comp.out2 ERROR: 0:19: 'subgroup op' : requires SPIR-V 1.3
3 ERROR: 0:20: 'subgroup op' : requires SPIR-V 1.3
4 ERROR: 0:21: 'subgroup op' : requires SPIR-V 1.3
5 ERROR: 0:22: 'subgroup op' : requires SPIR-V 1.3
6 ERROR: 0:24: 'subgroup op' : requires SPIR-V 1.3
7 ERROR: 0:25: 'subgroup op' : requires SPIR-V 1.3
8 ERROR: 0:26: 'subgroup op' : requires SPIR-V 1.3
9 ERROR: 0:27: 'subgroup op' : requires SPIR-V 1.3
10 ERROR: 0:29: 'subgroup op' : requires SPIR-V 1.3
11 ERROR: 0:30: 'subgroup op' : requires SPIR-V 1.3
[all …]
/external/libxml2/result/
Datt48 <val o="0" v="53"/>
9 <val o="e08" v="53"/>
10 <val o="1c32" v="53"/>
11 <val o="2a3c" v="53"/>
12 <val o="3835" v="53"/>
13 <val o="4645" v="53"/>
14 <val o="5455" v="53"/>
15 <val o="6265" v="53"/>
16 <val o="7075" v="53"/>
17 <val o="7e85" v="53"/>
[all …]
/external/libxml2/result/noent/
Datt48 <val o="0" v="53"/>
9 <val o="e08" v="53"/>
10 <val o="1c32" v="53"/>
11 <val o="2a3c" v="53"/>
12 <val o="3835" v="53"/>
13 <val o="4645" v="53"/>
14 <val o="5455" v="53"/>
15 <val o="6265" v="53"/>
16 <val o="7075" v="53"/>
17 <val o="7e85" v="53"/>
[all …]
/external/libxml2/test/
Datt48 <val o="0" v="53"/>
9 <val o="e08" v="53"/>
10 <val o="1c32" v="53"/>
11 <val o="2a3c" v="53"/>
12 <val o="3835" v="53"/>
13 <val o="4645" v="53"/>
14 <val o="5455" v="53"/>
15 <val o="6265" v="53"/>
16 <val o="7075" v="53"/>
17 <val o="7e85" v="53"/>
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dattr-amdgpu-flat-work-group-size-vgpr-limit.ll10 %v0 = call i32 asm sideeffect "; def $0", "=v"()
11 %v1 = call i32 asm sideeffect "; def $0", "=v"()
12 %v2 = call i32 asm sideeffect "; def $0", "=v"()
13 %v3 = call i32 asm sideeffect "; def $0", "=v"()
14 %v4 = call i32 asm sideeffect "; def $0", "=v"()
15 %v5 = call i32 asm sideeffect "; def $0", "=v"()
16 %v6 = call i32 asm sideeffect "; def $0", "=v"()
17 %v7 = call i32 asm sideeffect "; def $0", "=v"()
18 %v8 = call i32 asm sideeffect "; def $0", "=v"()
19 %v9 = call i32 asm sideeffect "; def $0", "=v"()
[all …]
Dllvm.fma.f16.ll10 ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
11 ; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
12 ; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
13 ; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
14 ; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
15 ; SI: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]]
16 ; SI: v_fma_f32 v[[R_F32:[0-9]+]], v[[A_F32:[0-9]]], v[[B_F32:[0-9]]], v[[C_F32:[0-9]]]
17 ; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
18 ; VIGFX9: v_fma_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]], v[[C_F16]]
19 ; GCN: buffer_store_short v[[R_F16]]
[all …]
Dsdwa-peephole.ll1 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -amdgpu-sdwa-peephole=0 -v…
7 ; NOSDWA: v_lshrrev_b32_e32 v[[DST:[0-9]+]], 16, v{{[0-9]+}}
8 ; NOSDWA: v_add_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v[[DST]]
11 ; VI: v_add_u32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD…
12 ; GFX9: v_add_u32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD sr…
13 ; GFX10: v_add_nc_u32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PA…
15 define amdgpu_kernel void @add_shr_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
24 ; NOSDWA: v_lshrrev_b32_e32 v[[DST:[0-9]+]], 16, v{{[0-9]+}}
25 ; NOSDWA: v_subrev_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v[[DST]]
28 ; VI: v_subrev_u32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_…
[all …]
Dv_mac_f16.ll5 ; GCN: {{buffer|flat}}_load_ushort v[[A_F16:[0-9]+]]
6 ; GCN: {{buffer|flat}}_load_ushort v[[B_F16:[0-9]+]]
7 ; GCN: {{buffer|flat}}_load_ushort v[[C_F16:[0-9]+]]
8 ; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
9 ; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
10 ; SI: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]]
11 ; SI: v_mac_f32_e32 v[[C_F32]], v[[A_F32]], v[[B_F32]]
12 ; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[C_F32]]
13 ; SI: buffer_store_short v[[R_F16]]
14 ; VI: v_mac_f16_e32 v[[C_F16]], v[[A_F16]], v[[B_F16]]
[all …]
Dfmul.f16.ll6 ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
7 ; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
8 ; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
9 ; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
10 ; SI: v_mul_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]], v[[B_F32]]
11 ; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
12 ; GFX89: v_mul_f16_e32 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]]
13 ; GCN: buffer_store_short v[[R_F16]]
28 ; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
29 ; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
[all …]
Dfsub.f16.ll6 ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
7 ; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
8 ; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
9 ; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
10 ; SI: v_sub_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]], v[[B_F32]]
11 ; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
12 ; GFX89: v_sub_f16_e32 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]]
13 ; GCN: buffer_store_short v[[R_F16]]
28 ; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
29 ; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
[all …]
Dfadd.f16.ll5 ; GCN: {{buffer|flat}}_load_ushort v[[A_F16:[0-9]+]]
6 ; GCN: {{buffer|flat}}_load_ushort v[[B_F16:[0-9]+]]
7 ; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
8 ; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
9 ; SI: v_add_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]], v[[B_F32]]
10 ; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
11 ; VI: v_add_f16_e32 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]]
12 ; GCN: buffer_store_short v[[R_F16]]
27 ; GCN: {{buffer|flat}}_load_ushort v[[B_F16:[0-9]+]]
28 ; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
[all …]
/external/llvm/test/MC/AMDGPU/
Dflat.s18 flat_load_dword v1, v[3:4]
20 // CI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x30,0xdc,0x03,0x00,0x00,0x01]
21 // VI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x50,0xdc,0x03,0x00,0x00,0x01]
23 flat_load_dword v1, v[3:4] glc
25 // CI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x31,0xdc,0x03,0x00,0x00,0x01]
26 // VI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x51,0xdc,0x03,0x00,0x00,0x01]
28 flat_load_dword v1, v[3:4] glc slc
30 // CI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x00,0x01]
31 // VI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x00,0x01]
33 flat_load_dword v1, v[3:4] glc tfe
[all …]
/external/llvm-project/llvm/test/MC/AMDGPU/
Dflat.s18 flat_load_dword v1, v[3:4]
20 // CI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x30,0xdc,0x03,0x00,0x00,0x01]
21 // VI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x50,0xdc,0x03,0x00,0x00,0x01]
23 flat_load_dword v1, v[3:4] glc
25 // CI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x31,0xdc,0x03,0x00,0x00,0x01]
26 // VI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x51,0xdc,0x03,0x00,0x00,0x01]
28 flat_load_dword v1, v[3:4] glc slc
30 // CI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x00,0x01]
31 // VI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x00,0x01]
33 flat_store_dword v[3:4], v1
[all …]
/external/libjpeg-turbo/
Djaricom.c32 #define V(i, a, b, c, d) \ macro
39 V( 0, 0x5a1d, 1, 1, 1 ),
40 V( 1, 0x2586, 14, 2, 0 ),
41 V( 2, 0x1114, 16, 3, 0 ),
42 V( 3, 0x080b, 18, 4, 0 ),
43 V( 4, 0x03d8, 20, 5, 0 ),
44 V( 5, 0x01da, 23, 6, 0 ),
45 V( 6, 0x00e5, 25, 7, 0 ),
46 V( 7, 0x006f, 28, 8, 0 ),
47 V( 8, 0x0036, 30, 9, 0 ),
[all …]
/external/mesa3d/src/amd/compiler/tests/
Dtest_to_hw_instr.cpp50 //~gfx[67]>> p_unit_test 0
51 //~gfx[67]! v1: %0:v[1] = v_xor_b32 %0:v[1], %0:v[0]
52 //~gfx[67]! v1: %0:v[0] = v_xor_b32 %0:v[1], %0:v[0]
53 //~gfx[67]! v1: %0:v[1] = v_xor_b32 %0:v[1], %0:v[0]
54 bld.pseudo(aco_opcode::p_unit_test, Operand(0u));
60 //~gfx[67]! v2b: %0:v[0][16:32] = v_lshlrev_b32 16, %0:v[0][0:16]
61 //~gfx[67]! v1: %0:v[0] = v_alignbyte_b32 %0:v[1][0:16], %0:v[0][16:32], 2
62 //~gfx[67]! v1: %0:v[0] = v_alignbyte_b32 %0:v[0][0:16], %0:v[0][16:32], 2
69 //~gfx[67]! v2b: %0:v[0][16:32] = v_lshlrev_b32 16, %0:v[0][0:16]
70 //~gfx[67]! v1: %0:v[0] = v_alignbyte_b32 %0:v[1][0:16], %0:v[0][16:32], 2
[all …]
/external/llvm-project/compiler-rt/test/fuzzer/
DMultipleConstraintsOnSmallInputTest.cpp1 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
16 char v = (a1 ^ a2); in func1() local
17 if ( v <= 15 ) in func1()
18 return 0; in func1()
24 char v = (a1 & a2); in func2() local
25 if ( v > 80 ) in func2()
26 return 0; in func2()
32 char v = (a1 & a2); in func3() local
33 if ( v > 48 ) in func3()
34 return 0; in func3()
[all …]
/external/llvm-project/llvm/test/MC/RISCV/rvv/
Dload.s1 # RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
5 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
6 # RUN: | llvm-objdump -d --mattr=+experimental-v - \
8 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
11 vle8.v v8, (a0), v0.t
12 # CHECK-INST: vle8.v v8, (a0), v0.t
13 # CHECK-ENCODING: [0x07,0x04,0x05,0x00]
14 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
17 vle8.v v8, (a0)
18 # CHECK-INST: vle8.v v8, (a0)
[all …]
Dstore.s1 # RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
5 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
6 # RUN: | llvm-objdump -d --mattr=+experimental-v - \
8 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
11 vse8.v v24, (a0), v0.t
12 # CHECK-INST: vse8.v v24, (a0), v0.t
13 # CHECK-ENCODING: [0x27,0x0c,0x05,0x00]
14 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
15 # CHECK-UNKNOWN: 27 0c 05 00 <unknown>
17 vse8.v v24, (a0)
[all …]
/external/ethtool/
Dde2104x.c88 "0x18: CSR3 (Rx Ring Base Address) 0x%08x\n" in print_ring_addresses()
89 "0x20: CSR4 (Tx Ring Base Address) 0x%08x\n" in print_ring_addresses()
99 "0x40: CSR8 (Missed Frames Counter) 0x%08x\n", csr8); in print_rx_missed()
104 unsigned int rx_missed = csr8 & 0xffff; in print_rx_missed()
117 u32 tmp, v, *data = (u32 *)regs->data; in de21040_dump_regs() local
125 v = data[0]; in de21040_dump_regs()
127 "0x00: CSR0 (Bus Mode) 0x%08x\n" in de21040_dump_regs()
132 v, in de21040_dump_regs()
133 csr0_tap[(v >> 17) & 3], in de21040_dump_regs()
134 v & (1 << 16) ? "Diagnostic" : "Standard", in de21040_dump_regs()
[all …]
/external/mesa3d/src/mesa/main/
Dapi_arrayelt.c52 * in the range [0, 7]. Luckily these type tokens are sequentially
63 * Convert normalized/integer/double to the range [0, 3].
75 return 0; in vertex_format_to_index()
96 VertexAttrib1NbvNV(GLuint index, const GLbyte *v) in VertexAttrib1NbvNV() argument
98 CALL_VertexAttrib1fNV(get_dispatch(), (index, BYTE_TO_FLOAT(v[0]))); in VertexAttrib1NbvNV()
102 VertexAttrib1bvNV(GLuint index, const GLbyte *v) in VertexAttrib1bvNV() argument
104 CALL_VertexAttrib1fNV(get_dispatch(), (index, (GLfloat)v[0])); in VertexAttrib1bvNV()
108 VertexAttrib2NbvNV(GLuint index, const GLbyte *v) in VertexAttrib2NbvNV() argument
110 CALL_VertexAttrib2fNV(get_dispatch(), (index, BYTE_TO_FLOAT(v[0]), BYTE_TO_FLOAT(v[1]))); in VertexAttrib2NbvNV()
114 VertexAttrib2bvNV(GLuint index, const GLbyte *v) in VertexAttrib2bvNV() argument
[all …]
/external/llvm/test/CodeGen/AArch64/
Daarch64-be-bv.ll7 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
8 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1
9 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
10 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
12 %rv = add <8 x i16> %in, <i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0>
13 %el = extractelement <8 x i16> %rv, i32 0
19 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
20 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, lsl #8
21 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
22 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Daarch64-be-bv.ll7 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
8 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1
9 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
10 ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
12 %rv = add <8 x i16> %in, <i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0>
19 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
20 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, lsl #8
21 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
22 ; CHECK-NEXT: st1 { v[[REG1]].8h }, [x{{[0-9]+}}]
24 %rv = add <8 x i16> %in, <i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0>
[all …]

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