| /external/llvm/test/ObjectYAML/MachO/ |
| D | lazy_bind_opcode.yaml | 66 Imm: 2
70 Imm: 1
72 Imm: 0
75 Imm: 0
77 Imm: 0
79 Imm: 2
83 Imm: 1
85 Imm: 0
88 Imm: 0
90 Imm: 0
[all …]
|
| D | weak_bind_opcode.yaml | 66 Imm: 1
68 Imm: 0
71 Imm: 1
73 Imm: 2
77 Imm: 0
79 Imm: 0
82 Imm: 0
84 Imm: 0
87 Imm: 0
89 Imm: 2
[all …]
|
| D | bind_opcode.yaml | 66 Imm: 1
68 Imm: 0
71 Imm: 1
73 Imm: 2
77 Imm: 0
79 Imm: 0
82 Imm: 0
84 Imm: 0
87 Imm: 0
89 Imm: 2
[all …]
|
| D | out_of_order_linkedit.yaml | 144 Imm: 1
146 Imm: 2
150 Imm: 0
154 Imm: 0
157 Imm: 1
160 Imm: 0
163 Imm: 1
166 Imm: 2
171 Imm: 0
174 Imm: 0
[all …]
|
| /external/llvm-project/llvm/test/ObjectYAML/MachO/ |
| D | lazy_bind_opcode.yaml | 66 Imm: 2
70 Imm: 1
72 Imm: 0
75 Imm: 0
77 Imm: 0
79 Imm: 2
83 Imm: 1
85 Imm: 0
88 Imm: 0
90 Imm: 0
[all …]
|
| D | weak_bind_opcode.yaml | 66 Imm: 1
68 Imm: 0
71 Imm: 1
73 Imm: 2
77 Imm: 0
79 Imm: 0
82 Imm: 0
84 Imm: 0
87 Imm: 0
89 Imm: 2
[all …]
|
| D | bind_opcode.yaml | 66 Imm: 1
68 Imm: 0
71 Imm: 1
73 Imm: 2
77 Imm: 0
79 Imm: 0
82 Imm: 0
84 Imm: 0
87 Imm: 0
89 Imm: 2
[all …]
|
| D | out_of_order_linkedit.yaml | 144 Imm: 1
146 Imm: 2
150 Imm: 0
154 Imm: 0
157 Imm: 1
160 Imm: 0
163 Imm: 1
166 Imm: 2
171 Imm: 0
174 Imm: 0
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) { in getShiftType() argument
74 switch ((Imm >> 6) & 0x7) { in getShiftType()
85 static inline unsigned getShiftValue(unsigned Imm) { in getShiftValue() argument
86 return Imm & 0x3f; in getShiftValue()
90 /// imm: 6-bit shift amount
97 /// {5-0} = imm
99 unsigned Imm) { in getShifterImm() argument
100 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!"); in getShifterImm()
110 return (STEnc << 6) | (Imm & 0x3f); in getShifterImm()
118 static inline unsigned getArithShiftValue(unsigned Imm) { in getArithShiftValue() argument
[all …]
|
| /external/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) { in getShiftType() argument
74 switch ((Imm >> 6) & 0x7) { in getShiftType()
85 static inline unsigned getShiftValue(unsigned Imm) { in getShiftValue() argument
86 return Imm & 0x3f; in getShiftValue()
90 /// imm: 6-bit shift amount
97 /// {5-0} = imm
99 unsigned Imm) { in getShifterImm() argument
100 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!"); in getShifterImm()
110 return (STEnc << 6) | (Imm & 0x3f); in getShifterImm()
118 static inline unsigned getArithShiftValue(unsigned Imm) { in getArithShiftValue() argument
[all …]
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) { in getShiftType() argument
74 switch ((Imm >> 6) & 0x7) { in getShiftType()
85 static inline unsigned getShiftValue(unsigned Imm) { in getShiftValue() argument
86 return Imm & 0x3f; in getShiftValue()
90 /// imm: 6-bit shift amount
97 /// {5-0} = imm
99 unsigned Imm) { in getShifterImm() argument
100 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!"); in getShifterImm()
110 return (STEnc << 6) | (Imm & 0x3f); in getShifterImm()
118 static inline unsigned getArithShiftValue(unsigned Imm) { in getArithShiftValue() argument
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/ |
| D | legalizer-info-validation.mir | 16 # DEBUG: G_ADD (opcode [[ADD_OPC:[0-9]+]]): 1 type index, 0 imm indices
18 # DEBUG-NEXT: .. the first uncovered imm index: 0, OK
20 # DEBUG-NEXT: G_SUB (opcode [[SUB_OPC:[0-9]+]]): 1 type index, 0 imm indices
23 # DEBUG-NEXT: .. the first uncovered imm index: 0, OK
25 # DEBUG-NEXT: G_MUL (opcode {{[0-9]+}}): 1 type index, 0 imm indices
28 # DEBUG-NEXT: .. the first uncovered imm index: 0, OK
32 # DEBUG-NEXT: .. the first uncovered imm index: 0, OK
34 # DEBUG-NEXT: G_UDIV (opcode {{[0-9]+}}): 1 type index, 0 imm indices
37 # DEBUG-NEXT: .. the first uncovered imm index: 0, OK
39 # DEBUG-NEXT: G_SREM (opcode {{[0-9]+}}): 1 type index, 0 imm indices
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoC.td | 23 return isUInt<6>(Imm) && (Imm != 0);
24 return isUInt<5>(Imm) && (Imm != 0);
30 int64_t Imm;
31 if (!MCOp.evaluateAsConstantImm(Imm))
34 return isUInt<6>(Imm) && (Imm != 0);
35 return isUInt<5>(Imm) && (Imm != 0);
39 def simm6 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<6>(Imm);}]> {
44 int64_t Imm;
45 if (MCOp.evaluateAsConstantImm(Imm))
46 return isInt<6>(Imm);
[all …]
|
| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoC.td | 23 return isUInt<6>(Imm) && (Imm != 0);
24 return isUInt<5>(Imm) && (Imm != 0);
30 int64_t Imm;
31 if (!MCOp.evaluateAsConstantImm(Imm))
34 return isUInt<6>(Imm) && (Imm != 0);
35 return isUInt<5>(Imm) && (Imm != 0);
39 def simm6 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<6>(Imm);}]> {
44 int64_t Imm;
45 if (MCOp.evaluateAsConstantImm(Imm))
46 return isInt<6>(Imm);
[all …]
|
| /external/mesa3d/src/intel/compiler/ |
| D | brw_fs_combine_constants.cpp | 109 struct imm { struct
161 struct imm *imm; argument
166 static struct imm *
170 if (table->imm[i].size == size && in find_imm()
171 !memcmp(table->imm[i].bytes, data, size)) { in find_imm()
172 return &table->imm[i]; in find_imm()
178 static struct imm *
183 table->imm = reralloc(mem_ctx, table->imm, struct imm, table->size); in new_imm()
185 return &table->imm[table->len++]; in new_imm()
189 * Comparator used for sorting an array of imm structures.
[all …]
|
| /external/llvm-project/llvm/test/tools/llvm-lipo/Inputs/ |
| D | armv7-slice-big.yaml | 389 Imm: 1
391 Imm: 2
395 Imm: 11
397 Imm: 2
399 Imm: 0
403 Imm: 2
405 Imm: 2
407 Imm: 0
412 Imm: 11
414 Imm: 0
[all …]
|
| /external/clang/lib/Headers/ |
| D | avx512bwintrin.h | 1632 #define _mm512_shufflehi_epi16(A, imm) __extension__ ({ \ argument
1636 4 + (((imm) >> 0) & 0x3), \
1637 4 + (((imm) >> 2) & 0x3), \
1638 4 + (((imm) >> 4) & 0x3), \
1639 4 + (((imm) >> 6) & 0x3), \
1641 12 + (((imm) >> 0) & 0x3), \
1642 12 + (((imm) >> 2) & 0x3), \
1643 12 + (((imm) >> 4) & 0x3), \
1644 12 + (((imm) >> 6) & 0x3), \
1646 20 + (((imm) >> 0) & 0x3), \
[all …]
|
| D | avx2intrin.h | 498 #define _mm256_shuffle_epi32(a, imm) __extension__ ({ \ argument
501 0 + (((imm) >> 0) & 0x3), \
502 0 + (((imm) >> 2) & 0x3), \
503 0 + (((imm) >> 4) & 0x3), \
504 0 + (((imm) >> 6) & 0x3), \
505 4 + (((imm) >> 0) & 0x3), \
506 4 + (((imm) >> 2) & 0x3), \
507 4 + (((imm) >> 4) & 0x3), \
508 4 + (((imm) >> 6) & 0x3)); })
510 #define _mm256_shufflehi_epi16(a, imm) __extension__ ({ \ argument
[all …]
|
| /external/virglrenderer/tests/ |
| D | large_shader.h | 14 IMM[0] FLT32 {0x40000000, 0xbf800000, 0x00000000, 0x3f7fffff}
15 IMM[1] FLT32 {0xbf3504f4, 0x3f3504f4, 0x00000000, 0x3fb504f3}
16 IMM[2] FLT32 {0xbf87c3b7, 0x80000000, 0xbf733333, 0x41000000}
17 IMM[3] UINT32 {0, 4294967295, 0, 0}
18 IMM[4] INT32 {0, 32, 1, 0}
19 IMM[5] FLT32 {0x3f6e147b, 0x00000000, 0x40400000, 0x42e20000}
20 IMM[6] FLT32 {0x42640000, 0x3f000000, 0x472aee8c, 0x3f800000}
21 IMM[7] FLT32 {0x42680000, 0x42e40000, 0x432a0000, 0x432b0000}
22 IMM[8] FLT32 {0xbf19999a, 0xbef5c28f, 0x3f23d70a, 0x400147ae}
23 IMM[9] FLT32 {0xbf4ccccd, 0x3eb851ec, 0xbef5c28f, 0x3e800000}
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | urem-seteq-nonzero.ll | 8 ; X86-NEXT: imull $-1431655765, {{[0-9]+}}(%esp), %eax # imm = 0xAAAAAAAB
9 ; X86-NEXT: addl $1431655765, %eax # imm = 0x55555555
10 ; X86-NEXT: cmpl $1431655765, %eax # imm = 0x55555555
16 ; X64-NEXT: imull $-1431655765, %edi, %eax # imm = 0xAAAAAAAB
17 ; X64-NEXT: addl $1431655765, %eax # imm = 0x55555555
18 ; X64-NEXT: cmpl $1431655765, %eax # imm = 0x55555555
29 ; X86-NEXT: imull $-1431655765, {{[0-9]+}}(%esp), %eax # imm = 0xAAAAAAAB
30 ; X86-NEXT: addl $-1431655766, %eax # imm = 0xAAAAAAAA
31 ; X86-NEXT: cmpl $1431655765, %eax # imm = 0x55555555
37 ; X64-NEXT: imull $-1431655765, %edi, %eax # imm = 0xAAAAAAAB
[all …]
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstrCDE.td | 16 let Name = "Imm"#width#"b";
21 ImmLeaf<i32, "{ return Imm >= 0 && Imm < (1 << "#width#"); }"> {
115 !con(params.Iops1, (ins imm_13b:$imm), params.PredOp),
116 !strconcat(iname, params.PAsm, "\t$coproc, $Rd, $imm"),
118 bits<13> imm;
122 let Inst{21-16} = imm{12-7};
124 let Inst{7} = imm{6};
125 let Inst{5-0} = imm{5-0};
131 !con(params.Iops2, (ins imm_9b:$imm), params.PredOp),
132 !strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $imm"),
[all …]
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrMemory.td | 83 def : Pat<(i32 (load (regPlusImm I32:$addr, imm:$off))),
84 (LOAD_I32 imm:$off, $addr, 0)>;
85 def : Pat<(i64 (load (regPlusImm I32:$addr, imm:$off))),
86 (LOAD_I64 imm:$off, $addr, 0)>;
87 def : Pat<(f32 (load (regPlusImm I32:$addr, imm:$off))),
88 (LOAD_F32 imm:$off, $addr, 0)>;
89 def : Pat<(f64 (load (regPlusImm I32:$addr, imm:$off))),
90 (LOAD_F64 imm:$off, $addr, 0)>;
91 def : Pat<(i32 (load (or_is_add I32:$addr, imm:$off))),
92 (LOAD_I32 imm:$off, $addr, 0)>;
[all …]
|
| /external/iproute2/include/ |
| D | bpf_util.h | 76 .imm = 0 })
84 .imm = 0 })
88 #define BPF_ALU64_IMM(OP, DST, IMM) \ argument
94 .imm = IMM })
96 #define BPF_ALU32_IMM(OP, DST, IMM) \ argument
102 .imm = IMM })
112 .imm = 0 })
120 .imm = 0 })
124 #define BPF_MOV64_IMM(DST, IMM) \ argument
130 .imm = IMM })
[all …]
|
| /external/mesa3d/src/gallium/auxiliary/postprocess/ |
| D | pp_mlaa.h | 55 "IMM FLT32 { 0.0030, 0.0000, 1.0000, 0.0000}\n"
67 " 11: SGE TEMP[2], TEMP[0], IMM[0].xxxx\n"
68 " 12: DP4 TEMP[0].x, TEMP[2], IMM[0].zzzz\n"
69 " 13: SEQ TEMP[1].x, TEMP[0].xxxx, IMM[0].yyyy\n"
86 "IMM FLT32 { 0.2126, 0.7152, 0.0722, 0.1000}\n"
87 "IMM FLT32 { 1.0000, 0.0000, 0.0000, 0.0000}\n"
89 " 1: DP3 TEMP[0].x, TEMP[1].xyzz, IMM[0]\n"
91 " 3: DP3 TEMP[0].y, TEMP[1].xyzz, IMM[0].xyzz\n"
93 " 5: DP3 TEMP[0].z, TEMP[1].xyzz, IMM[0].xyzz\n"
95 " 7: DP3 TEMP[0].w, TEMP[1].xyzz, IMM[0].xyzz\n"
[all …]
|
| /external/llvm-project/clang/include/clang/Basic/ |
| D | arm_cde.td | 65 !con((CDEIRInt<NAME> $cp), cgArgs, (? $imm))>;
68 cgArgs, (? $imm))>;
72 (seq !con((CDEIRInt<NAME # "d"> $cp), cgArgs, (? $imm)):$pair,
80 (? $imm)):$pair,
86 defm cx1 : CDE_CX_m<(args imm_13b:$imm), (args), (?)>;
87 defm cx2 : CDE_CX_m<(args imm_9b:$imm), (args u32:$n), (? $n)>;
88 defm cx3 : CDE_CX_m<(args imm_6b:$imm), (args u32:$n, u32:$m), (? $n, $m)>;
95 (bitcast !con((CDEIRInt<NAME, [f32]> $cp), cgArgs, (? $imm)),
99 (bitcast $acc, FScalar)), cgArgs, (? $imm)), Scalar)>;
103 (bitcast !con((CDEIRInt<NAME, [f64]> $cp), cgArgs, (? $imm)),
[all …]
|