| /external/llvm/test/MC/ARM/ |
| D | v8_IT_manual.s | 5 it ge label
9 it ge label
11 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
12 it ge label
14 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
15 it ge label
18 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
19 it ge label
23 it ge label
27 it ge label
[all …]
|
| /external/llvm-project/llvm/test/MC/ARM/ |
| D | v8_IT_manual.s | 5 it ge label
9 it ge label
11 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
12 it ge label
14 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
15 it ge label
18 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
19 it ge label
23 it ge label
27 it ge label
[all …]
|
| D | implicit-it-generation.s | 1 @ RUN: llvm-mc -triple thumbv7a--none-eabi -arm-implicit-it=always < %s -show-encoding | FileCheck …
7 @ CHECK: it eq
43 @ CHECK: it eq
45 @ CHECK: it lt
47 @ CHECK: it eq
49 @ CHECK: it ge
78 @ CHECK: it eq
81 @ CHECK: it eq
84 @ CHECK: it eq
99 @ CHECK: it eq
[all …]
|
| /external/pdfium/core/fxcrt/ |
| D | fx_bidi_unittest.cpp | 133 auto it = bidi.begin(); in TEST() local
134 ASSERT_FALSE(it == bidi.end()); in TEST()
135 EXPECT_EQ(0, it->start); in TEST()
136 EXPECT_EQ(1, it->count); in TEST()
137 EXPECT_EQ(CFX_BidiChar::NEUTRAL, it->direction); in TEST()
138 ++it; in TEST()
139 EXPECT_TRUE(it == bidi.end()); in TEST()
146 auto it = bidi.begin(); in TEST() local
147 ASSERT_FALSE(it == bidi.end()); in TEST()
148 EXPECT_EQ(0, it->start); in TEST()
[all …]
|
| /external/swiftshader/src/OpenGL/compiler/ |
| D | IntermTraverse.cpp | 34 void TIntermSymbol::traverse(TIntermTraverser* it) in traverse() argument
36 it->visitSymbol(this); in traverse()
39 void TIntermConstantUnion::traverse(TIntermTraverser* it) in traverse() argument
41 it->visitConstantUnion(this); in traverse()
47 void TIntermBinary::traverse(TIntermTraverser* it) in traverse() argument
54 if(it->preVisit) in traverse()
56 visit = it->visitBinary(PreVisit, this); in traverse()
64 it->incrementDepth(this); in traverse()
66 if(it->rightToLeft) in traverse()
70 right->traverse(it); in traverse()
[all …]
|
| /external/deqp-deps/glslang/glslang/MachineIndependent/ |
| D | IntermTraverse.cpp | 64 void TIntermSymbol::traverse(TIntermTraverser *it) in traverse() argument
66 it->visitSymbol(this); in traverse()
69 void TIntermConstantUnion::traverse(TIntermTraverser *it) in traverse() argument
71 it->visitConstantUnion(this); in traverse()
84 void TIntermBinary::traverse(TIntermTraverser *it) in traverse() argument
91 if (it->preVisit) in traverse()
92 visit = it->visitBinary(EvPreVisit, this); in traverse()
98 it->incrementDepth(this); in traverse()
100 if (it->rightToLeft) { in traverse()
102 right->traverse(it); in traverse()
[all …]
|
| /external/angle/third_party/vulkan-deps/glslang/src/glslang/MachineIndependent/ |
| D | IntermTraverse.cpp | 64 void TIntermSymbol::traverse(TIntermTraverser *it) in traverse() argument
66 it->visitSymbol(this); in traverse()
69 void TIntermConstantUnion::traverse(TIntermTraverser *it) in traverse() argument
71 it->visitConstantUnion(this); in traverse()
84 void TIntermBinary::traverse(TIntermTraverser *it) in traverse() argument
91 if (it->preVisit) in traverse()
92 visit = it->visitBinary(EvPreVisit, this); in traverse()
98 it->incrementDepth(this); in traverse()
100 if (it->rightToLeft) { in traverse()
102 right->traverse(it); in traverse()
[all …]
|
| /external/OpenCSD/decoder/tests/snapshots-ete/002-ack_test_scr/ |
| D | test_TARMAC | 3 1 clk cpu0 IT (1) 10300000 14004000 O EL3h_s : B 0x10310000
4 2 clk cpu0 IT (2) 10310000 d2b01000 O EL3h_s : MOV x0,#0x80800000
6 3 clk cpu0 IT (3) 10310004 d51e2040 O EL3h_s : MSR TCR_EL3,x0
8 4 clk cpu0 IT (4) 10310008 d5033fdf O EL3h_s : ISB
28 5 clk cpu0 IT (5) 1031000c d2b01000 O EL3h_s : MOV x0,#0x80800000
30 6 clk cpu0 IT (6) 10310010 d51c2040 O EL3h_s : MSR TCR_EL2,x0
32 7 clk cpu0 IT (7) 10310014 d5033fdf O EL3h_s : ISB
35 8 clk cpu0 IT (8) 10310018 d2800040 O EL3h_s : MOV x0,#2
37 9 clk cpu0 IT (9) 1031001c d51c1100 O EL3h_s : MSR HCR_EL2,x0
39 10 clk cpu0 IT (10) 10310020 d5033fdf O EL3h_s : ISB
[all …]
|
| /external/webp/src/enc/ |
| D | iterator_enc.c | 22 static void InitLeft(VP8EncIterator* const it) { in InitLeft() argument
23 it->y_left_[-1] = it->u_left_[-1] = it->v_left_[-1] = in InitLeft()
24 (it->y_ > 0) ? 129 : 127; in InitLeft()
25 memset(it->y_left_, 129, 16); in InitLeft()
26 memset(it->u_left_, 129, 8); in InitLeft()
27 memset(it->v_left_, 129, 8); in InitLeft()
28 it->left_nz_[8] = 0; in InitLeft()
29 if (it->top_derr_ != NULL) { in InitLeft()
30 memset(&it->left_derr_, 0, sizeof(it->left_derr_)); in InitLeft()
34 static void InitTop(VP8EncIterator* const it) { in InitTop() argument
[all …]
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| /external/vixl/test/aarch32/traces/ |
| D | assembler-cond-rd-operand-rn-low-registers-in-it-block-tst-t32.h | 38 0x08, 0xbf, 0x00, 0x42 // It eq; tst eq r0 r0
41 0x08, 0xbf, 0x08, 0x42 // It eq; tst eq r0 r1
44 0x08, 0xbf, 0x10, 0x42 // It eq; tst eq r0 r2
47 0x08, 0xbf, 0x18, 0x42 // It eq; tst eq r0 r3
50 0x08, 0xbf, 0x20, 0x42 // It eq; tst eq r0 r4
53 0x08, 0xbf, 0x28, 0x42 // It eq; tst eq r0 r5
56 0x08, 0xbf, 0x30, 0x42 // It eq; tst eq r0 r6
59 0x08, 0xbf, 0x38, 0x42 // It eq; tst eq r0 r7
62 0x08, 0xbf, 0x01, 0x42 // It eq; tst eq r1 r0
65 0x08, 0xbf, 0x09, 0x42 // It eq; tst eq r1 r1
[all …]
|
| D | assembler-cond-rdlow-rnlow-rmlow-in-it-block-mul-t32.h | 38 0x08, 0xbf, 0x40, 0x43 // It eq; mul eq r0 r0 r0
41 0x08, 0xbf, 0x48, 0x43 // It eq; mul eq r0 r1 r0
44 0x08, 0xbf, 0x50, 0x43 // It eq; mul eq r0 r2 r0
47 0x08, 0xbf, 0x58, 0x43 // It eq; mul eq r0 r3 r0
50 0x08, 0xbf, 0x60, 0x43 // It eq; mul eq r0 r4 r0
53 0x08, 0xbf, 0x68, 0x43 // It eq; mul eq r0 r5 r0
56 0x08, 0xbf, 0x70, 0x43 // It eq; mul eq r0 r6 r0
59 0x08, 0xbf, 0x78, 0x43 // It eq; mul eq r0 r7 r0
62 0x08, 0xbf, 0x41, 0x43 // It eq; mul eq r1 r0 r1
65 0x08, 0xbf, 0x49, 0x43 // It eq; mul eq r1 r1 r1
[all …]
|
| D | assembler-cond-rd-operand-rn-low-registers-in-it-block-cmn-t32.h | 38 0x08, 0xbf, 0xc0, 0x42 // It eq; cmn eq r0 r0
41 0x08, 0xbf, 0xc8, 0x42 // It eq; cmn eq r0 r1
44 0x08, 0xbf, 0xd0, 0x42 // It eq; cmn eq r0 r2
47 0x08, 0xbf, 0xd8, 0x42 // It eq; cmn eq r0 r3
50 0x08, 0xbf, 0xe0, 0x42 // It eq; cmn eq r0 r4
53 0x08, 0xbf, 0xe8, 0x42 // It eq; cmn eq r0 r5
56 0x08, 0xbf, 0xf0, 0x42 // It eq; cmn eq r0 r6
59 0x08, 0xbf, 0xf8, 0x42 // It eq; cmn eq r0 r7
62 0x08, 0xbf, 0xc1, 0x42 // It eq; cmn eq r1 r0
65 0x08, 0xbf, 0xc9, 0x42 // It eq; cmn eq r1 r1
[all …]
|
| D | assembler-cond-rdlow-rnlow-operand-immediate-zero-in-it-block-rsb-t32.h | 38 0x08, 0xbf, 0x40, 0x42 // It eq; rsb eq r0 r0 0
41 0x08, 0xbf, 0x48, 0x42 // It eq; rsb eq r0 r1 0
44 0x08, 0xbf, 0x50, 0x42 // It eq; rsb eq r0 r2 0
47 0x08, 0xbf, 0x58, 0x42 // It eq; rsb eq r0 r3 0
50 0x08, 0xbf, 0x60, 0x42 // It eq; rsb eq r0 r4 0
53 0x08, 0xbf, 0x68, 0x42 // It eq; rsb eq r0 r5 0
56 0x08, 0xbf, 0x70, 0x42 // It eq; rsb eq r0 r6 0
59 0x08, 0xbf, 0x78, 0x42 // It eq; rsb eq r0 r7 0
62 0x08, 0xbf, 0x41, 0x42 // It eq; rsb eq r1 r0 0
65 0x08, 0xbf, 0x49, 0x42 // It eq; rsb eq r1 r1 0
[all …]
|
| D | assembler-cond-rdlow-operand-imm8-in-it-block-mov-t32.h | 38 0x78, 0xbf, 0x6f, 0x21 // It vc; mov vc r1 111
41 0x18, 0xbf, 0x86, 0x21 // It ne; mov ne r1 134
44 0x18, 0xbf, 0x15, 0x25 // It ne; mov ne r5 21
47 0x28, 0xbf, 0xdd, 0x26 // It cs; mov cs r6 221
50 0x28, 0xbf, 0x64, 0x23 // It cs; mov cs r3 100
53 0xd8, 0xbf, 0xd1, 0x22 // It le; mov le r2 209
56 0x98, 0xbf, 0x08, 0x27 // It ls; mov ls r7 8
59 0x28, 0xbf, 0xc9, 0x27 // It cs; mov cs r7 201
62 0x18, 0xbf, 0x70, 0x23 // It ne; mov ne r3 112
65 0xb8, 0xbf, 0x98, 0x24 // It lt; mov lt r4 152
[all …]
|
| D | assembler-cond-rdlow-rnlow-operand-immediate-imm3-in-it-block-sub-t32.h | 38 0x58, 0xbf, 0xc0, 0x1f // It pl; sub pl r0 r0 7
41 0x28, 0xbf, 0x50, 0x1f // It cs; sub cs r0 r2 5
44 0x98, 0xbf, 0x31, 0x1e // It ls; sub ls r1 r6 0
47 0x38, 0xbf, 0x8d, 0x1f // It cc; sub cc r5 r1 6
50 0x28, 0xbf, 0x15, 0x1e // It cs; sub cs r5 r2 0
53 0x68, 0xbf, 0xf5, 0x1f // It vs; sub vs r5 r6 7
56 0x98, 0xbf, 0x42, 0x1f // It ls; sub ls r2 r0 5
59 0x08, 0xbf, 0x63, 0x1f // It eq; sub eq r3 r4 5
62 0xb8, 0xbf, 0xec, 0x1f // It lt; sub lt r4 r5 7
65 0xb8, 0xbf, 0x7e, 0x1e // It lt; sub lt r6 r7 1
[all …]
|
| D | assembler-cond-rdlow-rnlow-operand-immediate-imm3-in-it-block-add-t32.h | 38 0x58, 0xbf, 0xc0, 0x1d // It pl; add pl r0 r0 7
41 0x28, 0xbf, 0x50, 0x1d // It cs; add cs r0 r2 5
44 0x98, 0xbf, 0x31, 0x1c // It ls; add ls r1 r6 0
47 0x38, 0xbf, 0x8d, 0x1d // It cc; add cc r5 r1 6
50 0x28, 0xbf, 0x15, 0x1c // It cs; add cs r5 r2 0
53 0x68, 0xbf, 0xf5, 0x1d // It vs; add vs r5 r6 7
56 0x98, 0xbf, 0x42, 0x1d // It ls; add ls r2 r0 5
59 0x08, 0xbf, 0x63, 0x1d // It eq; add eq r3 r4 5
62 0xb8, 0xbf, 0xec, 0x1d // It lt; add lt r4 r5 7
65 0xb8, 0xbf, 0x7e, 0x1c // It lt; add lt r6 r7 1
[all …]
|
| D | assembler-cond-rdlow-rnlow-operand-immediate-imm8-in-it-block-add-t32.h | 38 0x48, 0xbf, 0x5a, 0x33 // It mi; add mi r3 r3 90
41 0x78, 0xbf, 0x8a, 0x36 // It vc; add vc r6 r6 138
44 0x38, 0xbf, 0x48, 0x35 // It cc; add cc r5 r5 72
47 0xa8, 0xbf, 0xb5, 0x36 // It ge; add ge r6 r6 181
50 0x38, 0xbf, 0x8f, 0x31 // It cc; add cc r1 r1 143
53 0x78, 0xbf, 0x72, 0x35 // It vc; add vc r5 r5 114
56 0xa8, 0xbf, 0xc3, 0x34 // It ge; add ge r4 r4 195
59 0xb8, 0xbf, 0xcb, 0x30 // It lt; add lt r0 r0 203
62 0x88, 0xbf, 0x62, 0x31 // It hi; add hi r1 r1 98
65 0xc8, 0xbf, 0x1b, 0x1c // It gt; add gt r3 r3 0
[all …]
|
| D | assembler-cond-rdlow-operand-imm8-in-it-block-cmp-t32.h | 38 0x78, 0xbf, 0x6f, 0x29 // It vc; cmp vc r1 111
41 0x18, 0xbf, 0x86, 0x29 // It ne; cmp ne r1 134
44 0x18, 0xbf, 0x15, 0x2d // It ne; cmp ne r5 21
47 0x28, 0xbf, 0xdd, 0x2e // It cs; cmp cs r6 221
50 0x28, 0xbf, 0x64, 0x2b // It cs; cmp cs r3 100
53 0xd8, 0xbf, 0xd1, 0x2a // It le; cmp le r2 209
56 0x98, 0xbf, 0x08, 0x2f // It ls; cmp ls r7 8
59 0x28, 0xbf, 0xc9, 0x2f // It cs; cmp cs r7 201
62 0x18, 0xbf, 0x70, 0x2b // It ne; cmp ne r3 112
65 0xb8, 0xbf, 0x98, 0x2c // It lt; cmp lt r4 152
[all …]
|
| D | assembler-cond-rdlow-rnlow-operand-immediate-imm8-in-it-block-sub-t32.h | 38 0x48, 0xbf, 0x5a, 0x3b // It mi; sub mi r3 r3 90
41 0x78, 0xbf, 0x8a, 0x3e // It vc; sub vc r6 r6 138
44 0x38, 0xbf, 0x48, 0x3d // It cc; sub cc r5 r5 72
47 0xa8, 0xbf, 0xb5, 0x3e // It ge; sub ge r6 r6 181
50 0x38, 0xbf, 0x8f, 0x39 // It cc; sub cc r1 r1 143
53 0x78, 0xbf, 0x72, 0x3d // It vc; sub vc r5 r5 114
56 0xa8, 0xbf, 0xc3, 0x3c // It ge; sub ge r4 r4 195
59 0xb8, 0xbf, 0xcb, 0x38 // It lt; sub lt r0 r0 203
62 0x88, 0xbf, 0x62, 0x39 // It hi; sub hi r1 r1 98
65 0xc8, 0xbf, 0x1b, 0x1e // It gt; sub gt r3 r3 0
[all …]
|
| D | assembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-sbc-t32.h | 38 0xc8, 0xbf, 0x83, 0x41 // It gt; sbc gt r3 r3 r0
41 0xa8, 0xbf, 0x8e, 0x41 // It ge; sbc ge r6 r6 r1
44 0xc8, 0xbf, 0x8f, 0x41 // It gt; sbc gt r7 r7 r1
47 0xc8, 0xbf, 0x82, 0x41 // It gt; sbc gt r2 r2 r0
50 0x08, 0xbf, 0x95, 0x41 // It eq; sbc eq r5 r5 r2
53 0xc8, 0xbf, 0x80, 0x41 // It gt; sbc gt r0 r0 r0
56 0xb8, 0xbf, 0xa0, 0x41 // It lt; sbc lt r0 r0 r4
59 0x88, 0xbf, 0x9e, 0x41 // It hi; sbc hi r6 r6 r3
62 0xa8, 0xbf, 0xb7, 0x41 // It ge; sbc ge r7 r7 r6
65 0x08, 0xbf, 0xad, 0x41 // It eq; sbc eq r5 r5 r5
[all …]
|
| D | assembler-cond-rd-rn-operand-rm-rd-is-rn-in-it-block-add-t32.h | 38 0x58, 0xbf, 0x8d, 0x44 // It pl; add pl r13 r13 r1
41 0x48, 0xbf, 0xa3, 0x44 // It mi; add mi r11 r11 r4
44 0x68, 0xbf, 0xa4, 0x18 // It vs; add vs r4 r4 r2
47 0x98, 0xbf, 0xbf, 0x19 // It ls; add ls r7 r7 r6
50 0xd8, 0xbf, 0xa4, 0x18 // It le; add le r4 r4 r2
53 0x78, 0xbf, 0x83, 0x44 // It vc; add vc r11 r11 r0
56 0xd8, 0xbf, 0x5e, 0x44 // It le; add le r6 r6 r11
59 0x08, 0xbf, 0x4c, 0x44 // It eq; add eq r4 r4 r9
62 0x88, 0xbf, 0x94, 0x44 // It hi; add hi r12 r12 r2
65 0x88, 0xbf, 0x8b, 0x44 // It hi; add hi r11 r11 r1
[all …]
|
| D | assembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-asr-t32.h | 38 0xc8, 0xbf, 0x03, 0x41 // It gt; asr gt r3 r3 r0
41 0xa8, 0xbf, 0x0e, 0x41 // It ge; asr ge r6 r6 r1
44 0xc8, 0xbf, 0x0f, 0x41 // It gt; asr gt r7 r7 r1
47 0xc8, 0xbf, 0x02, 0x41 // It gt; asr gt r2 r2 r0
50 0x08, 0xbf, 0x15, 0x41 // It eq; asr eq r5 r5 r2
53 0xc8, 0xbf, 0x00, 0x41 // It gt; asr gt r0 r0 r0
56 0xb8, 0xbf, 0x20, 0x41 // It lt; asr lt r0 r0 r4
59 0x88, 0xbf, 0x1e, 0x41 // It hi; asr hi r6 r6 r3
62 0xa8, 0xbf, 0x37, 0x41 // It ge; asr ge r7 r7 r6
65 0x08, 0xbf, 0x2d, 0x41 // It eq; asr eq r5 r5 r5
[all …]
|
| D | assembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-eor-t32.h | 38 0xc8, 0xbf, 0x43, 0x40 // It gt; eor gt r3 r3 r0
41 0xa8, 0xbf, 0x4e, 0x40 // It ge; eor ge r6 r6 r1
44 0xc8, 0xbf, 0x4f, 0x40 // It gt; eor gt r7 r7 r1
47 0xc8, 0xbf, 0x42, 0x40 // It gt; eor gt r2 r2 r0
50 0x08, 0xbf, 0x55, 0x40 // It eq; eor eq r5 r5 r2
53 0xc8, 0xbf, 0x40, 0x40 // It gt; eor gt r0 r0 r0
56 0xb8, 0xbf, 0x60, 0x40 // It lt; eor lt r0 r0 r4
59 0x88, 0xbf, 0x5e, 0x40 // It hi; eor hi r6 r6 r3
62 0xa8, 0xbf, 0x77, 0x40 // It ge; eor ge r7 r7 r6
65 0x08, 0xbf, 0x6d, 0x40 // It eq; eor eq r5 r5 r5
[all …]
|
| D | assembler-cond-rd-rn-operand-rm-all-low-in-it-block-add-t32.h | 38 0x28, 0xbf, 0x4f, 0x19 // It cs; add cs r7 r1 r5
41 0xc8, 0xbf, 0x0b, 0x18 // It gt; add gt r3 r1 r0
44 0x98, 0xbf, 0x9c, 0x19 // It ls; add ls r4 r3 r6
47 0x58, 0xbf, 0x1d, 0x19 // It pl; add pl r5 r3 r4
50 0x88, 0xbf, 0x01, 0x18 // It hi; add hi r1 r0 r0
53 0x98, 0xbf, 0xd1, 0x18 // It ls; add ls r1 r2 r3
56 0x78, 0xbf, 0x1c, 0x19 // It vc; add vc r4 r3 r4
59 0x18, 0xbf, 0x39, 0x18 // It ne; add ne r1 r7 r0
62 0x98, 0xbf, 0x23, 0x18 // It ls; add ls r3 r4 r0
65 0xc8, 0xbf, 0xe6, 0x18 // It gt; add gt r6 r4 r3
[all …]
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| D | assembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-adc-t32.h | 38 0xc8, 0xbf, 0x43, 0x41 // It gt; adc gt r3 r3 r0
41 0xa8, 0xbf, 0x4e, 0x41 // It ge; adc ge r6 r6 r1
44 0xc8, 0xbf, 0x4f, 0x41 // It gt; adc gt r7 r7 r1
47 0xc8, 0xbf, 0x42, 0x41 // It gt; adc gt r2 r2 r0
50 0x08, 0xbf, 0x55, 0x41 // It eq; adc eq r5 r5 r2
53 0xc8, 0xbf, 0x40, 0x41 // It gt; adc gt r0 r0 r0
56 0xb8, 0xbf, 0x60, 0x41 // It lt; adc lt r0 r0 r4
59 0x88, 0xbf, 0x5e, 0x41 // It hi; adc hi r6 r6 r3
62 0xa8, 0xbf, 0x77, 0x41 // It ge; adc ge r7 r7 r6
65 0x08, 0xbf, 0x6d, 0x41 // It eq; adc eq r5 r5 r5
[all …]
|