1// Copyright 2016, VIXL authors 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are met: 6// 7// * Redistributions of source code must retain the above copyright notice, 8// this list of conditions and the following disclaimer. 9// * Redistributions in binary form must reproduce the above copyright notice, 10// this list of conditions and the following disclaimer in the documentation 11// and/or other materials provided with the distribution. 12// * Neither the name of ARM Limited nor the names of its contributors may be 13// used to endorse or promote products derived from this software without 14// specific prior written permission. 15// 16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27// Test description for instructions of the following forms: 28// MNEMONIC{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } 29// MNEMONIC{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } 30// 31// Note that this test only covers the cases where the optional shift 32// operand is not provided. The shift operands are tested in 33// "cond-rd-operand-rn-shift-amount-*-a32.json". 34 35{ 36 "mnemonics" : [ 37 "Cmn", // CMN{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1 38 "Cmp", // CMP{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1 39 "Mov", // MOV{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1 40 "Movs", // MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1 41 "Mvn", // MVN{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1 42 "Mvns", // MVNS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1 43 "Teq", // TEQ{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1 44 "Tst", // TST{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1 45 46 "Sxtb", // SXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1 47 "Sxtb16", // SXTB16{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1 48 "Sxth", // SXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1 49 "Uxtb", // UXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1 50 "Uxtb16", // UXTB16{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1 51 "Uxth" // UXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1 52 ], 53 "description" : { 54 "operands": [ 55 { 56 "name": "cond", 57 "type": "Condition" 58 }, 59 { 60 "name": "rd", 61 "type": "AllRegistersButPC" 62 }, 63 { 64 "name": "op", 65 "wrapper": "Operand", 66 "operands": [ 67 { 68 "name": "rn", 69 "type": "AllRegistersButPC" 70 } 71 ] 72 } 73 ], 74 "inputs": [ 75 { 76 "name": "apsr", 77 "type": "NZCV" 78 }, 79 { 80 "name": "rd", 81 "type": "Register" 82 }, 83 { 84 "name": "rn", 85 "type": "Register" 86 } 87 ] 88 }, 89 "test-files": [ 90 { 91 "type": "assembler", 92 "test-cases": [ 93 { 94 "name": "Operands", 95 "operands": [ 96 "cond", "rd", "rn" 97 ], 98 "operand-limit": 1000 99 } 100 ] 101 }, 102 { 103 "type": "simulator", 104 "test-cases": [ 105 { 106 "name": "Condition", 107 "operands": [ 108 "cond" 109 ], 110 "inputs": [ 111 "apsr" 112 ] 113 }, 114 // Test combinations of registers values with rd == rn. 115 { 116 "name": "RdIsRn", 117 "operands": [ 118 "rd", "rn" 119 ], 120 "inputs": [ 121 "rd", "rn" 122 ], 123 "operand-filter": "rd == rn", 124 "input-filter": "rd == rn" 125 }, 126 // Test combinations of registers values. 127 { 128 "name": "RdIsNotRn", 129 "operands": [ 130 "rd", "rn" 131 ], 132 "inputs": [ 133 "rd", "rn" 134 ], 135 "operand-filter": "rd != rn", 136 "operand-limit": 10, 137 "input-limit": 200 138 } 139 ] 140 } 141 ] 142} 143