Home
last modified time | relevance | path

Searched refs:lsl (Results 1 – 25 of 26) sorted by relevance

12

/art/runtime/interpreter/mterp/arm/
Dmain.S245 add pc, rIBASE, \reg, lsl #${handler_size_bits}
248 add pc, \base, \reg, lsl #${handler_size_bits}
255 ldr \reg, [rFP, \vreg, lsl #2]
258 str \reg, [rFP, \vreg, lsl #2]
260 str \reg, [rREFS, \vreg, lsl #2]
263 add ip, rFP, \vreg, lsl #2
267 add ip, rREFS, \vreg, lsl #2
271 str \reg, [rFP, \vreg, lsl #2]
272 str \reg, [rREFS, \vreg, lsl #2]
275 str \reg, [rREFS, \vreg, lsl #2]
[all …]
Darray.S22 add r0, r0, r1, lsl #$shift @ r0<- arrayObj + index*width
82 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width
114 add r0, r0, r1, lsl #$shift @ r0<- arrayObj + index*width
167 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width
198 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb
200 add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.)
Dcontrol_flow.S78 orrs rINST, r0, r3, lsl #16 @ rINST<- AAAAaaaa
131 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
133 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2
Dother.S32 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
62 mov r0, r0, lsl #16 @ r0<- BBBB0000
83 orr r0, r0, r2, lsl #16 @ r1<- BBBBbbbb
99 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word)
102 orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word)
128 orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb
141 mov r1, r1, lsl #16 @ r1<- BBBB0000
Dobject.S41 add r0, r0, r1, lsl #3 @ entry address within the cache
Dfloating_point.S354 orrs r3, r0, r1, lsl #12
/art/runtime/arch/arm64/
Dmemcmp16_arm64.S52 lsl limit, limit, #1 /* Half-words to bytes. */
78 lsl limit, limit, #3 /* Bits -> bytes. */
80 lsl mask, mask, limit
112 lsl tmp1, tmp1, #3 /* Bytes beyond alignment -> bits. */
Dquick_entrypoints_arm64.S1119 str w2, [x3, x1, lsl #2] // Heap reference = 32b
1127 str w2, [x3, x1, lsl #2] // Heap reference = 32b
1150 str w2, [x3, x1, lsl #2] // Heap reference = 32b
1607 lsl \xTemp1, \xCount, \xTemp0 // Calculate data size
1627 lsl \xTemp1, \xCount, #1
1633 lsl \xTemp1, \xCount, #2
1639 lsl \xTemp1, \xCount, #3
2048 add x0, x0, x2, lsl #1
2174 tst wIP0, wIP0, lsl #1
2249 lsl \wreg, wIP0, #LOCK_WORD_STATE_FORWARDING_ADDRESS_SHIFT
[all …]
/art/runtime/interpreter/mterp/arm64/
Dother.S31 orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb
61 lsl w0, w0, #16 // r0<- BBBB0000
82 orr w0, w0, w2, lsl #16 // w1<- BBBBbbbb
101 orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb
102 orr x0, x0, x2, lsl #32 // w0<- hhhhBBBBbbbb
103 orr x0, x0, x3, lsl #48 // w0<- HHHHhhhhBBBBbbbb
123 orr x0, x0, x2, lsl #16 // x0<- ssssssssBBBBbbbb
132 lsl x0, x0, #48
Dcontrol_flow.S80 orr wINST, w0, w1, lsl #16 // wINST<- AAAAaaaa
133 orr x0, x0, x1, lsl #16 // x0<- ssssssssBBBBbbbb
135 add x0, xPC, x0, lsl #1 // x0<- PC + ssssssssBBBBbbbb*2
Darray.S186 orr x1, x0, x1, lsl #16 // x1<- ssssssssBBBBbbbb
188 add x1, xPC, x1, lsl #1 // x1<- PC + ssssssssBBBBbbbb*2 (array data off.)
Dmain.S240 add \reg, xIBASE, \reg, lsl #${handler_size_bits}
244 add \reg, \base, \reg, lsl #${handler_size_bits}
566 add xPC, x0, x1, lsl #1 // generate new dex_pc_ptr
Dobject.S39 add x0, x0, x1, lsl #4 // entry address within the cache
/art/runtime/interpreter/mterp/arm64ng/
Dother.S10 orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb
37 lsl w0, w0, #16 // r0<- BBBB0000
94 orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb
95 orr x0, x0, x2, lsl #32 // w0<- hhhhBBBBbbbb
96 orr x0, x0, x3, lsl #48 // w0<- HHHHhhhhBBBBbbbb
116 orr x0, x0, x2, lsl #16 // x0<- ssssssssBBBBbbbb
125 lsl x0, x0, #48
Dcontrol_flow.S78 orr wINST, w0, w1, lsl #16 // wINST<- AAAAaaaa
131 orr x0, x0, x1, lsl #16 // x0<- ssssssssBBBBbbbb
133 add x0, xPC, x0, lsl #1 // x0<- PC + ssssssssBBBBbbbb*2
Darray.S133 orr x0, x0, x1, lsl #16 // x0<- ssssssssBBBBbbbb
135 add x0, xPC, x0, lsl #1 // x0<- PC + ssssssssBBBBbbbb*2 (array data off.)
Dmain.S177 add \reg, xIBASE, \reg, lsl #${handler_size_bits}
387 lsl x14, x14, #2
396 add \refs, x14, ip2, lsl #2
399 add \fp, \refs, ip, lsl #2
635 add ip2, xREFS, x3, lsl #2 // pointer to first argument in reference array
636 add ip2, ip2, x2, lsl #2 // pointer to last argument in reference array
637 add x5, xFP, x3, lsl #2 // pointer to first argument in register array
638 add x6, x5, x2, lsl #2 // pointer to last argument in register array
764 add ip, ip, ip2, lsl #32
823 add \gpr_reg64, ip, ip2, lsl #32
[all …]
/art/runtime/interpreter/mterp/armng/
Dmain.S182 add pc, rIBASE, \reg, lsl #${handler_size_bits}
189 ldr \reg, [rFP, \vreg, lsl #2]
192 ldr \reg, [rREFS, \vreg, lsl #2]
195 str \reg, [rFP, \vreg, lsl #2]
197 str \reg, [rREFS, \vreg, lsl #2]
200 str \reg, [rFP, \vreg, lsl #2]
201 str \reg, [rREFS, \vreg, lsl #2]
204 add \tmpreg, rFP, \vreg, lsl #2
207 str \tmpreg, [rREFS, \vreg, lsl #2]
216 ldr \vreg, [rFP, \vreg, lsl #2]
[all …]
Darray.S16 add r0, r0, r1, lsl #$shift @ r0<- arrayObj + index*width
87 add r0, r0, r1, lsl #$shift @ r0<- arrayObj + index*width
94 add r0, r0, r1, lsl #$shift @ r0<- arrayObj + index*width
141 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
143 add r0, rPC, r0, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.)
Dcontrol_flow.S78 orrs rINST, r0, r1, lsl #16 // wINST<- AAAAaaaa
131 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
133 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2
Dinvoke.S98 ldr r0, [r2, r3, lsl #2]
114 ldr r0, [r2, r4, lsl #2]
166 ldr r0, [r0, r2, lsl #2]
Dother.S10 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
37 mov r0, r0, lsl #16 @ r0<- BBBB0000
91 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word)
94 orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word)
120 orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb
133 mov r1, r1, lsl #16 @ r1<- BBBB0000
Darithmetic.S859 orr r0, r0, r1, lsl r3 @ r0<- r0 | (r1 << (32-r2))
884 orr r0, r0, r1, lsl r3 @ r0<- r0 | (r1 << (32-r2))
935 orr r0, r0, r1, lsl r3 @ r0<- r0 | (r1 << (32-r2))
960 orr r0, r0, r1, lsl r3 @ r0<- r0 | (r1 << (32-r2))
/art/runtime/arch/arm/
Dmemcmp16_arm.S202 orr ip, ip, lr, lsl #16
207 orreq ip, ip, lr, lsl #16
212 orreq ip, ip, lr, lsl #16
217 orreq ip, ip, lr, lsl #16
Dquick_entrypoints_arm.S731 str r2, [r3, r1, lsl #2]
738 str r2, [r3, r1, lsl #2]
759 str r2, [r3, r1, lsl #2]
1269 lsl r2, r1, r3 // Calculate data size
1299 lsl r2, r1, #1
1310 lsl r2, r1, #2
1321 lsl r2, r1, #3
1777 add r0, r0, r2, lsl #1
2043 lsl \reg, ip, #LOCK_WORD_STATE_FORWARDING_ADDRESS_SHIFT
2101 ldr ip, [ip, \index_reg, lsl #2] // 4 bytes.
[all …]

12