| /external/llvm-project/llvm/test/CodeGen/RISCV/ |
| D | addcarry.ll | 4 ; Test ADDCARRY node expansion on a target that does not currently support ADDCARRY.
5 ; Signed fixed point multiplication eventually expands down to an ADDCARRY.
|
| /external/tcpdump/ |
| D | in_cksum.c | 53 #define ADDCARRY(x) {if ((x) > 65535) (x) -= 65535;} macro
54 #define REDUCE {l_util.l = sum; sum = l_util.s[0] + l_util.s[1]; ADDCARRY(sum);}
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| /external/iputils/ |
| D | clockdiff.c | 40 #undef ADDCARRY
41 #define ADDCARRY(sum) { \ macro
69 ADDCARRY(sum); in in_cksum()
82 ADDCARRY(sum); in in_cksum()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 243 ADDCARRY, SUBCARRY, enumerator
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 283 ADDCARRY, enumerator
|
| /external/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.h | 100 SADDO, SSUBO, UADDO, USUBO, ADDCARRY, SUBCARRY, enumerator
|
| D | SystemZISelLowering.cpp | 186 setOperationAction(ISD::ADDCARRY, VT, Custom); in SystemZTargetLowering()
3691 while (Carry.getOpcode() == ISD::ADDCARRY) in isAddCarryChain()
3723 case ISD::ADDCARRY: in lowerADDSUBCARRY()
3727 BaseOp = SystemZISD::ADDCARRY; in lowerADDSUBCARRY()
5396 case ISD::ADDCARRY: in LowerOperation()
5583 OPCODE(ADDCARRY); in getTargetNodeName()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.h | 99 SADDO, SSUBO, UADDO, USUBO, ADDCARRY, SUBCARRY, enumerator
|
| D | SystemZISelLowering.cpp | 182 setOperationAction(ISD::ADDCARRY, VT, Custom); in SystemZTargetLowering()
3639 while (Carry.getOpcode() == ISD::ADDCARRY) in isAddCarryChain()
3671 case ISD::ADDCARRY: in lowerADDSUBCARRY()
3675 BaseOp = SystemZISD::ADDCARRY; in lowerADDSUBCARRY()
5140 case ISD::ADDCARRY: in LowerOperation()
5327 OPCODE(ADDCARRY); in getTargetNodeName()
|
| D | SystemZOperators.td | 281 def z_addcarry_1 : SDNode<"SystemZISD::ADDCARRY", SDT_ZBinaryWithCarry>;
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 152 case ISD::ADDCARRY: in PromoteIntegerResult()
1498 case ISD::ADDCARRY: in PromoteIntegerOperand()
2121 case ISD::ADDCARRY: in ExpandIntegerResult()
2522 N->getOpcode() == ISD::ADD ? ISD::ADDCARRY : ISD::SUBCARRY, in ExpandIntRes_ADDSUB()
2529 Hi = DAG.getNode(ISD::ADDCARRY, dl, VTList, HiOps); in ExpandIntRes_ADDSUB()
2694 CarryOp = ISD::ADDCARRY; in ExpandIntRes_UADDSUBO()
2770 unsigned CarryOp = N->getOpcode() == ISD::SADDO_CARRY ? ISD::ADDCARRY in ExpandIntRes_SADDSUBO_CARRY()
2900 ISD::ADDCARRY, TLI.getTypeToExpandTo(*DAG.getContext(), NVT)); in ExpandIntRes_ABS()
2908 Hi = DAG.getNode(ISD::ADDCARRY, dl, VTList, Hi, Sign, Lo.getValue(1)); in ExpandIntRes_ABS()
|
| D | SelectionDAGDumper.cpp | 295 case ISD::ADDCARRY: return "addcarry"; in getOperationName()
|
| D | DAGCombiner.cpp | 1632 case ISD::ADDCARRY: return visitADDCARRY(N); in visit()
2592 if (V.getOpcode() != ISD::ADDCARRY && V.getOpcode() != ISD::SUBCARRY && in getAsCarry()
2693 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1)) && in visitADDLikeCommutative()
2695 return DAG.getNode(ISD::ADDCARRY, DL, N1->getVTList(), in visitADDLikeCommutative()
2699 if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT)) in visitADDLikeCommutative()
2701 return DAG.getNode(ISD::ADDCARRY, DL, in visitADDLikeCommutative()
2834 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1))) { in visitUADDOLike()
2838 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0, Y, in visitUADDOLike()
2843 if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT)) in visitUADDOLike()
2845 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0, in visitUADDOLike()
[all …]
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 753 case ISD::ADDCARRY: in Select()
1103 unsigned Opc = N->getOpcode() == ISD::ADDCARRY ? AMDGPU::V_ADDC_U32_e64 in SelectAddcSubb()
1110 unsigned Opc = N->getOpcode() == ISD::ADDCARRY ? AMDGPU::S_ADD_CO_PSEUDO in SelectAddcSubb()
1126 if ((IsAdd && (UI->getOpcode() != ISD::ADDCARRY)) || in SelectUADDO_USUBO()
|
| D | AMDGPUISelLowering.cpp | 1841 SDValue Add1_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Lo, in LowerUDIVREM64()
1843 SDValue Add1_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Hi, in LowerUDIVREM64()
1856 SDValue Add2_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_Lo, in LowerUDIVREM64()
1858 SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc, in LowerUDIVREM64()
1860 SDValue Add2_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add2_HiC, in LowerUDIVREM64()
|
| D | SIISelLowering.cpp | 278 setOperationAction(ISD::ADDCARRY, MVT::i32, Legal); in SITargetLowering()
286 setOperationAction(ISD::ADDCARRY, MVT::i64, Legal); in SITargetLowering()
831 setTargetDAGCombine(ISD::ADDCARRY); in SITargetLowering()
10310 Opc == ISD::ANY_EXTEND || Opc == ISD::ADDCARRY) in performAddCombine()
10326 Opc = (Opc == ISD::SIGN_EXTEND) ? ISD::SUBCARRY : ISD::ADDCARRY; in performAddCombine()
10329 case ISD::ADDCARRY: { in performAddCombine()
10334 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), RHS->getVTList(), Args); in performAddCombine()
10367 Opc = (Opc == ISD::SIGN_EXTEND) ? ISD::ADDCARRY : ISD::SUBCARRY; in performSubCombine()
10400 if ((LHSOpc == ISD::ADD && Opc == ISD::ADDCARRY) || in performAddCarrySubCarryCombine()
10753 case ISD::ADDCARRY: in PerformDAGCombine()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 291 case ISD::ADDCARRY: return "addcarry"; in getOperationName()
|
| D | LegalizeIntegerTypes.cpp | 150 case ISD::ADDCARRY: in PromoteIntegerResult()
1296 case ISD::ADDCARRY: in PromoteIntegerOperand()
1892 case ISD::ADDCARRY: in ExpandIntegerResult()
2265 N->getOpcode() == ISD::ADD ? ISD::ADDCARRY : ISD::SUBCARRY, in ExpandIntRes_ADDSUB()
2272 Hi = DAG.getNode(ISD::ADDCARRY, dl, VTList, HiOps); in ExpandIntRes_ADDSUB()
2437 CarryOp = ISD::ADDCARRY; in ExpandIntRes_UADDSUBO()
|
| D | DAGCombiner.cpp | 1514 case ISD::ADDCARRY: return visitADDCARRY(N); in visit()
2389 if (V.getOpcode() != ISD::ADDCARRY && V.getOpcode() != ISD::SUBCARRY && in getAsCarry()
2490 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1)) && in visitADDLikeCommutative()
2492 return DAG.getNode(ISD::ADDCARRY, DL, N1->getVTList(), in visitADDLikeCommutative()
2496 if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT)) in visitADDLikeCommutative()
2498 return DAG.getNode(ISD::ADDCARRY, DL, in visitADDLikeCommutative()
2649 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1))) { in visitUADDOLike()
2653 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0, Y, in visitUADDOLike()
2658 if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT)) in visitUADDOLike()
2660 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0, in visitUADDOLike()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1400 setOperationAction(ISD::ADDCARRY, VT, Expand); in HexagonTargetLowering()
1403 setOperationAction(ISD::ADDCARRY, MVT::i64, Custom); in HexagonTargetLowering()
2842 if (Opc == ISD::ADDCARRY) in LowerAddSubCarry()
2915 case ISD::ADDCARRY: in LowerOperation()
|
| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1533 setOperationAction(ISD::ADDCARRY, VT, Expand); in HexagonTargetLowering()
1536 setOperationAction(ISD::ADDCARRY, MVT::i64, Custom); in HexagonTargetLowering()
3012 if (Opc == ISD::ADDCARRY) in LowerAddSubCarry()
3085 case ISD::ADDCARRY: in LowerOperation()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 1712 SDValue Add1_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Lo, in LowerUDIVREM64()
1714 SDValue Add1_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Hi, in LowerUDIVREM64()
1727 SDValue Add2_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_Lo, in LowerUDIVREM64()
1729 SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc, in LowerUDIVREM64()
1731 SDValue Add2_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add2_HiC, in LowerUDIVREM64()
|
| D | SIISelLowering.cpp | 247 setOperationAction(ISD::ADDCARRY, MVT::i32, Legal); in SITargetLowering()
255 setOperationAction(ISD::ADDCARRY, MVT::i64, Legal); in SITargetLowering()
717 setTargetDAGCombine(ISD::ADDCARRY); in SITargetLowering()
9557 Opc == ISD::ANY_EXTEND || Opc == ISD::ADDCARRY) in performAddCombine()
9573 Opc = (Opc == ISD::SIGN_EXTEND) ? ISD::SUBCARRY : ISD::ADDCARRY; in performAddCombine()
9576 case ISD::ADDCARRY: { in performAddCombine()
9581 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), RHS->getVTList(), Args); in performAddCombine()
9614 Opc = (Opc == ISD::SIGN_EXTEND) ? ISD::ADDCARRY : ISD::SUBCARRY; in performSubCombine()
9647 if ((LHSOpc == ISD::ADD && Opc == ISD::ADDCARRY) || in performAddCarrySubCarryCombine()
9994 case ISD::ADDCARRY: in PerformDAGCombine()
|
| D | AMDGPUISelDAGToDAG.cpp | 767 case ISD::ADDCARRY: in Select()
1066 unsigned Opc = N->getOpcode() == ISD::ADDCARRY ? AMDGPU::V_ADDC_U32_e64 in SelectAddcSubb()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 673 setOperationAction(ISD::ADDCARRY, VT, Expand); in initActions()
|