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Searched refs:AMDGPUTargetLowering (Results 1 – 25 of 33) sorted by relevance

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/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp49 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { in getEquivalentMemType()
58 EVT AMDGPUTargetLowering::getEquivalentBitType(LLVMContext &Ctx, EVT VT) { in getEquivalentBitType()
66 AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM, in AMDGPUTargetLowering() function in AMDGPUTargetLowering
491 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const { in getVectorIdxTy()
495 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const { in isSelectSupported()
501 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { in isFPImmLegal()
507 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const { in ShouldShrinkFPConstant()
512 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N, in shouldReduceLoadWidth()
535 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy, in isLoadBitCastBeneficial()
554 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const { in isCheapToSpeculateCttz()
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DAMDGPUTargetTransformInfo.h26 class AMDGPUTargetLowering; variable
34 const AMDGPUTargetLowering *TLI;
37 const AMDGPUTargetLowering *getTLI() const { return TLI; } in getTLI()
DAMDGPUCallLowering.h22 class AMDGPUTargetLowering; variable
26 AMDGPUCallLowering(const AMDGPUTargetLowering &TLI);
DAMDGPUCallLowering.cpp28 AMDGPUCallLowering::AMDGPUCallLowering(const AMDGPUTargetLowering &TLI) in AMDGPUCallLowering()
DAMDGPUSubtarget.h121 const AMDGPUTargetLowering *getTargetLowering() const override;
446 inline const AMDGPUTargetLowering *AMDGPUSubtarget::getTargetLowering() const { in getTargetLowering()
DAMDGPUISelLowering.h27 class AMDGPUTargetLowering : public TargetLowering {
121 AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
DR600ISelLowering.h25 class R600TargetLowering final : public AMDGPUTargetLowering {
DR600ISelLowering.cpp35 : AMDGPUTargetLowering(TM, STI), Gen(STI.getGeneration()) { in R600TargetLowering()
238 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); in EmitInstrWithCustomInserter()
616 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerOperation()
671 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerOperation()
833 AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG); in ReplaceNodeResults()
921 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG); in LowerGlobalAddress()
1355 if (SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG)) in LowerSTORE()
1953 default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()
2070 if (SDValue Ret = AMDGPUTargetLowering::PerformDAGCombine(N, DCI)) in PerformDAGCombine()
2166 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()
DSIISelLowering.h23 class SITargetLowering final : public AMDGPUTargetLowering {
DSIISelLowering.cpp57 : AMDGPUTargetLowering(TM, STI) { in SITargetLowering()
947 return AMDGPUTargetLowering::LowerReturn(Chain, CallConv, isVarArg, Outs, in LowerReturn()
1159 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); in EmitInstrWithCustomInserter()
1230 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerOperation()
1567 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG); in LowerGlobalAddress()
1915 return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerINTRINSIC_WO_CHAIN()
2522 if (SDValue Base = AMDGPUTargetLowering::performAndCombine(N, DCI)) in performAndCombine()
2865 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()
3061 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()
3378 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT); in CreateLiveInRegister()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp42 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { in getEquivalentMemType()
51 unsigned AMDGPUTargetLowering::numBitsUnsigned(SDValue Op, SelectionDAG &DAG) { in numBitsUnsigned()
57 unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) { in numBitsSigned()
65 AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM, in AMDGPUTargetLowering() function in AMDGPUTargetLowering
588 bool AMDGPUTargetLowering::allUsesHaveSourceMods(const SDNode *N, in allUsesHaveSourceMods()
612 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const { in getVectorIdxTy()
616 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const { in isSelectSupported()
622 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, in isFPImmLegal()
630 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const { in ShouldShrinkFPConstant()
635 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N, in shouldReduceLoadWidth()
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DAMDGPUTargetTransformInfo.h35 class AMDGPUTargetLowering; variable
73 const AMDGPUTargetLowering *TLI;
106 const AMDGPUTargetLowering *getTLI() const { return TLI; } in getTLI()
240 const AMDGPUTargetLowering *TLI;
251 const AMDGPUTargetLowering *getTLI() const { return TLI; } in getTLI()
DAMDGPUCallLowering.h22 class AMDGPUTargetLowering; variable
45 AMDGPUCallLowering(const AMDGPUTargetLowering &TLI);
DR600ISelLowering.h24 class R600TargetLowering final : public AMDGPUTargetLowering {
DAMDGPUISelLowering.h28 class AMDGPUTargetLowering : public TargetLowering {
147 AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
DR600ISelLowering.cpp58 : AMDGPUTargetLowering(TM, STI), Subtarget(&STI), Gen(STI.getGeneration()) { in R600TargetLowering()
319 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); in EmitInstrWithCustomInserter()
479 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerOperation()
657 AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG); in ReplaceNodeResults()
747 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG); in LowerGlobalAddress()
1962 if (SDValue Ret = AMDGPUTargetLowering::PerformDAGCombine(N, DCI)) in PerformDAGCombine()
2066 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()
DSIISelLowering.h23 class SITargetLowering final : public AMDGPUTargetLowering {
DAMDGPUISelDAGToDAG.cpp1638 N = AMDGPUTargetLowering::stripBitcast(SDValue(N,0)).getNode(); in findMemSDNode()
1644 dyn_cast<MemSDNode>(AMDGPUTargetLowering::stripBitcast(V))) in findMemSDNode()
2717 const AMDGPUTargetLowering& Lowering = in PostprocessISelDAG()
2718 *static_cast<const AMDGPUTargetLowering*>(getTargetLowering()); in PostprocessISelDAG()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp46 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { in getEquivalentMemType()
55 unsigned AMDGPUTargetLowering::numBitsUnsigned(SDValue Op, SelectionDAG &DAG) { in numBitsUnsigned()
61 unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) { in numBitsSigned()
69 AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM, in AMDGPUTargetLowering() function in AMDGPUTargetLowering
659 bool AMDGPUTargetLowering::allUsesHaveSourceMods(const SDNode *N, in allUsesHaveSourceMods()
683 EVT AMDGPUTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT, in getTypeForExtReturn()
694 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const { in getVectorIdxTy()
698 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const { in isSelectSupported()
704 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, in isFPImmLegal()
712 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const { in ShouldShrinkFPConstant()
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DAMDGPUCallLowering.h22 class AMDGPUTargetLowering; variable
47 AMDGPUCallLowering(const AMDGPUTargetLowering &TLI);
DAMDGPUTargetTransformInfo.h35 class AMDGPUTargetLowering; variable
111 const AMDGPUTargetLowering *getTLI() const { return TLI; } in getTLI()
276 const AMDGPUTargetLowering *TLI;
287 const AMDGPUTargetLowering *getTLI() const { return TLI; } in getTLI()
DR600ISelLowering.h24 class R600TargetLowering final : public AMDGPUTargetLowering {
DAMDGPUISelLowering.h29 class AMDGPUTargetLowering : public TargetLowering {
146 AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
DR600ISelLowering.cpp58 : AMDGPUTargetLowering(TM, STI), Subtarget(&STI), Gen(STI.getGeneration()) { in R600TargetLowering()
319 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); in EmitInstrWithCustomInserter()
479 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerOperation()
663 AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG); in ReplaceNodeResults()
752 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG); in LowerGlobalAddress()
1968 if (SDValue Ret = AMDGPUTargetLowering::PerformDAGCombine(N, DCI)) in PerformDAGCombine()
2072 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()
DSIISelLowering.h23 class SITargetLowering final : public AMDGPUTargetLowering {

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