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Searched refs:ANY_EXTEND (Results 1 – 25 of 139) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/RISCV/
Dpr40333.ll7 ; loop would be created in DAGCombine, converting ANY_EXTEND to SIGN_EXTEND
/external/llvm/test/CodeGen/AArch64/
Darm64-AnInfiniteLoopInDAGCombine.ll10 ; As we think the (2) optimization from SIGN_EXTEND to ANY_EXTEND is
/external/llvm-project/llvm/test/CodeGen/AArch64/
Darm64-AnInfiniteLoopInDAGCombine.ll10 ; As we think the (2) optimization from SIGN_EXTEND to ANY_EXTEND is
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h398 ANY_EXTEND, enumerator
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp112 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break; in PromoteIntegerResult()
267 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); in PromoteIntRes_BITCAST()
280 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
294 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, in PromoteIntRes_BITCAST()
308 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
341 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), in PromoteIntRes_BUILD_PAIR()
466 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); in PromoteIntRes_INT_EXTEND()
879 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; in PromoteIntegerOperand()
992 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op); in PromoteIntOp_ANY_EXTEND()
1158 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); in PromoteIntOp_SIGN_EXTEND()
[all …]
DTargetLowering.cpp413 SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND, in ShrinkDemandedOp()
696 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) { in SimplifyDemandedBits()
710 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), in SimplifyDemandedBits()
732 SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, in SimplifyDemandedBits()
968 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, in SimplifyDemandedBits()
990 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, in SimplifyDemandedBits()
1022 case ISD::ANY_EXTEND: { in SimplifyDemandedBits()
1722 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), in SimplifySetCC()
3268 ISD::ANY_EXTEND, dl, VT, Result); in expandUnalignedLoad()
DDAGCombiner.cpp988 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) in PromoteOperand()
990 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); in PromoteOperand()
1397 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); in visit()
1486 case ISD::ANY_EXTEND: in combine()
2725 (N0.getOpcode() == ISD::ANY_EXTEND && in SimplifyBinOpWithSameOpcodeHands()
3105 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { in visitAND()
3234 (N0.getOpcode() == ISD::ANY_EXTEND && in visitAND()
3236 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; in visitAND()
4104 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || in MatchRotate()
4108 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || in MatchRotate()
[all …]
DLegalizeVectorTypes.cpp69 case ISD::ANY_EXTEND: in ScalarizeVectorResult()
436 case ISD::ANY_EXTEND: in ScalarizeVectorOperand()
513 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), in ScalarizeVecOp_EXTRACT_VECTOR_ELT()
661 case ISD::ANY_EXTEND: in SplitVectorResult()
1504 case ISD::ANY_EXTEND: in SplitVectorOperand()
2135 case ISD::ANY_EXTEND: in WidenVectorResult()
2456 Val = DAG.getNode(ISD::ANY_EXTEND, DL, WidenSVT, Val); in WidenVecRes_EXTEND_VECTOR_INREG()
3090 case ISD::ANY_EXTEND: in WidenVectorOperand()
3176 case ISD::ANY_EXTEND: in WidenVecOp_EXTEND()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h532 ANY_EXTEND, enumerator
/external/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h681 ANY_EXTEND, enumerator
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp119 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break; in PromoteIntegerResult()
308 case ISD::ANY_EXTEND: in PromoteIntRes_AtomicCmpSwap()
344 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); in PromoteIntRes_BITCAST()
347 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftPromotedHalf(InOp)); in PromoteIntRes_BITCAST()
360 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
377 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, in PromoteIntRes_BITCAST()
419 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, InOp); in PromoteIntRes_BITCAST()
425 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
476 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), in PromoteIntRes_BUILD_PAIR()
637 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); in PromoteIntRes_INT_EXTEND()
[all …]
DLegalizeVectorTypes.cpp73 case ISD::ANY_EXTEND: in ScalarizeVectorResult()
403 return DAG.getNode(ISD::ANY_EXTEND, DL, EltVT, Op); in ScalarizeVecRes_VecInregOp()
573 case ISD::ANY_EXTEND: in ScalarizeVectorOperand()
711 : DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, Res); in ScalarizeVecOp_EXTRACT_VECTOR_ELT()
840 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Res); in ScalarizeVecOp_VECREDUCE()
961 case ISD::ANY_EXTEND: in SplitVectorResult()
1544 Vec = DAG.getNode(ISD::ANY_EXTEND, dl, VecVT, Vec); in SplitVecRes_INSERT_VECTOR_ELT()
1547 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, EltVT, Elt); in SplitVecRes_INSERT_VECTOR_ELT()
2106 case ISD::ANY_EXTEND: in SplitVectorOperand()
2341 Vec = DAG.getNode(ISD::ANY_EXTEND, dl, VecVT, Vec); in SplitVecOp_EXTRACT_VECTOR_ELT()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp117 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break; in PromoteIntegerResult()
305 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); in PromoteIntRes_BITCAST()
318 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
333 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, in PromoteIntRes_BITCAST()
376 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, InOp); in PromoteIntRes_BITCAST()
382 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
427 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), in PromoteIntRes_BUILD_PAIR()
583 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); in PromoteIntRes_INT_EXTEND()
1249 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; in PromoteIntegerOperand()
1398 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op); in PromoteIntOp_ANY_EXTEND()
[all …]
DLegalizeVectorTypes.cpp72 case ISD::ANY_EXTEND: in ScalarizeVectorResult()
393 return DAG.getNode(ISD::ANY_EXTEND, DL, EltVT, Op); in ScalarizeVecRes_VecInregOp()
567 case ISD::ANY_EXTEND: in ScalarizeVectorOperand()
696 : DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, Res); in ScalarizeVecOp_EXTRACT_VECTOR_ELT()
795 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Res); in ScalarizeVecOp_VECREDUCE()
900 case ISD::ANY_EXTEND: in SplitVectorResult()
1438 Vec = DAG.getNode(ISD::ANY_EXTEND, dl, VecVT, Vec); in SplitVecRes_INSERT_VECTOR_ELT()
1441 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, EltVT, Elt); in SplitVecRes_INSERT_VECTOR_ELT()
1972 case ISD::ANY_EXTEND: in SplitVectorOperand()
2199 Vec = DAG.getNode(ISD::ANY_EXTEND, dl, VecVT, Vec); in SplitVecOp_EXTRACT_VECTOR_ELT()
[all …]
DDAGCombiner.cpp1140 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) in PromoteOperand()
1142 return DAG.getNode(ISD::ANY_EXTEND, DL, PVT, Op); in PromoteOperand()
1561 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); in visit()
1668 case ISD::ANY_EXTEND: in combine()
4381 if (HandOpcode == ISD::ANY_EXTEND || HandOpcode == ISD::ZERO_EXTEND || in hoistLogicOpWithSameOpcodeHands()
4397 if (HandOpcode == ISD::ANY_EXTEND && LegalTypes && in hoistLogicOpWithSameOpcodeHands()
5107 if (Not.getOpcode() == ISD::ANY_EXTEND) in combineShiftAnd1ToBitTest()
5217 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { in visitAND()
5344 (N0.getOpcode() == ISD::ANY_EXTEND && in visitAND()
5347 LoadSDNode *LN0 = N0->getOpcode() == ISD::ANY_EXTEND in visitAND()
[all …]
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVISelLowering.cpp566 DAG.getNode(ISD::ANY_EXTEND, DL, Subtarget.getXLenVT(), Op0); in LowerOperation()
573 SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0); in LowerOperation()
1052 SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0)); in customLegalizeToWOp()
1053 SDValue NewOp1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1)); in customLegalizeToWOp()
1063 SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0)); in customLegalizeToWOpWithSExt()
1064 SDValue NewOp1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1)); in customLegalizeToWOpWithSExt()
1190 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0)); in ReplaceNodeResults()
1202 SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, in ReplaceNodeResults()
1218 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0)); in ReplaceNodeResults()
1220 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1)); in ReplaceNodeResults()
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/external/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp1126 StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal); in LowerCall()
1359 theVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, theVal); in LowerCall()
1863 Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op1); in LowerSelect()
1864 Op2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op2); in LowerSelect()
1989 ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal); in LowerSTOREVector()
2227 P = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, P); in LowerFormalArguments()
2249 Elt0 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt0); in LowerFormalArguments()
2250 Elt1 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt1); in LowerFormalArguments()
2292 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt); in LowerFormalArguments()
2523 TmpVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, TmpVal); in LowerReturn()
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/external/llvm/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp820 case ISD::ANY_EXTEND: in expandRxSBG()
933 if (RISBG.Input.getOpcode() != ISD::ANY_EXTEND && in tryRISBGZero()
1025 if (RxSBG[I].Input.getOpcode() != ISD::ANY_EXTEND && in tryRxSBG()
DSystemZISelLowering.h482 return ISD::ANY_EXTEND; in getExtendForAtomicOps()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp845 case ISD::ANY_EXTEND: in expandRxSBG()
965 if (RISBG.Input.getOpcode() != ISD::ANY_EXTEND && in tryRISBGZero()
1071 if (RxSBG[I].Input.getOpcode() != ISD::ANY_EXTEND && in tryRxSBG()
1864 Result = CurDAG->getNode(ISD::ANY_EXTEND, DL, VT, Result); in expandSelectBoolean()
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp849 case ISD::ANY_EXTEND: in expandRxSBG()
969 if (RISBG.Input.getOpcode() != ISD::ANY_EXTEND && in tryRISBGZero()
1075 if (RxSBG[I].Input.getOpcode() != ISD::ANY_EXTEND && in tryRxSBG()
1909 Result = CurDAG->getNode(ISD::ANY_EXTEND, DL, VT, Result); in expandSelectBoolean()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp878 case ISD::ANY_EXTEND: in PreprocessISelDAG()
886 unsigned NewOpc = N->getOpcode() == ISD::ANY_EXTEND in PreprocessISelDAG()
1688 if (Shift.getOpcode() == ISD::ANY_EXTEND && Shift.hasOneUse() && in foldMaskedShiftToScaledMask()
1715 SDValue NewX = DAG.getNode(ISD::ANY_EXTEND, DL, VT, X); in foldMaskedShiftToScaledMask()
1804 if (X.getOpcode() == ISD::ANY_EXTEND) { in foldMaskAndShiftToScale()
2109 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND || in matchAddressRecursively()
3438 NBits = CurDAG->getNode(ISD::ANY_EXTEND, DL, NVT, NBits); in matchBitExtract()
3495 Control = CurDAG->getNode(ISD::ANY_EXTEND, DL, XVT, Control); in matchBitExtract()
3806 if (Shift.getOpcode() == ISD::ANY_EXTEND && Shift.hasOneUse() && in tryShrinkShlLogicImm()
3883 SDValue NewX = CurDAG->getNode(ISD::ANY_EXTEND, dl, NVT, X); in tryShrinkShlLogicImm()
/external/llvm-project/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp1038 case ISD::ANY_EXTEND: in PreprocessISelDAG()
1047 assert(N->getOpcode() == ISD::ANY_EXTEND && in PreprocessISelDAG()
1051 NewOpc = N->getOpcode() == ISD::ANY_EXTEND in PreprocessISelDAG()
1868 if (Shift.getOpcode() == ISD::ANY_EXTEND && Shift.hasOneUse() && in foldMaskedShiftToScaledMask()
1895 SDValue NewX = DAG.getNode(ISD::ANY_EXTEND, DL, VT, X); in foldMaskedShiftToScaledMask()
1984 if (X.getOpcode() == ISD::ANY_EXTEND) { in foldMaskAndShiftToScale()
2289 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND || in matchAddressRecursively()
3536 NBits = CurDAG->getNode(ISD::ANY_EXTEND, DL, NVT, NBits); in matchBitExtract()
3594 Control = CurDAG->getNode(ISD::ANY_EXTEND, DL, XVT, Control); in matchBitExtract()
3905 if (Shift.getOpcode() == ISD::ANY_EXTEND && Shift.hasOneUse() && in tryShrinkShlLogicImm()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVISelLowering.cpp417 SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0); in LowerOperation()
853 SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0)); in customLegalizeToWOp()
854 SDValue NewOp1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1)); in customLegalizeToWOp()
864 SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0)); in customLegalizeToWOpWithSExt()
865 SDValue NewOp1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1)); in customLegalizeToWOpWithSExt()
1005 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0.getOperand(0)); in PerformDAGCombine()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonISelLoweringHVX.cpp125 setOperationAction(ISD::ANY_EXTEND, T, Custom); in initializeHVXLowering()
158 setOperationAction(ISD::ANY_EXTEND, T, Custom); in initializeHVXLowering()
258 setOperationAction(ISD::ANY_EXTEND, VecTy, Custom); in initializeHVXLowering()
2070 case ISD::ANY_EXTEND: return LowerHvxAnyExt(Op, DAG); in LowerHvxOperation()
2102 case ISD::ANY_EXTEND: in LowerHvxOperationWrapper()
2144 case ISD::ANY_EXTEND: in ReplaceHvxNodeResults()

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