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Searched refs:AllOnes (Results 1 – 25 of 52) sorted by relevance

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/external/llvm-project/llvm/lib/Target/Lanai/
DLanaiISelLowering.cpp1325 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) { in isZeroOrAllOnes() argument
1326 return AllOnes ? isAllOnesConstant(N) : isNullConstant(N); in isZeroOrAllOnes()
1347 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC, in isConditionalZeroOrAllOnes() argument
1357 if (isZeroOrAllOnes(N1, AllOnes)) { in isConditionalZeroOrAllOnes()
1362 if (isZeroOrAllOnes(N2, AllOnes)) { in isConditionalZeroOrAllOnes()
1371 if (AllOnes) in isConditionalZeroOrAllOnes()
1388 Invert = !AllOnes; in isConditionalZeroOrAllOnes()
1389 if (AllOnes) in isConditionalZeroOrAllOnes()
1420 bool AllOnes) { in combineSelectAndUse() argument
1426 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps, in combineSelectAndUse()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiISelLowering.cpp1325 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) { in isZeroOrAllOnes() argument
1326 return AllOnes ? isAllOnesConstant(N) : isNullConstant(N); in isZeroOrAllOnes()
1347 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC, in isConditionalZeroOrAllOnes() argument
1357 if (isZeroOrAllOnes(N1, AllOnes)) { in isConditionalZeroOrAllOnes()
1362 if (isZeroOrAllOnes(N2, AllOnes)) { in isConditionalZeroOrAllOnes()
1371 if (AllOnes) in isConditionalZeroOrAllOnes()
1388 Invert = !AllOnes; in isConditionalZeroOrAllOnes()
1389 if (AllOnes) in isConditionalZeroOrAllOnes()
1420 bool AllOnes) { in combineSelectAndUse() argument
1426 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps, in combineSelectAndUse()
[all …]
/external/llvm/lib/Target/Lanai/
DLanaiISelLowering.cpp1279 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) { in isZeroOrAllOnes() argument
1280 return AllOnes ? isAllOnesConstant(N) : isNullConstant(N); in isZeroOrAllOnes()
1301 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC, in isConditionalZeroOrAllOnes() argument
1311 if (isZeroOrAllOnes(N1, AllOnes)) { in isConditionalZeroOrAllOnes()
1316 if (isZeroOrAllOnes(N2, AllOnes)) { in isConditionalZeroOrAllOnes()
1325 if (AllOnes) in isConditionalZeroOrAllOnes()
1342 Invert = !AllOnes; in isConditionalZeroOrAllOnes()
1343 if (AllOnes) in isConditionalZeroOrAllOnes()
1374 bool AllOnes) { in combineSelectAndUse() argument
1380 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps, in combineSelectAndUse()
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/external/llvm-project/llvm/unittests/CodeGen/GlobalISel/
DPatternMatchTest.cpp433 auto AllOnes = B.buildConstant(LLT::scalar(64), -1); in TEST_F() local
434 EXPECT_TRUE(mi_match(AllOnes.getReg(0), *MRI, m_AllOnesInt())); in TEST_F()
478 auto AllOnes = B.buildConstant(LLT::scalar(64), -1); in TEST_F() local
479 auto NotInst1 = B.buildXor(s64, Copies[0], AllOnes); in TEST_F()
487 auto NotInst2 = B.buildXor(s64, AllOnes, Copies[1]); in TEST_F()
/external/llvm-project/llvm/include/llvm/ADT/
DBitfields.h107 static constexpr Unsigned AllOnes = ~Unsigned(0); // 11111111 member
109 static constexpr Unsigned Umax = AllOnes >> (TypeBits - Bits); // 00111111
/external/llvm-project/llvm/test/Transforms/LowerTypeTests/
Dexport-allones.ll159 ; SUMMARY-NEXT: Kind: AllOnes
172 ; SUMMARY-NEXT: Kind: AllOnes
Dexport-icall.ll66 ; SUMMARY-NEXT: Kind: AllOnes
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp757 SDValue AllOnes = DAG.getConstant( in ExpandSELECT() local
759 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes); in ExpandSELECT()
968 SDValue AllOnes = DAG.getConstant( in ExpandVSELECT() local
970 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes); in ExpandVSELECT()
/external/llvm-project/llvm/unittests/ADT/
DAPIntTest.cpp650 APInt AllOnes(129, "0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", 16); in TEST() local
653 APInt AddLL = AllOnes + Two; in TEST()
656 APInt AddLR = AllOnes + getRValue("2", RawDataR); in TEST()
670 APInt AddLK = AllOnes + 2; in TEST()
673 APInt AddKL = 2 + AllOnes; in TEST()
722 APInt AllOnes(129, "0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", 16); in TEST() local
725 APInt SubLL = HighOneLowOne - AllOnes; in TEST()
734 AllOnes; in TEST()
746 EXPECT_EQ(SubLK, AllOnes); in TEST()
755 EXPECT_EQ(SubRK, AllOnes); in TEST()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/
DInstCombineShifts.cpp1014 Constant *AllOnes = ConstantInt::getAllOnesValue(Ty); in visitShl() local
1015 Value *Mask = Builder.CreateShl(AllOnes, Op1); in visitShl()
1168 Constant *AllOnes = ConstantInt::getAllOnesValue(Ty); in visitLShr() local
1169 Value *Mask = Builder.CreateLShr(AllOnes, Op1); in visitLShr()
DInstCombineSimplifyDemanded.cpp676 APInt AllOnes = APInt::getAllOnesValue(BitWidth); in SimplifyDemandedUseBits() local
677 if (SimplifyDemandedBits(I, 0, AllOnes, Known2, Depth + 1) || in SimplifyDemandedUseBits()
678 SimplifyDemandedBits(I, 1, AllOnes, Known2, Depth + 1)) in SimplifyDemandedUseBits()
/external/llvm-project/llvm/lib/Transforms/InstCombine/
DInstCombineShifts.cpp999 Constant *AllOnes = ConstantInt::getAllOnesValue(Ty); in visitShl() local
1000 Value *Mask = Builder.CreateShl(AllOnes, Op1); in visitShl()
1159 Constant *AllOnes = ConstantInt::getAllOnesValue(Ty); in visitLShr() local
1160 Value *Mask = Builder.CreateLShr(AllOnes, Op1); in visitLShr()
DInstCombineSimplifyDemanded.cpp720 APInt AllOnes = APInt::getAllOnesValue(BitWidth); in SimplifyDemandedUseBits() local
721 if (SimplifyDemandedBits(I, 0, AllOnes, Known2, Depth + 1) || in SimplifyDemandedUseBits()
722 SimplifyDemandedBits(I, 1, AllOnes, Known2, Depth + 1)) in SimplifyDemandedUseBits()
/external/llvm/lib/Transforms/InstCombine/
DInstCombineSimplifyDemanded.cpp721 APInt AllOnes = APInt::getAllOnesValue(BitWidth); in SimplifyDemandedUseBits() local
722 if (SimplifyDemandedBits(I->getOperandUse(0), AllOnes, KnownZero2, in SimplifyDemandedUseBits()
724 SimplifyDemandedBits(I->getOperandUse(1), AllOnes, KnownZero2, in SimplifyDemandedUseBits()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp944 SDValue AllOnes = DAG.getConstant( in ExpandSELECT() local
946 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes); in ExpandSELECT()
1186 SDValue AllOnes = DAG.getConstant( in ExpandVSELECT() local
1188 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes); in ExpandVSELECT()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DModuleSummaryIndexYAML.h24 io.enumCase(value, "AllOnes", TypeTestResolution::AllOnes);
/external/llvm-project/llvm/include/llvm/IR/
DModuleSummaryIndexYAML.h25 io.enumCase(value, "AllOnes", TypeTestResolution::AllOnes);
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp1043 SDValue AllOnes = DAG.getConstant( in ExpandSELECT() local
1045 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes); in ExpandSELECT()
1287 SDValue AllOnes = DAG.getConstant( in ExpandVSELECT() local
1289 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes); in ExpandVSELECT()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/IPO/
DLowerTypeTests.cpp773 if (TIL.TheKind == TypeTestResolution::AllOnes) in lowerTypeTestCall()
927 TIL.TheKind == TypeTestResolution::AllOnes) { in exportTypeId()
1008 TIL.TheKind == TypeTestResolution::AllOnes) { in importTypeId()
1132 : TypeTestResolution::AllOnes; in lowerTypeTestCalls()
/external/llvm-project/llvm/lib/Transforms/IPO/
DLowerTypeTests.cpp783 if (TIL.TheKind == TypeTestResolution::AllOnes) in lowerTypeTestCall()
936 TIL.TheKind == TypeTestResolution::AllOnes) { in exportTypeId()
1017 TIL.TheKind == TypeTestResolution::AllOnes) { in importTypeId()
1145 : TypeTestResolution::AllOnes; in lowerTypeTestCalls()
/external/llvm-project/llvm/test/Assembler/
Dthinlto-summary.ll60 ; Test the AllOnes resolution, and all kinds of WholeProgramDevirtResolution
/external/llvm/test/CodeGen/X86/
Dvselect.ll127 ; Fold (vselect (build_vector AllOnes), N1, N2) -> N1
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp4278 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff), in LowerFCOPYSIGN() local
4280 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes); in LowerFCOPYSIGN()
4282 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes)); in LowerFCOPYSIGN()
8588 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) { in isZeroOrAllOnes() argument
8589 return AllOnes ? isAllOnesConstant(N) : isNullConstant(N); in isZeroOrAllOnes()
8604 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, in isConditionalZeroOrAllOnes() argument
8614 if (isZeroOrAllOnes(N1, AllOnes)) { in isConditionalZeroOrAllOnes()
8619 if (isZeroOrAllOnes(N2, AllOnes)) { in isConditionalZeroOrAllOnes()
8628 if (AllOnes) in isConditionalZeroOrAllOnes()
8637 Invert = !AllOnes; in isConditionalZeroOrAllOnes()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMISelLowering.cpp5536 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createVMOVModImm(0xe, 0xff), in LowerFCOPYSIGN() local
5538 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes); in LowerFCOPYSIGN()
5540 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes)); in LowerFCOPYSIGN()
7784 SDValue AllOnes = in PromoteMVEPredVector() local
7786 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v16i8, AllOnes); in PromoteMVEPredVector()
7807 DAG.getNode(ISD::VSELECT, dl, MVT::v16i8, RecastV1, AllOnes, AllZeroes); in PromoteMVEPredVector()
10963 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) { in isZeroOrAllOnes() argument
10964 return AllOnes ? isAllOnesConstant(N) : isNullConstant(N); in isZeroOrAllOnes()
10979 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, in isConditionalZeroOrAllOnes() argument
10989 if (isZeroOrAllOnes(N1, AllOnes)) { in isConditionalZeroOrAllOnes()
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMISelLowering.cpp5783 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createVMOVModImm(0xe, 0xff), in LowerFCOPYSIGN() local
5785 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes); in LowerFCOPYSIGN()
5787 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes)); in LowerFCOPYSIGN()
8090 SDValue AllOnes = in PromoteMVEPredVector() local
8092 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v16i8, AllOnes); in PromoteMVEPredVector()
8113 DAG.getNode(ISD::VSELECT, dl, MVT::v16i8, RecastV1, AllOnes, AllZeroes); in PromoteMVEPredVector()
11410 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) { in isZeroOrAllOnes() argument
11411 return AllOnes ? isAllOnesConstant(N) : isNullConstant(N); in isZeroOrAllOnes()
11426 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, in isConditionalZeroOrAllOnes() argument
11436 if (isZeroOrAllOnes(N1, AllOnes)) { in isConditionalZeroOrAllOnes()
[all …]

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