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Searched refs:AllocationOrder (Results 1 – 25 of 26) sorted by relevance

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/external/llvm-project/llvm/unittests/CodeGen/
DAllocationOrderTest.cpp15 std::vector<MCPhysReg> loadOrder(const AllocationOrder &O, unsigned Limit = 0) { in loadOrder()
30 AllocationOrder O(std::move(Hints), Order, false); in TEST()
37 AllocationOrder O(std::move(Hints), Order, false); in TEST()
44 AllocationOrder O(std::move(Hints), Order, true); in TEST()
51 AllocationOrder O(std::move(Hints), Order, false); in TEST()
60 AllocationOrder O(std::move(Hints), Order, false); in TEST()
70 AllocationOrder O(std::move(Hints), Order, true); in TEST()
77 AllocationOrder O(std::move(Hints), Order, false); in TEST()
84 AllocationOrder O(std::move(Hints), Order, false); in TEST()
93 AllocationOrder O(std::move(Hints), Order, false); in TEST()
[all …]
/external/llvm-project/llvm/lib/CodeGen/
DAllocationOrder.h30 class LLVM_LIBRARY_VISIBILITY AllocationOrder {
45 const AllocationOrder &AO;
49 Iterator(const AllocationOrder &AO, int Pos) : AO(AO), Pos(Pos) {} in Iterator()
84 static AllocationOrder create(unsigned VirtReg, const VirtRegMap &VRM,
90 AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order, in AllocationOrder() function
DAllocationOrder.cpp29 AllocationOrder AllocationOrder::create(unsigned VirtReg, const VirtRegMap &VRM, in create()
52 return AllocationOrder(std::move(Hints), Order, HardHints); in create()
DRegAllocGreedy.cpp456 const AllocationOrder &Order);
459 const AllocationOrder &Order);
461 const AllocationOrder &Order,
473 MCRegister getCheapestEvicteeWeight(const AllocationOrder &Order,
482 Register tryAssign(LiveInterval&, AllocationOrder&,
485 unsigned tryEvict(LiveInterval&, AllocationOrder&,
488 MCRegister tryRegionSplit(LiveInterval &, AllocationOrder &,
492 AllocationOrder &Order,
503 AllocationOrder &Order, MCRegister PhysReg,
507 unsigned tryBlockSplit(LiveInterval&, AllocationOrder&,
[all …]
DRegisterScavenging.cpp362 const LiveRegUnits &LiveOut, ArrayRef<MCPhysReg> AllocationOrder, in findSurvivorBackwards() argument
380 for (MCPhysReg Reg : AllocationOrder) { in findSurvivorBackwards()
398 for (MCPhysReg Reg : AllocationOrder) { in findSurvivorBackwards()
570 ArrayRef<MCPhysReg> AllocationOrder = RC.getRawAllocationOrder(MF); in scavengeRegisterBackwards() local
572 findSurvivorBackwards(*MRI, MBBI, To, LiveUnits, AllocationOrder, in scavengeRegisterBackwards()
DRegAllocFast.cpp749 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtReg() local
750 for (MCPhysReg PhysReg : AllocationOrder) { in allocVirtReg()
802 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtRegUndef() local
803 assert(!AllocationOrder.empty() && "Allocation order must not be empty"); in allocVirtRegUndef()
804 PhysReg = AllocationOrder[0]; in allocVirtRegUndef()
930 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in useVirtReg() local
931 setPhysReg(MI, MO, *AllocationOrder.begin()); in useVirtReg()
DCMakeLists.txt3 AllocationOrder.cpp
DRegAllocBasic.cpp268 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix); in selectOrSplit()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DAllocationOrder.cpp29 AllocationOrder::AllocationOrder(unsigned VirtReg, in AllocationOrder() function in AllocationOrder
DAllocationOrder.h29 class LLVM_LIBRARY_VISIBILITY AllocationOrder {
43 AllocationOrder(unsigned VirtReg,
DRegAllocGreedy.cpp455 const AllocationOrder &Order);
458 const AllocationOrder &Order);
460 const AllocationOrder &Order,
472 unsigned getCheapestEvicteeWeight(const AllocationOrder &Order,
481 unsigned tryAssign(LiveInterval&, AllocationOrder&,
484 unsigned tryEvict(LiveInterval&, AllocationOrder&,
487 unsigned tryRegionSplit(LiveInterval&, AllocationOrder&,
492 AllocationOrder &Order,
502 unsigned tryAssignCSRFirstTime(LiveInterval &VirtReg, AllocationOrder &Order,
506 unsigned tryBlockSplit(LiveInterval&, AllocationOrder&,
[all …]
DRegisterScavenging.cpp381 const LiveRegUnits &LiveOut, ArrayRef<MCPhysReg> AllocationOrder, in findSurvivorBackwards() argument
399 for (MCPhysReg Reg : AllocationOrder) { in findSurvivorBackwards()
417 for (MCPhysReg Reg : AllocationOrder) { in findSurvivorBackwards()
589 ArrayRef<MCPhysReg> AllocationOrder = RC.getRawAllocationOrder(MF); in scavengeRegisterBackwards() local
591 findSurvivorBackwards(*MRI, MBBI, To, LiveUnits, AllocationOrder, in scavengeRegisterBackwards()
DRegAllocFast.cpp716 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtReg() local
717 for (MCPhysReg PhysReg : AllocationOrder) { in allocVirtReg()
743 definePhysReg(MI, *AllocationOrder.begin(), regFree); in allocVirtReg()
744 assignVirtToPhysReg(LR, *AllocationOrder.begin()); in allocVirtReg()
763 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtRegUndef() local
764 assert(!AllocationOrder.empty() && "Allocation order must not be empty"); in allocVirtRegUndef()
765 PhysReg = AllocationOrder[0]; in allocVirtRegUndef()
DCMakeLists.txt3 AllocationOrder.cpp
DRegAllocBasic.cpp262 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix); in selectOrSplit()
/external/llvm/lib/CodeGen/
DAllocationOrder.cpp30 AllocationOrder::AllocationOrder(unsigned VirtReg, in AllocationOrder() function in AllocationOrder
DAllocationOrder.h29 class LLVM_LIBRARY_VISIBILITY AllocationOrder {
39 AllocationOrder(unsigned VirtReg,
DRegAllocGreedy.cpp366 unsigned tryAssign(LiveInterval&, AllocationOrder&,
368 unsigned tryEvict(LiveInterval&, AllocationOrder&,
370 unsigned tryRegionSplit(LiveInterval&, AllocationOrder&,
374 AllocationOrder &Order,
383 unsigned tryAssignCSRFirstTime(LiveInterval &VirtReg, AllocationOrder &Order,
387 unsigned tryBlockSplit(LiveInterval&, AllocationOrder&,
389 unsigned tryInstructionSplit(LiveInterval&, AllocationOrder&,
391 unsigned tryLocalSplit(LiveInterval&, AllocationOrder&,
393 unsigned trySplit(LiveInterval&, AllocationOrder&,
395 unsigned tryLastChanceRecoloring(LiveInterval &, AllocationOrder &,
[all …]
DCMakeLists.txt3 AllocationOrder.cpp
DRegAllocBasic.cpp226 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix); in selectOrSplit()
/external/llvm-project/llvm/test/CodeGen/ARM/
Dfavor-low-reg-for-Osize.ll9 ; DEBUG: AllocationOrder(GPR) = [ $r0 $r1 $r2 $r3 $r4 $r5 $r6 $r7 $r12 $lr $r8 $r9 $r10 $r1…
20 ; DEBUG: AllocationOrder(GPR) = [ $r0 $r1 $r2 $r3 $r12 $lr $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 ]
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dcompute-regpressure.ll4 ; DEBUG-COUNT-3: AllocationOrder(VRSAVERC) = [ ]
/external/llvm-project/llvm/utils/gn/secondary/llvm/lib/CodeGen/
DBUILD.gn21 "AllocationOrder.cpp",
/external/swiftshader/third_party/llvm-10.0/
DAndroid.bp108 "llvm/lib/CodeGen/AllocationOrder.cpp",
DBUILD.gn264 "llvm/lib/CodeGen/AllocationOrder.cpp",

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