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/external/arm-trusted-firmware/plat/imx/common/include/
Dimx_clock.h27 #define CCM_CCGR_SETTING0_DOM_CLK_RUN BIT(0)
28 #define CCM_CCGR_SETTING0_DOM_CLK_RUN_WAIT BIT(1)
29 #define CCM_CCGR_SETTING0_DOM_CLK_ALWAYS (BIT(1) | BIT(0))
31 #define CCM_CCGR_SETTING1_DOM_CLK_RUN BIT(4)
32 #define CCM_CCGR_SETTING1_DOM_CLK_RUN_WAIT BIT(5)
33 #define CCM_CCGR_SETTING1_DOM_CLK_ALWAYS (BIT(5) | BIT(4))
35 #define CCM_CCGR_SETTING2_DOM_CLK_RUN BIT(8)
36 #define CCM_CCGR_SETTING2_DOM_CLK_RUN_WAIT BIT(9)
37 #define CCM_CCGR_SETTING2_DOM_CLK_ALWAYS (BIT(9) | BIT(8))
39 #define CCM_CCGR_SETTING3_DOM_CLK_RUN BIT(12)
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Dimx_io_mux.h26 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_ALT1_SD3_CD_B BIT(0)
97 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT1_I2C1_SCL BIT(0)
98 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT2_PMIC_READY BIT(1)
99 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT3_ECSPI1_SS1 (BIT(1) | BIT(0))
100 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT4_ENET2_1588_EVENT0_IN BIT(3)
101 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT5_GPIO4_IO0 (BIT(2) | BIT(0))
102 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT6_ENET1_MDIO (BIT(2) | BIT(1))
103 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_SION BIT(3)
107 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT1_I2C1_SDA BIT(0)
108 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT2_SAI3_MCLK BIT(1)
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/external/arm-trusted-firmware/drivers/renesas/rcar/pfc/V3M/
Dpfc_init_v3m.c16 #define GPSR0_DU_EXODDF_DU_ODDF_DISP_CDE BIT(21)
17 #define GPSR0_DU_EXVSYNC_DU_VSYNC BIT(20)
18 #define GPSR0_DU_EXHSYNC_DU_HSYNC BIT(19)
19 #define GPSR0_DU_DOTCLKOUT BIT(18)
20 #define GPSR0_DU_DB7 BIT(17)
21 #define GPSR0_DU_DB6 BIT(16)
22 #define GPSR0_DU_DB5 BIT(15)
23 #define GPSR0_DU_DB4 BIT(14)
24 #define GPSR0_DU_DB3 BIT(13)
25 #define GPSR0_DU_DB2 BIT(12)
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/external/arm-trusted-firmware/drivers/imx/uart/
Dimx_uart.h12 #define IMX_UART_RXD_CHARRDY BIT(15)
13 #define IMX_UART_RXD_ERR BIT(14)
14 #define IMX_UART_RXD_OVERRUN BIT(13)
15 #define IMX_UART_RXD_FRMERR BIT(12)
16 #define IMX_UART_RXD_BRK BIT(11)
17 #define IMX_UART_RXD_PRERR BIT(10)
22 #define IMX_UART_CR1_ADEN BIT(15)
23 #define IMX_UART_CR1_ADBR BIT(14)
24 #define IMX_UART_CR1_TRDYEN BIT(13)
25 #define IMX_UART_CR1_IDEN BIT(12)
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/external/arm-trusted-firmware/include/drivers/st/
Dstm32_uart_regs.h26 #define USART_CR1_UE BIT(0)
27 #define USART_CR1_UESM BIT(1)
28 #define USART_CR1_RE BIT(2)
29 #define USART_CR1_TE BIT(3)
30 #define USART_CR1_IDLEIE BIT(4)
31 #define USART_CR1_RXNEIE BIT(5)
32 #define USART_CR1_TCIE BIT(6)
33 #define USART_CR1_TXEIE BIT(7)
34 #define USART_CR1_PEIE BIT(8)
35 #define USART_CR1_PS BIT(9)
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Dstm32_i2c.h15 #define I2C_CR1_PE BIT(0)
16 #define I2C_CR1_TXIE BIT(1)
17 #define I2C_CR1_RXIE BIT(2)
18 #define I2C_CR1_ADDRIE BIT(3)
19 #define I2C_CR1_NACKIE BIT(4)
20 #define I2C_CR1_STOPIE BIT(5)
21 #define I2C_CR1_TCIE BIT(6)
22 #define I2C_CR1_ERRIE BIT(7)
24 #define I2C_CR1_ANFOFF BIT(12)
25 #define I2C_CR1_SWRST BIT(13)
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Dstm32mp1_rcc.h240 #define RCC_TZCR_TZEN BIT(0)
241 #define RCC_TZCR_MCKPROT BIT(1)
246 #define RCC_SELR_SRCRDY BIT(31)
276 #define RCC_DIVR_DIVRDY BIT(31)
285 #define RCC_TIMGXPRER_TIMGXPRE BIT(0)
294 #define RCC_BDCR_LSEON BIT(0)
295 #define RCC_BDCR_LSEBYP BIT(1)
296 #define RCC_BDCR_LSERDY BIT(2)
297 #define RCC_BDCR_DIGBYP BIT(3)
300 #define RCC_BDCR_LSECSSON BIT(8)
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Dstm32mp1_ddr_regs.h255 #define DDRCTRL_MSTR_DDR3 BIT(0)
256 #define DDRCTRL_MSTR_LPDDR2 BIT(2)
257 #define DDRCTRL_MSTR_LPDDR3 BIT(3)
260 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF BIT(12)
261 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER BIT(13)
262 #define DDRCTRL_MSTR_DLL_OFF_MODE BIT(15)
265 #define DDRCTRL_STAT_OPERATING_MODE_NORMAL BIT(0)
266 #define DDRCTRL_STAT_OPERATING_MODE_SR (BIT(0) | BIT(1))
268 #define DDRCTRL_STAT_SELFREF_TYPE_ASR (BIT(4) | BIT(5))
269 #define DDRCTRL_STAT_SELFREF_TYPE_SR BIT(5)
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/external/arm-trusted-firmware/plat/imx/imx8m/imx8mp/include/
Dgpc_reg.h39 #define MASK_DSM_TRIGGER_A53 BIT(31)
40 #define IRQ_SRC_A53_WUP BIT(30)
42 #define IRQ_SRC_C1 BIT(29)
43 #define IRQ_SRC_C0 BIT(28)
44 #define IRQ_SRC_C3 BIT(23)
45 #define IRQ_SRC_C2 BIT(22)
46 #define CPU_CLOCK_ON_LPM BIT(14)
47 #define A53_CLK_ON_LPM BIT(14)
48 #define MASTER0_LPM_HSK BIT(6)
49 #define MASTER1_LPM_HSK BIT(7)
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/external/arm-trusted-firmware/plat/imx/imx8m/imx8mm/include/
Dgpc_reg.h37 #define MASK_DSM_TRIGGER_A53 BIT(31)
38 #define IRQ_SRC_A53_WUP BIT(30)
40 #define IRQ_SRC_C1 BIT(29)
41 #define IRQ_SRC_C0 BIT(28)
42 #define IRQ_SRC_C3 BIT(23)
43 #define IRQ_SRC_C2 BIT(22)
44 #define CPU_CLOCK_ON_LPM BIT(14)
45 #define A53_CLK_ON_LPM BIT(14)
46 #define MASTER0_LPM_HSK BIT(6)
47 #define MASTER1_LPM_HSK BIT(7)
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/external/wpa_supplicant_8/src/common/
Dieee802_11_defs.h32 #define WLAN_GET_SEQ_FRAG(seq) ((seq) & (BIT(3) | BIT(2) | BIT(1) | BIT(0)))
34 (((seq) & (~(BIT(3) | BIT(2) | BIT(1) | BIT(0)))) >> 4)
93 #define WLAN_CAPABILITY_ESS BIT(0)
94 #define WLAN_CAPABILITY_IBSS BIT(1)
95 #define WLAN_CAPABILITY_CF_POLLABLE BIT(2)
96 #define WLAN_CAPABILITY_CF_POLL_REQUEST BIT(3)
97 #define WLAN_CAPABILITY_PRIVACY BIT(4)
98 #define WLAN_CAPABILITY_SHORT_PREAMBLE BIT(5)
99 #define WLAN_CAPABILITY_PBCC BIT(6)
100 #define WLAN_CAPABILITY_CHANNEL_AGILITY BIT(7)
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Ddefs.h12 #define WPA_CIPHER_NONE BIT(0)
13 #define WPA_CIPHER_WEP40 BIT(1)
14 #define WPA_CIPHER_WEP104 BIT(2)
15 #define WPA_CIPHER_TKIP BIT(3)
16 #define WPA_CIPHER_CCMP BIT(4)
17 #define WPA_CIPHER_AES_128_CMAC BIT(5)
18 #define WPA_CIPHER_GCMP BIT(6)
19 #define WPA_CIPHER_SMS4 BIT(7)
20 #define WPA_CIPHER_GCMP_256 BIT(8)
21 #define WPA_CIPHER_CCMP_256 BIT(9)
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/external/arm-trusted-firmware/plat/imx/imx8m/imx8mn/include/
Dgpc_reg.h37 #define MASK_DSM_TRIGGER_A53 BIT(31)
38 #define IRQ_SRC_A53_WUP BIT(30)
40 #define IRQ_SRC_C1 BIT(29)
41 #define IRQ_SRC_C0 BIT(28)
42 #define IRQ_SRC_C3 BIT(23)
43 #define IRQ_SRC_C2 BIT(22)
44 #define CPU_CLOCK_ON_LPM BIT(14)
45 #define A53_CLK_ON_LPM BIT(14)
46 #define MASTER0_LPM_HSK BIT(6)
47 #define MASTER1_LPM_HSK BIT(7)
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/external/arm-trusted-firmware/drivers/renesas/rcar/pfc/E3/
Dpfc_init_e3.c14 #define GPSR0_SDA4 BIT(17)
15 #define GPSR0_SCL4 BIT(16)
16 #define GPSR0_D15 BIT(15)
17 #define GPSR0_D14 BIT(14)
18 #define GPSR0_D13 BIT(13)
19 #define GPSR0_D12 BIT(12)
20 #define GPSR0_D11 BIT(11)
21 #define GPSR0_D10 BIT(10)
22 #define GPSR0_D9 BIT(9)
23 #define GPSR0_D8 BIT(8)
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/external/arm-trusted-firmware/drivers/imx/usdhc/
Dimx_usdhc.h34 #define XFERTYPE_DPSEL BIT(21)
35 #define XFERTYPE_CICEN BIT(20)
36 #define XFERTYPE_CCCEN BIT(19)
37 #define XFERTYPE_RSPTYP_136 BIT(16)
38 #define XFERTYPE_RSPTYP_48 BIT(17)
39 #define XFERTYPE_RSPTYP_48_BUSY (BIT(16) | BIT(17))
42 #define PSTATE_DAT0 BIT(24)
43 #define PSTATE_DLA BIT(2)
44 #define PSTATE_CDIHB BIT(1)
45 #define PSTATE_CIHB BIT(0)
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/external/arm-trusted-firmware/plat/mediatek/mt8192/include/
Dmcucfg.h23 #define MP2_CPU0_STANDBYWFE BIT(4)
24 #define MP2_CPU1_STANDBYWFE BIT(5)
30 #define sw_spark_en BIT(0)
31 #define sw_no_wait_for_q_channel BIT(1)
32 #define sw_fsm_override BIT(2)
33 #define sw_logic_pre1_pdb BIT(3)
34 #define sw_logic_pre2_pdb BIT(4)
35 #define sw_logic_pdb BIT(5)
36 #define sw_iso BIT(6)
38 #define sw_sram_isointb BIT(13)
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/external/arm-trusted-firmware/plat/imx/imx8m/imx8mq/include/
Dgpc_reg.h37 #define MASK_DSM_TRIGGER_A53 BIT(31)
38 #define IRQ_SRC_A53_WUP BIT(30)
40 #define IRQ_SRC_C1 BIT(29)
41 #define IRQ_SRC_C0 BIT(28)
42 #define IRQ_SRC_C3 BIT(23)
43 #define IRQ_SRC_C2 BIT(22)
44 #define CPU_CLOCK_ON_LPM BIT(14)
45 #define A53_CLK_ON_LPM BIT(14)
46 #define MASTER0_LPM_HSK BIT(6)
47 #define MASTER1_LPM_HSK BIT(7)
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/external/arm-trusted-firmware/drivers/marvell/comphy/
Dphy-comphy-3700.h17 #define COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT BIT(0)
19 #define COMPHY_SELECTOR_USB3_GBE1_SEL_BIT BIT(4)
21 #define COMPHY_SELECTOR_USB3_PHY_SEL_BIT BIT(8)
46 #define PU_IVREF_BIT BIT(15)
47 #define PU_PLL_BIT BIT(14)
48 #define PU_RX_BIT BIT(13)
49 #define PU_TX_BIT BIT(12)
50 #define PU_TX_INTP_BIT BIT(11)
51 #define PU_DFE_BIT BIT(10)
52 #define RESET_DTL_RX_BIT BIT(9)
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/external/llvm-project/llvm/test/CodeGen/PowerPC/
Daix-crspill.ll2 ; RUN: --verify-machineinstrs < %s | FileCheck --check-prefix=64BIT %s
5 ; RUN: --verify-machineinstrs < %s | FileCheck --check-prefix=32BIT %s
23 ; 64BIT-LABEL: .killOne:
25 ; 64BIT: mflr 0
26 ; 64BIT-NEXT: std 0, 16(1)
27 ; 64BIT-NEXT: mfcr 12
28 ; 64BIT-NEXT: stw 12, 8(1)
29 ; 64BIT: stdu 1, -112(1)
31 ; 64BIT: # Clobber CR
32 ; 64BIT: bl .do_something
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Daix-cc-byval-mem.ll4 ; RUN: FileCheck --check-prefixes=CHECK,32BIT %s
13 ; RUN: FileCheck --check-prefixes=CHECK,64BIT %s
55 ; 32BIT: fixedStack:
56 ; 32BIT-NEXT: - { id: 0, type: default, offset: 56, size: 4, alignment: 8, stack-id: default,
57 ; 32BIT: bb.0.entry:
58 ; 32BIT-NEXT: %[[VAL:[0-9]+]]:gprc = LBZ 0, %fixed-stack.0
59 ; 32BIT-NEXT: $r3 = COPY %[[VAL]]
60 ; 32BIT-NEXT: BLR
62 ; 64BIT: fixedStack:
63 ; 64BIT-NEXT: - { id: 0, type: default, offset: 112, size: 8, alignment: 16, stack-id: default,
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/external/arm-trusted-firmware/drivers/renesas/rcar/pfc/D3/
Dpfc_init_d3.c14 #define GPSR0_D15 BIT(15)
15 #define GPSR0_D14 BIT(14)
16 #define GPSR0_D13 BIT(13)
17 #define GPSR0_D12 BIT(12)
18 #define GPSR0_D11 BIT(11)
19 #define GPSR0_D10 BIT(10)
20 #define GPSR0_D9 BIT(9)
21 #define GPSR0_D8 BIT(8)
22 #define GPSR0_D7 BIT(7)
23 #define GPSR0_D6 BIT(6)
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/external/arm-trusted-firmware/plat/mediatek/mt8192/drivers/dcm/
Dmtk_dcm_utils.c11 #define MP_CPUSYS_TOP_ADB_DCM_REG0_MASK (BIT(17))
12 #define MP_CPUSYS_TOP_ADB_DCM_REG1_MASK (BIT(15) | \
13 BIT(16) | \
14 BIT(17) | \
15 BIT(18) | \
16 BIT(21))
17 #define MP_CPUSYS_TOP_ADB_DCM_REG2_MASK (BIT(15) | \
18 BIT(16) | \
19 BIT(17) | \
20 BIT(18))
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/external/arm-trusted-firmware/plat/brcm/board/stingray/driver/
Dplat_emmc.c59 val = (BIT(IOPAD_CTRL6_SDIO0_DATA7_SRC_R) | in emmc_soft_reset()
60 BIT(IOPAD_CTRL6_SDIO0_DATA7_HYS_R) | in emmc_soft_reset()
61 BIT(IOPAD_CTRL6_SDIO0_DATA7_DRIVE_R) | in emmc_soft_reset()
62 BIT(IOPAD_CTRL6_SDIO0_DATA6_SRC_R) | in emmc_soft_reset()
63 BIT(IOPAD_CTRL6_SDIO0_DATA6_HYS_R) | in emmc_soft_reset()
64 BIT(IOPAD_CTRL6_SDIO0_DATA6_DRIVE_R)); in emmc_soft_reset()
68 val = (BIT(IOPAD_CTRL5_SDIO0_DATA3_SRC_R) | in emmc_soft_reset()
69 BIT(IOPAD_CTRL5_SDIO0_DATA3_HYS_R) | in emmc_soft_reset()
70 BIT(IOPAD_CTRL5_SDIO0_DATA3_DRIVE_R) | in emmc_soft_reset()
71 BIT(IOPAD_CTRL5_SDIO0_DATA4_SRC_R) | in emmc_soft_reset()
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/external/arm-trusted-firmware/plat/marvell/armada/a3k/common/
Dplat_pm.c32 #define MVEBU_NB_GPIO1_UART1_SEL BIT(19)
33 #define MVEBU_NB_GPIO1_GPIO_25_26_EN BIT(17)
34 #define MVEBU_NB_GPIO1_GPIO_19_EN BIT(14)
35 #define MVEBU_NB_GPIO1_GPIO_18_EN BIT(13)
77 #define MVEBU_PM_PWR_DN_CNT_SEL BIT(28)
78 #define MVEBU_PM_SB_PWR_DWN BIT(4)
79 #define MVEBU_PM_INTERFACE_IDLE BIT(0)
81 #define MVEBU_PM_L2_FLUSH_EN BIT(22)
83 #define MVEBU_PM_DDR_SR_EN BIT(29)
84 #define MVEBU_PM_DDR_CLK_DIS_EN BIT(28)
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/external/curl/lib/
Durldata.h161 #define BIT(x) bool x macro
164 #define BIT(x) bit x:1 macro
173 BIT(eof_flag);
216 BIT(use);
232 BIT(verifypeer); /* set TRUE if this is desired */
233 BIT(verifyhost); /* set TRUE if CN/SAN must match hostname */
234 BIT(verifystatus); /* set TRUE if certificate status must be checked */
235 BIT(sessionid); /* cache session IDs or not */
256 BIT(certinfo); /* gather lots of certificate info */
257 BIT(falsestart);
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