Searched refs:BRW_OPCODE_ASR (Results 1 – 18 of 18) sorted by relevance
| /external/mesa3d/src/intel/compiler/ |
| D | brw_eu.cpp | 616 { BRW_OPCODE_ASR, 12, "asr", 2, 1, GEN_LT(GEN12) },
617 { BRW_OPCODE_ASR, 108, "asr", 2, 1, GEN_GE(GEN12) },
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| D | brw_vec4_cse.cpp | 60 case BRW_OPCODE_ASR: in is_expression()
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| D | brw_shader.cpp | 957 case BRW_OPCODE_ASR: in can_do_saturate()
1004 case BRW_OPCODE_ASR: in can_do_cmod()
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| D | brw_vec4_copy_propagation.cpp | 195 case BRW_OPCODE_ASR: in try_constant_propagate()
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| D | brw_fs_cse.cpp | 59 case BRW_OPCODE_ASR: in is_expression()
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| D | brw_eu_defines.h | 214 BRW_OPCODE_ASR, enumerator
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| D | brw_fs_copy_propagation.cpp | 757 case BRW_OPCODE_ASR: in try_constant_propagate()
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| D | brw_ir_performance.cpp | 304 case BRW_OPCODE_ASR: in instruction_desc()
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| D | brw_vec4_generator.cpp | 1584 case BRW_OPCODE_ASR: in generate_code()
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| D | brw_fs_generator.cpp | 2077 case BRW_OPCODE_ASR: in generate_code()
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| D | test_fs_cmod_propagation.cpp | 1489 EXPECT_EQ(BRW_OPCODE_ASR, instruction(block0, 0)->opcode); in TEST_F()
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| D | brw_fs.cpp | 6521 case BRW_OPCODE_ASR: in get_lowered_simd_width()
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| /external/igt-gpu-tools/assembler/ |
| D | lex.l | 129 "asr" { yylval.integer = BRW_OPCODE_ASR; return ASR; }
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| D | brw_defines.h | 647 BRW_OPCODE_ASR = 12, enumerator
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| D | brw_disasm.c | 66 [BRW_OPCODE_ASR] = { .name = "asr", .nsrc = 2, .ndst = 1 },
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| D | gram.y | 3060 (instr->header.opcode == BRW_OPCODE_ASR) || in reset_instruction_src_region()
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| /external/mesa3d/src/intel/tools/ |
| D | i965_lex.l | 55 asr { yylval.integer = BRW_OPCODE_ASR; return ASR; }
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| D | i965_gram.y | 219 case BRW_OPCODE_ASR: in i965_asm_binary_instruction()
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