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Searched refs:BRW_OPCODE_SEL (Results 1 – 25 of 30) sorted by relevance

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/external/mesa3d/src/intel/compiler/
Dbrw_fs_lower_regioning.cpp210 case BRW_OPCODE_SEL: in has_invalid_conversion()
238 return inst->opcode == BRW_OPCODE_SEL || in has_inconsistent_cmod()
306 if (inst->opcode != BRW_OPCODE_SEL) { in lower_dst_modifiers()
400 if (inst->predicate && inst->opcode != BRW_OPCODE_SEL) { in lower_dst_region()
Dbrw_vec4_copy_propagation.cpp258 case BRW_OPCODE_SEL: in try_constant_propagate()
409 case BRW_OPCODE_SEL: in try_copy_propagate()
Dtest_fs_cmod_propagation.cpp353 EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); in TEST_F()
396 EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); in TEST_F()
476 EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); in TEST_F()
797 EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); in TEST_F()
1421 EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); in TEST_F()
2201 EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); in TEST_F()
2245 EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); in TEST_F()
2289 EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); in TEST_F()
2380 EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); in TEST_F()
Dtest_fs_copy_propagation.cpp198 EXPECT_EQ(BRW_OPCODE_SEL, sel->opcode); in TEST_F()
Dbrw_vec4_cmod_propagation.cpp147 if ((scan_inst->predicate && scan_inst->opcode != BRW_OPCODE_SEL) || in opt_cmod_propagation_local()
Dbrw_eu.cpp597 { BRW_OPCODE_SEL, 2, "sel", 2, 1, GEN_LT(GEN12) },
598 { BRW_OPCODE_SEL, 98, "sel", 2, 1, GEN_GE(GEN12) },
Dbrw_vec4_live_variables.cpp115 if ((!inst->predicate || inst->opcode == BRW_OPCODE_SEL) && in setup_def_use()
Dbrw_vec4_cse.cpp53 case BRW_OPCODE_SEL: in is_expression()
Dbrw_shader.cpp857 case BRW_OPCODE_SEL: in is_commutative()
979 case BRW_OPCODE_SEL: in can_do_saturate()
Dbrw_vec4_visitor.cpp721 vec4_instruction *inst = emit(BRW_OPCODE_SEL, dst, src0, src1); in emit_minmax()
1440 if (inst->opcode != BRW_OPCODE_SEL) in emit_scratch_write()
1460 if (inst->opcode != BRW_OPCODE_SEL) in emit_scratch_write()
1479 if (inst->opcode != BRW_OPCODE_SEL) in emit_scratch_write()
Dbrw_ir_vec4.h334 return (conditional_mod && (opcode != BRW_OPCODE_SEL && in writes_flag()
Dbrw_fs_cse.cpp52 case BRW_OPCODE_SEL: in is_expression()
Dbrw_fs_copy_propagation.cpp595 case BRW_OPCODE_SEL: in try_copy_propagate()
823 case BRW_OPCODE_SEL: in try_constant_propagate()
Dtest_vec4_cmod_propagation.cpp358 EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); in TEST_F()
443 EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); in TEST_F()
Dbrw_vec4_reg_allocate.cpp324 return (!prev_inst->predicate || prev_inst->opcode == BRW_OPCODE_SEL) && in can_use_scratch_for_source()
Dbrw_vec4.cpp315 (opcode == BRW_OPCODE_SEL && in can_change_types()
1611 (devinfo->gen < 5 || (inst->opcode != BRW_OPCODE_SEL && in dump_instruction()
1870 if (inst->opcode == BRW_OPCODE_SEL && in lower_minmax()
2191 if (inst->opcode == BRW_OPCODE_SEL && type_sz(inst->dst.type) == 8) in get_lowered_simd_width()
Dbrw_eu_defines.h204 BRW_OPCODE_SEL, enumerator
Dbrw_vec4_nir.cpp1397 inst = emit(BRW_OPCODE_SEL, dst, zero, tmp32); in nir_emit_alu()
1553 inst = emit(BRW_OPCODE_SEL, dst, one, brw_imm_d(0)); in nir_emit_alu()
1856 inst = emit(BRW_OPCODE_SEL, dst, op[1], op[2]); in nir_emit_alu()
Dbrw_fs_nir.cpp3937 case nir_op_imin: return BRW_OPCODE_SEL; in brw_op_for_nir_reduction_op()
3938 case nir_op_umin: return BRW_OPCODE_SEL; in brw_op_for_nir_reduction_op()
3939 case nir_op_fmin: return BRW_OPCODE_SEL; in brw_op_for_nir_reduction_op()
3940 case nir_op_imax: return BRW_OPCODE_SEL; in brw_op_for_nir_reduction_op()
3941 case nir_op_umax: return BRW_OPCODE_SEL; in brw_op_for_nir_reduction_op()
3942 case nir_op_fmax: return BRW_OPCODE_SEL; in brw_op_for_nir_reduction_op()
Dbrw_fs.cpp491 (opcode == BRW_OPCODE_SEL && in can_change_types()
735 return ((this->predicate && this->opcode != BRW_OPCODE_SEL) || in is_partial_write()
1116 if ((conditional_mod && (opcode != BRW_OPCODE_SEL && in flags_written()
2767 case BRW_OPCODE_SEL: in opt_algebraic()
4174 if (inst->opcode == BRW_OPCODE_SEL && in lower_minmax()
6514 case BRW_OPCODE_SEL: in get_lowered_simd_width()
7229 (devinfo->gen < 5 || (inst->opcode != BRW_OPCODE_SEL && in dump_instruction()
/external/igt-gpu-tools/assembler/
Dlex.l123 "sel" { yylval.integer = BRW_OPCODE_SEL; return SEL; }
Dbrw_disasm.c60 [BRW_OPCODE_SEL] = { .name = "sel", .nsrc = 2, .ndst = 1 },
1081 (gen < 6 || (inst->header.opcode != BRW_OPCODE_SEL && in brw_disasm()
Dbrw_defines.h638 BRW_OPCODE_SEL = 2, enumerator
Dgen8_disasm.c868 if (gen8_cond_modifier(insn) && opcode != BRW_OPCODE_SEL) { in gen8_disassemble()
/external/mesa3d/src/intel/tools/
Di965_lex.l120 sel { yylval.integer = BRW_OPCODE_SEL; return SEL; }

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