Searched refs:BRW_OPCODE_SHL (Results 1 – 17 of 17) sorted by relevance
| /external/mesa3d/src/intel/compiler/ |
| D | brw_eu.cpp | 611 { BRW_OPCODE_SHL, 9, "shl", 2, 1, GEN_LT(GEN12) },
612 { BRW_OPCODE_SHL, 105, "shl", 2, 1, GEN_GE(GEN12) },
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| D | brw_vec4_cse.cpp | 59 case BRW_OPCODE_SHL: in is_expression()
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| D | brw_shader.cpp | 980 case BRW_OPCODE_SHL: in can_do_saturate()
1032 case BRW_OPCODE_SHL: in can_do_cmod()
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| D | brw_vec4_copy_propagation.cpp | 196 case BRW_OPCODE_SHL: in try_constant_propagate()
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| D | brw_fs_cse.cpp | 58 case BRW_OPCODE_SHL: in is_expression()
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| D | brw_eu_defines.h | 211 BRW_OPCODE_SHL, enumerator
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| D | brw_fs_copy_propagation.cpp | 758 case BRW_OPCODE_SHL: in try_constant_propagate()
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| D | brw_ir_performance.cpp | 302 case BRW_OPCODE_SHL: in instruction_desc()
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| D | brw_vec4_generator.cpp | 1590 case BRW_OPCODE_SHL: in generate_code()
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| D | brw_fs_generator.cpp | 2083 case BRW_OPCODE_SHL: in generate_code()
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| D | brw_fs.cpp | 6520 case BRW_OPCODE_SHL: in get_lowered_simd_width()
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| /external/igt-gpu-tools/assembler/ |
| D | lex.l | 128 "shl" { yylval.integer = BRW_OPCODE_SHL; return SHL; }
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| D | brw_defines.h | 644 BRW_OPCODE_SHL = 9, enumerator
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| D | brw_disasm.c | 65 [BRW_OPCODE_SHL] = { .name = "shl", .nsrc = 2, .ndst = 1 },
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| D | gram.y | 3062 (instr->header.opcode == BRW_OPCODE_SHL)) { in reset_instruction_src_region()
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| /external/mesa3d/src/intel/tools/ |
| D | i965_lex.l | 125 shl { yylval.integer = BRW_OPCODE_SHL; return SHL; }
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| D | i965_gram.y | 231 case BRW_OPCODE_SHL: in i965_asm_binary_instruction()
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