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Searched refs:CACHELINE (Results 1 – 14 of 14) sorted by relevance

/external/igt-gpu-tools/tests/i915/
Dgem_fence_thrash.c47 #define CACHELINE 64 macro
117 igt_memcpy_from_wc(dst, src, CACHELINE); in copy_wc_cacheline()
152 for (i = 0; i < dwords; i += CACHELINE/sizeof(uint32_t)) { in _bo_write_verify()
153 for (int j = 0; j < CACHELINE/sizeof(uint32_t); j++) in _bo_write_verify()
157 for (int j = 0; j < CACHELINE/sizeof(uint32_t); j++) in _bo_write_verify()
162 for (int j = 0; j < CACHELINE/sizeof(uint32_t); j++) in _bo_write_verify()
/external/jemalloc_new/src/
Dsz.c4 JEMALLOC_ALIGNED(CACHELINE)
18 JEMALLOC_ALIGNED(CACHELINE)
26 JEMALLOC_ALIGNED(CACHELINE)
Dckh.c277 usize = sz_sa2u(sizeof(ckhc_t) << lg_curcells, CACHELINE); in ckh_grow()
282 tab = (ckhc_t *)ipallocztm(tsd_tsdn(tsd), usize, CACHELINE, in ckh_grow()
322 usize = sz_sa2u(sizeof(ckhc_t) << lg_curcells, CACHELINE); in ckh_shrink()
326 tab = (ckhc_t *)ipallocztm(tsd_tsdn(tsd), usize, CACHELINE, true, NULL, in ckh_shrink()
398 usize = sz_sa2u(sizeof(ckhc_t) << lg_mincells, CACHELINE); in ckh_new()
403 ckh->tab = (ckhc_t *)ipallocztm(tsd_tsdn(tsd), usize, CACHELINE, true, in ckh_new()
Dlarge.c17 return large_palloc(tsdn, arena, usize, CACHELINE, zero); in large_malloc()
165 CACHELINE, false, NSIZES, &is_zeroed_trail, &commit)) != NULL in large_ralloc_no_move_expand()
168 CACHELINE, false, NSIZES, &is_zeroed_trail, &commit)) != NULL) { in large_ralloc_no_move_expand()
174 extent_past_get(extent), trailsize, 0, CACHELINE, false, in large_ralloc_no_move_expand()
274 if (alignment <= CACHELINE) { in large_ralloc_move_helper()
Dtcache.c409 size = sz_sa2u(size, CACHELINE); in tsd_tcache_data_init()
411 void *avail_array = ipallocztm(tsd_tsdn(tsd), size, CACHELINE, true, in tsd_tcache_data_init()
456 size = sz_sa2u(size, CACHELINE); in tcache_create_explicit()
458 tcache = ipallocztm(tsd_tsdn(tsd), size, CACHELINE, true, NULL, true, in tcache_create_explicit()
580 * (MALLOCX_TCACHE_MAX+1), CACHELINE); in tcaches_create_prep()
690 * sizeof(cache_bin_info_t), CACHELINE); in tcache_boot()
Drtree.c33 sizeof(rtree_node_elm_t), CACHELINE); in rtree_node_alloc_impl()
48 sizeof(rtree_leaf_elm_t), CACHELINE); in rtree_leaf_alloc_impl()
Dbase.c360 size_t base_alignment = CACHELINE; in base_new()
472 CACHELINE, &esn); in base_alloc_extent()
Dbackground_thread.c885 sizeof(background_thread_info_t), CACHELINE); in background_thread_boot1()
Dprof.c2360 CACHELINE); in prof_boot2()
2374 CACHELINE); in prof_boot2()
Darena.c1403 if (likely(alignment <= CACHELINE)) { in arena_palloc()
1780 arena = (arena_t *)base_alloc(tsdn, base, sizeof(arena_t), CACHELINE); in arena_new()
Djemalloc.c85 JEMALLOC_ALIGNED(CACHELINE)
/external/jemalloc_new/include/jemalloc/internal/
Djemalloc_internal_types.h148 #define CACHELINE 64 macro
149 #define CACHELINE_MASK (CACHELINE - 1)
/external/jemalloc_new/test/unit/
Dbase.c135 CACHELINE, in TEST_BEGIN()
136 CACHELINE << 1, in TEST_BEGIN()
/external/lz4/programs/
Dlz4io.c82 #define CACHELINE 64 macro