1 /*
2 * Copyright © 2008-9 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
26 *
27 */
28
29 #include "config.h"
30
31 #include <unistd.h>
32 #include <stdlib.h>
33 #include <stdio.h>
34 #include <string.h>
35 #include <fcntl.h>
36 #include <inttypes.h>
37 #include <errno.h>
38 #include <sys/stat.h>
39 #include <sys/ioctl.h>
40 #include <pthread.h>
41 #include "drm.h"
42
43 #include "igt.h"
44 #include "igt_x86.h"
45
46 #define PAGE_SIZE 4096
47 #define CACHELINE 64
48
49 #define OBJECT_SIZE (128*1024) /* restricted to 1MiB alignment on i915 fences */
50
51 /* Before introduction of the LRU list for fences, allocation of a fence for a page
52 * fault would use the first inactive fence (i.e. in preference one with no outstanding
53 * GPU activity, or it would wait on the first to finish). Given the choice, it would simply
54 * reuse the fence that had just been allocated for the previous page-fault - the worst choice
55 * when copying between two buffers and thus constantly swapping fences.
56 */
57
58 struct test {
59 int fd;
60 int tiling;
61 int num_surfaces;
62 };
63
64 static void *
bo_create(int fd,int tiling)65 bo_create (int fd, int tiling)
66 {
67 uint32_t handle;
68 void *ptr;
69
70 handle = gem_create(fd, OBJECT_SIZE);
71
72 /* dirty cpu caches a bit ... */
73 ptr = gem_mmap__cpu(fd, handle, 0, OBJECT_SIZE,
74 PROT_READ | PROT_WRITE);
75 memset(ptr, 0, OBJECT_SIZE);
76 munmap(ptr, OBJECT_SIZE);
77
78 gem_set_tiling(fd, handle, tiling, 1024);
79
80 ptr = gem_mmap__gtt(fd, handle, OBJECT_SIZE, PROT_READ | PROT_WRITE);
81
82 gem_set_domain(fd, handle, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
83 gem_close(fd, handle);
84
85 return ptr;
86 }
87
88 static void *
bo_copy(void * _arg)89 bo_copy (void *_arg)
90 {
91 struct test *t = (struct test *)_arg;
92 int fd = t->fd;
93 int n;
94 char *a, *b;
95
96 a = bo_create (fd, t->tiling);
97 b = bo_create (fd, t->tiling);
98
99 for (n = 0; n < 1000; n++) {
100 memcpy (a, b, OBJECT_SIZE);
101 sched_yield ();
102 }
103
104 munmap(a, OBJECT_SIZE);
105 munmap(b, OBJECT_SIZE);
106
107 return NULL;
108 }
109
copy_wc_page(void * dst,const void * src)110 static void copy_wc_page(void *dst, const void *src)
111 {
112 igt_memcpy_from_wc(dst, src, PAGE_SIZE);
113 }
114
copy_wc_cacheline(void * dst,const void * src)115 static void copy_wc_cacheline(void *dst, const void *src)
116 {
117 igt_memcpy_from_wc(dst, src, CACHELINE);
118 }
119
120 static void
_bo_write_verify(struct test * t)121 _bo_write_verify(struct test *t)
122 {
123 int fd = t->fd;
124 int i, k;
125 uint32_t **s;
126 unsigned int dwords = OBJECT_SIZE >> 2;
127 const char *tile_str[] = { "none", "x", "y" };
128 uint32_t tmp[PAGE_SIZE/sizeof(uint32_t)];
129
130 igt_assert(t->tiling >= 0 && t->tiling <= I915_TILING_Y);
131 igt_assert_lt(0, t->num_surfaces);
132
133 s = calloc(sizeof(*s), t->num_surfaces);
134 igt_assert(s);
135
136 for (k = 0; k < t->num_surfaces; k++)
137 s[k] = bo_create(fd, t->tiling);
138
139 for (k = 0; k < t->num_surfaces; k++) {
140 uint32_t *a = s[k];
141
142 a[0] = 0xdeadbeef;
143 igt_assert_f(a[0] == 0xdeadbeef,
144 "tiling %s: write failed at start (%x)\n",
145 tile_str[t->tiling], a[0]);
146
147 a[dwords - 1] = 0xc0ffee;
148 igt_assert_f(a[dwords - 1] == 0xc0ffee,
149 "tiling %s: write failed at end (%x)\n",
150 tile_str[t->tiling], a[dwords - 1]);
151
152 for (i = 0; i < dwords; i += CACHELINE/sizeof(uint32_t)) {
153 for (int j = 0; j < CACHELINE/sizeof(uint32_t); j++)
154 a[i + j] = ~(i + j);
155
156 copy_wc_cacheline(tmp, a + i);
157 for (int j = 0; j < CACHELINE/sizeof(uint32_t); j++)
158 igt_assert_f(tmp[j] == ~(i+ j),
159 "tiling %s: write failed at %d (%x)\n",
160 tile_str[t->tiling], i + j, tmp[j]);
161
162 for (int j = 0; j < CACHELINE/sizeof(uint32_t); j++)
163 a[i + j] = i + j;
164 }
165
166 for (i = 0; i < dwords; i += PAGE_SIZE/sizeof(uint32_t)) {
167 copy_wc_page(tmp, a + i);
168 for (int j = 0; j < PAGE_SIZE/sizeof(uint32_t); j++) {
169 igt_assert_f(tmp[j] == i + j,
170 "tiling %s: verify failed at %d (%x)\n",
171 tile_str[t->tiling], i + j, tmp[j]);
172 }
173 }
174 }
175
176 for (k = 0; k < t->num_surfaces; k++)
177 munmap(s[k], OBJECT_SIZE);
178
179 free(s);
180 }
181
182 static void *
bo_write_verify(void * _arg)183 bo_write_verify(void *_arg)
184 {
185 struct test *t = (struct test *)_arg;
186 int i;
187
188 for (i = 0; i < 10; i++)
189 _bo_write_verify(t);
190
191 return 0;
192 }
193
run_test(int threads_per_fence,void * f,int tiling,int surfaces_per_thread)194 static int run_test(int threads_per_fence, void *f, int tiling,
195 int surfaces_per_thread)
196 {
197 struct test t;
198 pthread_t *threads;
199 int n, num_fences, num_threads;
200
201 t.fd = drm_open_driver(DRIVER_INTEL);
202 t.tiling = tiling;
203 t.num_surfaces = surfaces_per_thread;
204
205 num_fences = gem_available_fences(t.fd);
206 igt_assert_lt(0, num_fences);
207
208 num_threads = threads_per_fence * num_fences;
209
210 igt_info("%s: threads %d, fences %d, tiling %d, surfaces per thread %d\n",
211 f == bo_copy ? "copy" : "write-verify", num_threads,
212 num_fences, tiling, surfaces_per_thread);
213
214 if (threads_per_fence) {
215 threads = calloc(sizeof(*threads), num_threads);
216 igt_assert(threads != NULL);
217
218 for (n = 0; n < num_threads; n++)
219 pthread_create (&threads[n], NULL, f, &t);
220
221 for (n = 0; n < num_threads; n++)
222 pthread_join (threads[n], NULL);
223
224 free(threads);
225 } else {
226 void *(*func)(void *) = f;
227 igt_assert(func(&t) == (void *)0);
228 }
229
230 close(t.fd);
231
232 return 0;
233 }
234
235 igt_main
236 {
237 igt_skip_on_simulation();
238
239 igt_subtest("bo-write-verify-none")
240 igt_assert(run_test(0, bo_write_verify, I915_TILING_NONE, 80) == 0);
241
242 igt_subtest("bo-write-verify-x")
243 igt_assert(run_test(0, bo_write_verify, I915_TILING_X, 80) == 0);
244
245 igt_subtest("bo-write-verify-y")
246 igt_assert(run_test(0, bo_write_verify, I915_TILING_Y, 80) == 0);
247
248 igt_subtest("bo-write-verify-threaded-none")
249 igt_assert(run_test(5, bo_write_verify, I915_TILING_NONE, 2) == 0);
250
251 igt_subtest("bo-write-verify-threaded-x") {
252 igt_assert(run_test(2, bo_write_verify, I915_TILING_X, 2) == 0);
253 igt_assert(run_test(5, bo_write_verify, I915_TILING_X, 2) == 0);
254 igt_assert(run_test(10, bo_write_verify, I915_TILING_X, 2) == 0);
255 igt_assert(run_test(20, bo_write_verify, I915_TILING_X, 2) == 0);
256 }
257
258 igt_subtest("bo-write-verify-threaded-y") {
259 igt_assert(run_test(2, bo_write_verify, I915_TILING_Y, 2) == 0);
260 igt_assert(run_test(5, bo_write_verify, I915_TILING_Y, 2) == 0);
261 igt_assert(run_test(10, bo_write_verify, I915_TILING_Y, 2) == 0);
262 igt_assert(run_test(20, bo_write_verify, I915_TILING_Y, 2) == 0);
263 }
264
265 igt_subtest("bo-copy")
266 igt_assert(run_test(1, bo_copy, I915_TILING_X, 1) == 0);
267 }
268