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/external/openssh/regress/
Dsftp-perm.sh22 rm -f ${COPY} ${COPY}.1
23 test -d ${COPY}.dd && { rmdir ${COPY}.dd || fatal "rmdir ${COPY}.dd"; }
86 "put $DATA $COPY" \
88 "cmp $DATA $COPY" \
89 "test ! -f $COPY"
93 "chmod 0700 $COPY" \
94 "touch $COPY; chmod 0400 $COPY" \
95 "test -x $COPY" \
96 "test ! -x $COPY"
100 "rm $COPY" \
[all …]
Dsftp-cmds.sh19 QUOTECOPY=${COPY}".\"blah\""
20 QUOTECOPY_ARG=${COPY}'.\"blah\"'
22 SPACECOPY="${COPY} this has spaces.txt"
23 SPACECOPY_ARG="${COPY}\ this\ has\ spaces.txt"
25 GLOBMETACOPY="${COPY} [metachar].txt"
27 rm -rf ${COPY} ${COPY}.1 ${COPY}.2 ${COPY}.dd ${COPY}.dd2
28 mkdir ${COPY}.dd
68 rm -f ${COPY}
70 echo "get $DATA $COPY" | ${SFTP} -D ${SFTPSERVER} >/dev/null 2>&1 \
72 cmp $DATA ${COPY} || fail "corrupted copy after get"
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dinst-select-freeze.mir16 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
17 ; GFX6: $vgpr0 = COPY [[COPY]]
19 ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
20 ; GFX10: $vgpr0 = COPY [[COPY]]
21 %0:vgpr(s32) = COPY $vgpr0
25 $vgpr0 = COPY %3(s32)
39 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
40 ; GFX6: $agpr0 = COPY [[COPY]]
42 ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
43 ; GFX10: $agpr0 = COPY [[COPY]]
[all …]
Dinst-select-load-constant.mir21 ; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
22 …; GFX6: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]], 0, 0, 0 :: (lo…
23 ; GFX6: $sgpr0 = COPY [[S_LOAD_DWORD_IMM]]
26 ; GFX7: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
27 …; GFX7: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]], 0, 0, 0 :: (lo…
28 ; GFX7: $sgpr0 = COPY [[S_LOAD_DWORD_IMM]]
31 ; GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
32 …; GFX8: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]], 0, 0, 0 :: (lo…
33 ; GFX8: $sgpr0 = COPY [[S_LOAD_DWORD_IMM]]
36 ; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
[all …]
Dlegalize-build-vector.mir10 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
11 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
12 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
14 %0:_(s32) = COPY $vgpr0
15 %1:_(s32) = COPY $vgpr1
25 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
26 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
27 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
28 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[C…
30 %0:_(s32) = COPY $vgpr0
[all …]
Dinst-select-concat-vectors.mir15 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
16 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
17 …; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.…
18 ; GCN: $vgpr0_vgpr1 = COPY [[REG_SEQUENCE]]
19 %0:vgpr(<2 x s16>) = COPY $vgpr0
20 %1:vgpr(<2 x s16>) = COPY $vgpr1
22 $vgpr0_vgpr1 = COPY %2
35 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
36 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
37 …; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.…
[all …]
Dlegalize-insert.mir11 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
12 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
13 ; CHECK: [[INSERT:%[0-9]+]]:_(s64) = G_INSERT [[COPY]], [[COPY1]](s32), 0
14 ; CHECK: $vgpr0_vgpr1 = COPY [[INSERT]](s64)
15 %0:_(s64) = COPY $vgpr0_vgpr1
16 %1:_(s32) = COPY $vgpr2
18 $vgpr0_vgpr1 = COPY %2
27 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
28 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
29 ; CHECK: [[INSERT:%[0-9]+]]:_(s64) = G_INSERT [[COPY]], [[COPY1]](s32), 32
[all …]
Dinst-select-insert-vector-elt.mir15 ; MOVREL: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
16 ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
17 ; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
18 ; MOVREL: $m0 = COPY [[COPY2]]
19 …E_MOVREL_B32_V2_:%[0-9]+]]:sreg_64 = S_INDIRECT_REG_WRITE_MOVREL_B32_V2 [[COPY]], [[COPY1]], 3, im…
22 ; GPRIDX: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
23 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
24 ; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3
25 ; GPRIDX: $m0 = COPY [[COPY2]]
26 …E_MOVREL_B32_V2_:%[0-9]+]]:sreg_64 = S_INDIRECT_REG_WRITE_MOVREL_B32_V2 [[COPY]], [[COPY1]], 3, im…
[all …]
Dinst-select-extract-vector-elt.mir17 ; MOVREL: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
18 ; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
19 ; MOVREL: $m0 = COPY [[COPY1]]
20 …: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
23 ; GPRIDX: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
24 ; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
25 ; GPRIDX: $m0 = COPY [[COPY1]]
26 …: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
28 %0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
29 %1:sgpr(s32) = COPY $sgpr2
[all …]
Dinst-select-shuffle-vector.v2s16.mir17 ; GFX9: $vgpr0 = COPY [[DEF]]
18 %0:vgpr(<2 x s16>) = COPY $vgpr0
19 %1:vgpr(<2 x s16>) = COPY $vgpr1
21 $vgpr0 = COPY %2
37 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
38 ; GFX9: $vgpr0 = COPY [[COPY]]
39 %0:vgpr(<2 x s16>) = COPY $vgpr0
40 %1:vgpr(<2 x s16>) = COPY $vgpr1
42 $vgpr0 = COPY %2
58 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
[all …]
Dregbankselect-freeze.mir14 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
15 ; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
18 ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
19 %0:_(s32) = COPY $vgpr0
23 $vgpr0 = COPY %3(s32)
35 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
36 ; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
39 ; CHECK: $agpr0 = COPY [[ANYEXT]](s32)
40 %0:_(s32) = COPY $vgpr0
44 $agpr0 = COPY %3(s32)
[all …]
Dinst-select-store-flat.mir20 ; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
21 ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
22 …; GFX7: FLAT_STORE_DWORD [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (s…
25 ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
26 ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
27 …; GFX8: FLAT_STORE_DWORD [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (s…
30 ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
31 ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
32 …; GFX9: FLAT_STORE_DWORD [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (s…
35 ; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
[all …]
Dinst-select-fcmp.mir14 ; WAVE64: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
15 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
16 ; WAVE64: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[COPY]](s32), [[COPY1]]
19 ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
20 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
21 ; WAVE32: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[COPY]](s32), [[COPY1]]
23 %0:vgpr(s32) = COPY $vgpr0
24 %1:vgpr(s32) = COPY $vgpr1
38 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
39 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
[all …]
Dinst-select-merge-values.mir16 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
17 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
18 …; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.…
20 %0:vgpr(s32) = COPY $vgpr0
21 %1:vgpr(s32) = COPY $vgpr1
38 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
39 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
40 …; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.…
42 %0:sgpr(s32) = COPY $sgpr0
43 %1:vgpr(s32) = COPY $vgpr0
[all …]
Dinst-select-ashr.mir17 ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
18 ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
19 ; GFX6: [[S_ASHR_I32_:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[COPY]], [[COPY1]], implicit-def $scc
22 ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
23 ; GFX7: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
24 ; GFX7: [[S_ASHR_I32_:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[COPY]], [[COPY1]], implicit-def $scc
27 ; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
28 ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
29 ; GFX8: [[S_ASHR_I32_:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[COPY]], [[COPY1]], implicit-def $scc
32 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
[all …]
Dinst-select-shl.mir17 ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
18 ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
19 ; GFX6: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY]], [[COPY1]], implicit-def $scc
22 ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
23 ; GFX7: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
24 ; GFX7: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY]], [[COPY1]], implicit-def $scc
27 ; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
28 ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
29 ; GFX8: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY]], [[COPY1]], implicit-def $scc
32 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
[all …]
Dinst-select-lshr.mir17 ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
18 ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
19 ; GFX6: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[COPY1]], implicit-def $scc
22 ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
23 ; GFX7: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
24 ; GFX7: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[COPY1]], implicit-def $scc
27 ; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
28 ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
29 ; GFX8: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[COPY1]], implicit-def $scc
32 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
[all …]
Dinst-select-ptr-add.mir17 ; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
18 ; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
19 ; GFX6: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
20 ; GFX6: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub0
21 ; GFX6: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
22 ; GFX6: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub1
28 ; GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
29 ; GFX8: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
30 ; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
31 ; GFX8: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub0
[all …]
Dinst-select-unmerge-values.mir16 ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
17 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
18 ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
20 %0:vgpr(s64) = COPY $vgpr0_vgpr1
37 ; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
38 ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
39 ; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
41 %0:sgpr(s64) = COPY $sgpr0_sgpr1
58 ; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
59 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
[all …]
Dregbankselect-icmp.mir15 ; GFX7: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
16 ; GFX7: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
17 ; GFX7: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
20 ; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
21 ; GFX8: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
22 ; GFX8: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
24 %0:_(s32) = COPY $sgpr0
25 %1:_(s32) = COPY $sgpr1
37 ; GFX7: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
38 ; GFX7: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
[all …]
Dinst-select-store-global.mir22 ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
23 ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
29 …; GFX6: BUFFER_STORE_DWORD_ADDR64 [[COPY1]], [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, imp…
32 ; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
33 ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
39 …; GFX7: BUFFER_STORE_DWORD_ADDR64 [[COPY1]], [[COPY]], [[REG_SEQUENCE1]], 0, 0, 0, 0, 0, 0, 0, imp…
42 ; GFX7-FLAT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
43 ; GFX7-FLAT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
44 …; GFX7-FLAT: FLAT_STORE_DWORD [[COPY]], [[COPY1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr …
47 ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
[all …]
Dlegalize-unmerge-values.mir11 ; CHECK: $vgpr0 = COPY [[UV]](s32)
12 ; CHECK: $vgpr1 = COPY [[UV1]](s32)
15 $vgpr0 = COPY %1(s32)
16 $vgpr1 = COPY %2(s32)
25 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
26 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
27 ; CHECK: $vgpr0 = COPY [[UV]](s32)
28 ; CHECK: $vgpr21 = COPY [[UV1]](s32)
29 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
31 $vgpr0 = COPY %1
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Dselect-fp-casts.mir18 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
19 ; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
20 ; CHECK: $h0 = COPY [[FCVTHSr]]
21 %0(s32) = COPY $s0
23 $h0 = COPY %1(s16)
40 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
41 ; CHECK: [[FCVTHDr:%[0-9]+]]:fpr16 = FCVTHDr [[COPY]]
42 ; CHECK: $h0 = COPY [[FCVTHDr]]
43 %0(s64) = COPY $d0
45 $h0 = COPY %1(s16)
[all …]
Dselect-binop.mir5 # Also check that we constrain the register class of the COPY to GPR32.
20 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
21 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
22 ; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
23 ; CHECK: $w0 = COPY [[ADDWrr]]
24 %0(s32) = COPY $w0
25 %1(s32) = COPY $w1
27 $w0 = COPY %2(s32)
46 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
47 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
[all …]
Dcombine-copy.mir5 # combining COPY instructions.
11 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
12 ; CHECK: $x0 = COPY [[COPY]](s64)
13 %0:_(s64) = COPY $x0
14 %1:_(s64) = COPY %0(s64)
15 $x0 = COPY %1(s64)
22 ; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY $x0
23 ; CHECK: $x0 = COPY [[COPY]](s64)
24 %0:gpr(s64) = COPY $x0
25 %1:_(s64) = COPY %0(s64)
[all …]

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