Searched refs:CPY (Results 1 – 25 of 33) sorted by relevance
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| /external/libkmsxx/kms++/src/ |
| D | helpers.cpp | 6 #define CPY(field) dst.field = src.field macro
17 CPY(clock); in drm_mode_to_video_mode()
19 CPY(hdisplay); in drm_mode_to_video_mode()
20 CPY(hsync_start); in drm_mode_to_video_mode()
21 CPY(hsync_end); in drm_mode_to_video_mode()
22 CPY(htotal); in drm_mode_to_video_mode()
23 CPY(hskew); in drm_mode_to_video_mode()
25 CPY(vdisplay); in drm_mode_to_video_mode()
26 CPY(vsync_start); in drm_mode_to_video_mode()
27 CPY(vsync_end); in drm_mode_to_video_mode()
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| /external/cn-cbor/test/ |
| D | test.c | 48 #define CPY(s, l) memcpy(out, s, l); out += l; in dump() macro
49 #define OUT(s) CPY(s, sizeof(s)-1) in dump()
72 CPY(cb->v.str, cb->length); /* should escape stuff */ in dump()
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| /external/libxml2/os400/ |
| D | make-src.sh | 288 then CMD="CPY OBJ('${SCRIPTDIR}/xmllint.cmd')"
343 then CMD="CPY OBJ('${SCRIPTDIR}/xmlcatalog.cmd')"
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedM1.td | 321 def : InstRW<[M1WriteNALU1], (instregex "^CPY")>;
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| D | AArch64SchedCyclone.td | 341 // CPY D,V[x] is a WriteV
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| D | AArch64SchedA57.td | 504 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^CPY")>;
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| D | AArch64InstrInfo.td | 3754 // AdvSIMD scalar CPY instruction
3757 defm CPY : SIMDScalarCPY<"cpy">;
4077 // subregister extractions, or a MOV (aka CPY here, alias for DUP) if
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| /external/capstone/arch/M680X/ |
| D | insn_props.inc | 122 { NOG, rrrr, M680X_REG_Y, NOR, true, false }, // CPY
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 343 // CPY D,V[x] is a WriteV
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| D | AArch64SchedExynosM3.td | 669 def : InstRW<[M3WriteNSHF1], (instregex "^CPY")>;
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| D | AArch64SchedA57.td | 508 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^CPY")>;
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| D | AArch64SchedExynosM4.td | 810 def : InstRW<[M4WriteNSHF1], (instregex "^CPY")>;
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| D | AArch64SchedExynosM5.td | 848 def : InstRW<[M5WriteNSHF2], (instregex "^CPY")>;
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| D | AArch64SchedFalkorDetails.td | 911 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^CPY(i8|i16|i32|i64)$")>;
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| D | AArch64SchedThunderX3T110.td | 1605 def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^CPY")>;
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| D | AArch64SchedThunderX2T99.td | 1495 def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^CPY")>;
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| D | AArch64InstrInfo.td | 4899 // AdvSIMD scalar CPY instruction
4902 defm CPY : SIMDScalarCPY<"cpy">;
5286 // subregister extractions, or a MOV (aka CPY here, alias for DUP) if
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 342 // CPY D,V[x] is a WriteV
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| D | AArch64SchedExynosM3.td | 668 def : InstRW<[M3WriteNSHF1], (instregex "^CPY")>;
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| D | AArch64SchedA57.td | 507 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^CPY")>;
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| D | AArch64SchedExynosM5.td | 847 def : InstRW<[M5WriteNSHF2], (instregex "^CPY")>;
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| D | AArch64SchedExynosM4.td | 809 def : InstRW<[M4WriteNSHF1], (instregex "^CPY")>;
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| D | AArch64SchedFalkorDetails.td | 911 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^CPY(i8|i16|i32|i64)$")>;
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| D | AArch64SchedThunderX2T99.td | 1495 def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^CPY")>;
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| D | AArch64InstrInfo.td | 4716 // AdvSIMD scalar CPY instruction
4719 defm CPY : SIMDScalarCPY<"cpy">;
5052 // subregister extractions, or a MOV (aka CPY here, alias for DUP) if
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