1//=- AArch64SchedA57.td - ARM Cortex-A57 Scheduling Defs -----*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for ARM Cortex-A57 to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// The Cortex-A57 is a traditional superscalar microprocessor with a 16// conservative 3-wide in-order stage for decode and dispatch. Combined with the 17// much wider out-of-order issue stage, this produced a need to carefully 18// schedule micro-ops so that all three decoded each cycle are successfully 19// issued as the reservation station(s) simply don't stay occupied for long. 20// Therefore, IssueWidth is set to the narrower of the two at three, while still 21// modeling the machine as out-of-order. 22 23def CortexA57Model : SchedMachineModel { 24 let IssueWidth = 3; // 3-way decode and dispatch 25 let MicroOpBufferSize = 128; // 128 micro-op re-order buffer 26 let LoadLatency = 4; // Optimistic load latency 27 let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch 28 29 // Enable partial & runtime unrolling. The magic number is chosen based on 30 // experiments and benchmarking data. 31 let LoopMicroOpBufferSize = 16; 32 let CompleteModel = 1; 33 34 list<Predicate> UnsupportedFeatures = SVEUnsupported.F; 35} 36 37//===----------------------------------------------------------------------===// 38// Define each kind of processor resource and number available on Cortex-A57. 39// Cortex A-57 has 8 pipelines that each has its own 8-entry queue where 40// micro-ops wait for their operands and then issue out-of-order. 41 42def A57UnitB : ProcResource<1>; // Type B micro-ops 43def A57UnitI : ProcResource<2>; // Type I micro-ops 44def A57UnitM : ProcResource<1>; // Type M micro-ops 45def A57UnitL : ProcResource<1>; // Type L micro-ops 46def A57UnitS : ProcResource<1>; // Type S micro-ops 47def A57UnitX : ProcResource<1>; // Type X micro-ops 48def A57UnitW : ProcResource<1>; // Type W micro-ops 49let SchedModel = CortexA57Model in { 50 def A57UnitV : ProcResGroup<[A57UnitX, A57UnitW]>; // Type V micro-ops 51} 52 53let SchedModel = CortexA57Model in { 54 55//===----------------------------------------------------------------------===// 56// Define customized scheduler read/write types specific to the Cortex-A57. 57 58include "AArch64SchedA57WriteRes.td" 59 60//===----------------------------------------------------------------------===// 61// Map the target-defined scheduler read/write resources and latency for 62// Cortex-A57. The Cortex-A57 types are directly associated with resources, so 63// defining the aliases precludes the need for mapping them using WriteRes. The 64// aliases are sufficient for creating a coarse, working model. As the model 65// evolves, InstRWs will be used to override some of these SchedAliases. 66// 67// WARNING: Using SchedAliases is convenient and works well for latency and 68// resource lookup for instructions. However, this creates an entry in 69// AArch64WriteLatencyTable with a WriteResourceID of 0, breaking 70// any SchedReadAdvance since the lookup will fail. 71 72def : SchedAlias<WriteImm, A57Write_1cyc_1I>; 73def : SchedAlias<WriteI, A57Write_1cyc_1I>; 74def : SchedAlias<WriteISReg, A57Write_2cyc_1M>; 75def : SchedAlias<WriteIEReg, A57Write_2cyc_1M>; 76def : SchedAlias<WriteExtr, A57Write_1cyc_1I>; 77def : SchedAlias<WriteIS, A57Write_1cyc_1I>; 78def : SchedAlias<WriteID32, A57Write_19cyc_1M>; 79def : SchedAlias<WriteID64, A57Write_35cyc_1M>; 80def : WriteRes<WriteIM32, [A57UnitM]> { let Latency = 3; } 81def : WriteRes<WriteIM64, [A57UnitM]> { let Latency = 5; } 82def : SchedAlias<WriteBr, A57Write_1cyc_1B>; 83def : SchedAlias<WriteBrReg, A57Write_1cyc_1B>; 84def : SchedAlias<WriteLD, A57Write_4cyc_1L>; 85def : SchedAlias<WriteST, A57Write_1cyc_1S>; 86def : SchedAlias<WriteSTP, A57Write_1cyc_1S>; 87def : SchedAlias<WriteAdr, A57Write_1cyc_1I>; 88def : SchedAlias<WriteLDIdx, A57Write_4cyc_1I_1L>; 89def : SchedAlias<WriteSTIdx, A57Write_1cyc_1I_1S>; 90def : SchedAlias<WriteF, A57Write_3cyc_1V>; 91def : SchedAlias<WriteFCmp, A57Write_3cyc_1V>; 92def : SchedAlias<WriteFCvt, A57Write_5cyc_1V>; 93def : SchedAlias<WriteFCopy, A57Write_5cyc_1L>; 94def : SchedAlias<WriteFImm, A57Write_3cyc_1V>; 95def : SchedAlias<WriteFMul, A57Write_5cyc_1V>; 96def : SchedAlias<WriteFDiv, A57Write_17cyc_1W>; 97def : SchedAlias<WriteV, A57Write_3cyc_1V>; 98def : SchedAlias<WriteVLD, A57Write_5cyc_1L>; 99def : SchedAlias<WriteVST, A57Write_1cyc_1S>; 100 101def : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 102 103def : WriteRes<WriteSys, []> { let Latency = 1; } 104def : WriteRes<WriteBarrier, []> { let Latency = 1; } 105def : WriteRes<WriteHint, []> { let Latency = 1; } 106 107def : WriteRes<WriteLDHi, []> { let Latency = 4; } 108 109// Forwarding logic is only modeled for multiply and accumulate 110def : ReadAdvance<ReadI, 0>; 111def : ReadAdvance<ReadISReg, 0>; 112def : ReadAdvance<ReadIEReg, 0>; 113def : ReadAdvance<ReadIM, 0>; 114def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>; 115def : ReadAdvance<ReadID, 0>; 116def : ReadAdvance<ReadExtrHi, 0>; 117def : ReadAdvance<ReadAdrBase, 0>; 118def : ReadAdvance<ReadVLD, 0>; 119 120 121//===----------------------------------------------------------------------===// 122// Specialize the coarse model by associating instruction groups with the 123// subtarget-defined types. As the modeled is refined, this will override most 124// of the above ShchedAlias mappings. 125 126// Miscellaneous 127// ----------------------------------------------------------------------------- 128 129def : InstRW<[WriteI], (instrs COPY)>; 130 131 132// Branch Instructions 133// ----------------------------------------------------------------------------- 134 135def : InstRW<[A57Write_1cyc_1B_1I], (instrs BL)>; 136def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>; 137 138 139// Shifted Register with Shift == 0 140// ---------------------------------------------------------------------------- 141 142def A57WriteISReg : SchedWriteVariant<[ 143 SchedVar<RegShiftedPred, [WriteISReg]>, 144 SchedVar<NoSchedPred, [WriteI]>]>; 145def : InstRW<[A57WriteISReg], (instregex ".*rs$")>; 146 147 148// Divide and Multiply Instructions 149// ----------------------------------------------------------------------------- 150 151// Multiply high 152def : InstRW<[A57Write_6cyc_1M], (instrs SMULHrr, UMULHrr)>; 153 154 155// Miscellaneous Data-Processing Instructions 156// ----------------------------------------------------------------------------- 157 158def : InstRW<[A57Write_1cyc_1I], (instrs EXTRWrri)>; 159def : InstRW<[A57Write_3cyc_1I_1M], (instrs EXTRXrri)>; 160def : InstRW<[A57Write_2cyc_1M], (instregex "BFM")>; 161 162 163// Cryptography Extensions 164// ----------------------------------------------------------------------------- 165 166def A57ReadAES : SchedReadAdvance<3, [A57Write_3cyc_1W]>; 167def : InstRW<[A57Write_3cyc_1W], (instregex "^AES[DE]")>; 168def : InstRW<[A57Write_3cyc_1W, A57ReadAES], (instregex "^AESI?MC")>; 169def : InstRW<[A57Write_6cyc_2V], (instregex "^SHA1SU0")>; 170def : InstRW<[A57Write_3cyc_1W], (instregex "^SHA1(H|SU1)")>; 171def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA1[CMP]")>; 172def : InstRW<[A57Write_3cyc_1W], (instregex "^SHA256SU0")>; 173def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA256(H|H2|SU1)")>; 174def : InstRW<[A57Write_3cyc_1W], (instregex "^CRC32")>; 175 176 177// Vector Load 178// ----------------------------------------------------------------------------- 179 180def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1i(8|16|32)$")>; 181def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1i(8|16|32)_POST$")>; 182def : InstRW<[A57Write_5cyc_1L], (instregex "LD1i(64)$")>; 183def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1i(64)_POST$")>; 184 185def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1Rv(8b|4h|2s)$")>; 186def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(8b|4h|2s)_POST$")>; 187def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Rv(1d)$")>; 188def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Rv(1d)_POST$")>; 189def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)$")>; 190def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>; 191 192def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Onev(8b|4h|2s|1d)$")>; 193def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>; 194def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Onev(16b|8h|4s|2d)$")>; 195def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>; 196def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Twov(8b|4h|2s|1d)$")>; 197def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>; 198def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Twov(16b|8h|4s|2d)$")>; 199def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>; 200def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Threev(8b|4h|2s|1d)$")>; 201def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>; 202def : InstRW<[A57Write_7cyc_3L], (instregex "LD1Threev(16b|8h|4s|2d)$")>; 203def : InstRW<[A57Write_7cyc_3L, WriteAdr], (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>; 204def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Fourv(8b|4h|2s|1d)$")>; 205def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>; 206def : InstRW<[A57Write_8cyc_4L], (instregex "LD1Fourv(16b|8h|4s|2d)$")>; 207def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>; 208 209def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD2i(8|16)$")>; 210def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2i(8|16)_POST$")>; 211def : InstRW<[A57Write_6cyc_2L], (instregex "LD2i(32)$")>; 212def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD2i(32)_POST$")>; 213def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2i(64)$")>; 214def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2i(64)_POST$")>; 215 216def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2Rv(8b|4h|2s)$")>; 217def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2Rv(8b|4h|2s)_POST$")>; 218def : InstRW<[A57Write_5cyc_1L], (instregex "LD2Rv(1d)$")>; 219def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD2Rv(1d)_POST$")>; 220def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)$")>; 221def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>; 222 223def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2Twov(8b|4h|2s)$")>; 224def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2Twov(8b|4h|2s)_POST$")>; 225def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD2Twov(16b|8h|4s)$")>; 226def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD2Twov(16b|8h|4s)_POST$")>; 227def : InstRW<[A57Write_6cyc_2L], (instregex "LD2Twov(2d)$")>; 228def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD2Twov(2d)_POST$")>; 229 230def : InstRW<[A57Write_9cyc_1L_3V], (instregex "LD3i(8|16)$")>; 231def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr], (instregex "LD3i(8|16)_POST$")>; 232def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD3i(32)$")>; 233def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD3i(32)_POST$")>; 234def : InstRW<[A57Write_6cyc_2L], (instregex "LD3i(64)$")>; 235def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD3i(64)_POST$")>; 236 237def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD3Rv(8b|4h|2s)$")>; 238def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD3Rv(8b|4h|2s)_POST$")>; 239def : InstRW<[A57Write_6cyc_2L], (instregex "LD3Rv(1d)$")>; 240def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD3Rv(1d)_POST$")>; 241def : InstRW<[A57Write_9cyc_1L_3V], (instregex "LD3Rv(16b|8h|4s)$")>; 242def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr], (instregex "LD3Rv(16b|8h|4s)_POST$")>; 243def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD3Rv(2d)$")>; 244def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD3Rv(2d)_POST$")>; 245 246def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD3Threev(8b|4h|2s)$")>; 247def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD3Threev(8b|4h|2s)_POST$")>; 248def : InstRW<[A57Write_10cyc_3L_4V], (instregex "LD3Threev(16b|8h|4s)$")>; 249def : InstRW<[A57Write_10cyc_3L_4V, WriteAdr], (instregex "LD3Threev(16b|8h|4s)_POST$")>; 250def : InstRW<[A57Write_8cyc_4L], (instregex "LD3Threev(2d)$")>; 251def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD3Threev(2d)_POST$")>; 252 253def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4i(8|16)$")>; 254def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(8|16)_POST$")>; 255def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD4i(32)$")>; 256def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD4i(32)_POST$")>; 257def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4i(64)$")>; 258def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(64)_POST$")>; 259 260def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD4Rv(8b|4h|2s)$")>; 261def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD4Rv(8b|4h|2s)_POST$")>; 262def : InstRW<[A57Write_6cyc_2L], (instregex "LD4Rv(1d)$")>; 263def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD4Rv(1d)_POST$")>; 264def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4Rv(16b|8h|4s)$")>; 265def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4Rv(16b|8h|4s)_POST$")>; 266def : InstRW<[A57Write_9cyc_2L_4V], (instregex "LD4Rv(2d)$")>; 267def : InstRW<[A57Write_9cyc_2L_4V, WriteAdr], (instregex "LD4Rv(2d)_POST$")>; 268 269def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD4Fourv(8b|4h|2s)$")>; 270def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD4Fourv(8b|4h|2s)_POST$")>; 271def : InstRW<[A57Write_11cyc_4L_4V], (instregex "LD4Fourv(16b|8h|4s)$")>; 272def : InstRW<[A57Write_11cyc_4L_4V, WriteAdr], (instregex "LD4Fourv(16b|8h|4s)_POST$")>; 273def : InstRW<[A57Write_8cyc_4L], (instregex "LD4Fourv(2d)$")>; 274def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD4Fourv(2d)_POST$")>; 275 276// Vector Store 277// ----------------------------------------------------------------------------- 278 279def : InstRW<[A57Write_1cyc_1S], (instregex "ST1i(8|16|32)$")>; 280def : InstRW<[A57Write_1cyc_1S, WriteAdr], (instregex "ST1i(8|16|32)_POST$")>; 281def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST1i(64)$")>; 282def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST1i(64)_POST$")>; 283 284def : InstRW<[A57Write_1cyc_1S], (instregex "ST1Onev(8b|4h|2s|1d)$")>; 285def : InstRW<[A57Write_1cyc_1S, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>; 286def : InstRW<[A57Write_2cyc_2S], (instregex "ST1Onev(16b|8h|4s|2d)$")>; 287def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>; 288def : InstRW<[A57Write_2cyc_2S], (instregex "ST1Twov(8b|4h|2s|1d)$")>; 289def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>; 290def : InstRW<[A57Write_4cyc_4S], (instregex "ST1Twov(16b|8h|4s|2d)$")>; 291def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>; 292def : InstRW<[A57Write_3cyc_3S], (instregex "ST1Threev(8b|4h|2s|1d)$")>; 293def : InstRW<[A57Write_3cyc_3S, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>; 294def : InstRW<[A57Write_6cyc_6S], (instregex "ST1Threev(16b|8h|4s|2d)$")>; 295def : InstRW<[A57Write_6cyc_6S, WriteAdr], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>; 296def : InstRW<[A57Write_4cyc_4S], (instregex "ST1Fourv(8b|4h|2s|1d)$")>; 297def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>; 298def : InstRW<[A57Write_8cyc_8S], (instregex "ST1Fourv(16b|8h|4s|2d)$")>; 299def : InstRW<[A57Write_8cyc_8S, WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>; 300 301def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST2i(8|16|32)$")>; 302def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST2i(8|16|32)_POST$")>; 303def : InstRW<[A57Write_2cyc_2S], (instregex "ST2i(64)$")>; 304def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST2i(64)_POST$")>; 305 306def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST2Twov(8b|4h|2s)$")>; 307def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>; 308def : InstRW<[A57Write_4cyc_4S_2V], (instregex "ST2Twov(16b|8h|4s)$")>; 309def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr], (instregex "ST2Twov(16b|8h|4s)_POST$")>; 310def : InstRW<[A57Write_4cyc_4S], (instregex "ST2Twov(2d)$")>; 311def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST2Twov(2d)_POST$")>; 312 313def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST3i(8|16)$")>; 314def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST3i(8|16)_POST$")>; 315def : InstRW<[A57Write_3cyc_3S], (instregex "ST3i(32)$")>; 316def : InstRW<[A57Write_3cyc_3S, WriteAdr], (instregex "ST3i(32)_POST$")>; 317def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST3i(64)$")>; 318def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST3i(64)_POST$")>; 319 320def : InstRW<[A57Write_3cyc_3S_2V], (instregex "ST3Threev(8b|4h|2s)$")>; 321def : InstRW<[A57Write_3cyc_3S_2V, WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST$")>; 322def : InstRW<[A57Write_6cyc_6S_4V], (instregex "ST3Threev(16b|8h|4s)$")>; 323def : InstRW<[A57Write_6cyc_6S_4V, WriteAdr], (instregex "ST3Threev(16b|8h|4s)_POST$")>; 324def : InstRW<[A57Write_6cyc_6S], (instregex "ST3Threev(2d)$")>; 325def : InstRW<[A57Write_6cyc_6S, WriteAdr], (instregex "ST3Threev(2d)_POST$")>; 326 327def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST4i(8|16)$")>; 328def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST4i(8|16)_POST$")>; 329def : InstRW<[A57Write_4cyc_4S], (instregex "ST4i(32)$")>; 330def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST4i(32)_POST$")>; 331def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST4i(64)$")>; 332def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST4i(64)_POST$")>; 333 334def : InstRW<[A57Write_4cyc_4S_2V], (instregex "ST4Fourv(8b|4h|2s)$")>; 335def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST$")>; 336def : InstRW<[A57Write_8cyc_8S_4V], (instregex "ST4Fourv(16b|8h|4s)$")>; 337def : InstRW<[A57Write_8cyc_8S_4V, WriteAdr], (instregex "ST4Fourv(16b|8h|4s)_POST$")>; 338def : InstRW<[A57Write_8cyc_8S], (instregex "ST4Fourv(2d)$")>; 339def : InstRW<[A57Write_8cyc_8S, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>; 340 341// Vector - Integer 342// ----------------------------------------------------------------------------- 343 344// Reference for forms in this group 345// D form - v8i8, v4i16, v2i32 346// Q form - v16i8, v8i16, v4i32 347// D form - v1i8, v1i16, v1i32, v1i64 348// Q form - v16i8, v8i16, v4i32, v2i64 349// D form - v8i8_v8i16, v4i16_v4i32, v2i32_v2i64 350// Q form - v16i8_v8i16, v8i16_v4i32, v4i32_v2i64 351 352// ASIMD absolute diff accum, D-form 353def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]ABA(v8i8|v4i16|v2i32)$")>; 354// ASIMD absolute diff accum, Q-form 355def : InstRW<[A57Write_5cyc_2X], (instregex "^[SU]ABA(v16i8|v8i16|v4i32)$")>; 356// ASIMD absolute diff accum long 357def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]ABAL")>; 358 359// ASIMD arith, reduce, 4H/4S 360def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>; 361// ASIMD arith, reduce, 8B/8H 362def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>; 363// ASIMD arith, reduce, 16B 364def : InstRW<[A57Write_8cyc_2X], (instregex "^[SU]?ADDL?Vv16i8v$")>; 365 366// ASIMD max/min, reduce, 4H/4S 367def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU](MIN|MAX)V(v4i16|v4i32)v$")>; 368// ASIMD max/min, reduce, 8B/8H 369def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>; 370// ASIMD max/min, reduce, 16B 371def : InstRW<[A57Write_8cyc_2X], (instregex "^[SU](MIN|MAX)Vv16i8v$")>; 372 373// ASIMD multiply, D-form 374def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)(_indexed)?$")>; 375// ASIMD multiply, Q-form 376def : InstRW<[A57Write_6cyc_2W], (instregex "^(P?MUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?$")>; 377 378// ASIMD multiply accumulate, D-form 379def : InstRW<[A57Write_5cyc_1W], (instregex "^ML[AS](v8i8|v4i16|v2i32)(_indexed)?$")>; 380// ASIMD multiply accumulate, Q-form 381def : InstRW<[A57Write_6cyc_2W], (instregex "^ML[AS](v16i8|v8i16|v4i32)(_indexed)?$")>; 382 383// ASIMD multiply accumulate long 384// ASIMD multiply accumulate saturating long 385def A57WriteIVMA : SchedWriteRes<[A57UnitW]> { let Latency = 5; } 386def A57ReadIVMA4 : SchedReadAdvance<4, [A57WriteIVMA]>; 387def : InstRW<[A57WriteIVMA, A57ReadIVMA4], (instregex "^(S|U|SQD)ML[AS]L")>; 388 389// ASIMD multiply long 390def : InstRW<[A57Write_5cyc_1W], (instregex "^(S|U|SQD)MULL")>; 391def : InstRW<[A57Write_5cyc_1W], (instregex "^PMULL(v8i8|v16i8)")>; 392def : InstRW<[A57Write_3cyc_1W], (instregex "^PMULL(v1i64|v2i64)")>; 393 394// ASIMD pairwise add and accumulate 395// ASIMD shift accumulate 396def A57WriteIVA : SchedWriteRes<[A57UnitX]> { let Latency = 4; } 397def A57ReadIVA3 : SchedReadAdvance<3, [A57WriteIVA]>; 398def : InstRW<[A57WriteIVA, A57ReadIVA3], (instregex "^[SU]ADALP")>; 399def : InstRW<[A57WriteIVA, A57ReadIVA3], (instregex "^(S|SR|U|UR)SRA")>; 400 401// ASIMD shift by immed, complex 402def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?(Q|R){1,2}SHR")>; 403def : InstRW<[A57Write_4cyc_1X], (instregex "^SQSHLU")>; 404 405 406// ASIMD shift by register, basic, Q-form 407def : InstRW<[A57Write_4cyc_2X], (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>; 408 409// ASIMD shift by register, complex, D-form 410def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>; 411 412// ASIMD shift by register, complex, Q-form 413def : InstRW<[A57Write_5cyc_2X], (instregex "^[SU][QR]{1,2}SHL(v16i8|v8i16|v4i32|v2i64)")>; 414 415 416// Vector - Floating Point 417// ----------------------------------------------------------------------------- 418 419// Reference for forms in this group 420// D form - v2f32 421// Q form - v4f32, v2f64 422// D form - 32, 64 423// D form - v1i32, v1i64 424// D form - v2i32 425// Q form - v4i32, v2i64 426 427// ASIMD FP arith, normal, D-form 428def : InstRW<[A57Write_5cyc_1V], (instregex "^(FABD|FADD|FSUB)(v2f32|32|64|v2i32p)")>; 429// ASIMD FP arith, normal, Q-form 430def : InstRW<[A57Write_5cyc_2V], (instregex "^(FABD|FADD|FSUB)(v4f32|v2f64|v2i64p)")>; 431 432// ASIMD FP arith, pairwise, D-form 433def : InstRW<[A57Write_5cyc_1V], (instregex "^FADDP(v2f32|32|64|v2i32)")>; 434// ASIMD FP arith, pairwise, Q-form 435def : InstRW<[A57Write_9cyc_3V], (instregex "^FADDP(v4f32|v2f64|v2i64)")>; 436 437// ASIMD FP compare, D-form 438def : InstRW<[A57Write_5cyc_1V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v2f32|32|64|v1i32|v2i32|v1i64)")>; 439// ASIMD FP compare, Q-form 440def : InstRW<[A57Write_5cyc_2V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v4f32|v2f64|v4i32|v2i64)")>; 441 442// ASIMD FP convert, long and narrow 443def : InstRW<[A57Write_8cyc_3V], (instregex "^FCVT(L|N|XN)v")>; 444// ASIMD FP convert, other, D-form 445def : InstRW<[A57Write_5cyc_1V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64)")>; 446// ASIMD FP convert, other, Q-form 447def : InstRW<[A57Write_5cyc_2V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v4f32|v2f64|v4i32|v2i64)")>; 448 449// ASIMD FP divide, D-form, F32 450def : InstRW<[A57Write_17cyc_1W], (instregex "FDIVv2f32")>; 451// ASIMD FP divide, Q-form, F32 452def : InstRW<[A57Write_34cyc_2W], (instregex "FDIVv4f32")>; 453// ASIMD FP divide, Q-form, F64 454def : InstRW<[A57Write_64cyc_2W], (instregex "FDIVv2f64")>; 455 456// Note: These were simply duplicated from ASIMD FDIV because of missing documentation 457// ASIMD FP square root, D-form, F32 458def : InstRW<[A57Write_17cyc_1W], (instregex "FSQRTv2f32")>; 459// ASIMD FP square root, Q-form, F32 460def : InstRW<[A57Write_34cyc_2W], (instregex "FSQRTv4f32")>; 461// ASIMD FP square root, Q-form, F64 462def : InstRW<[A57Write_64cyc_2W], (instregex "FSQRTv2f64")>; 463 464// ASIMD FP max/min, normal, D-form 465def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?(v2f32)")>; 466// ASIMD FP max/min, normal, Q-form 467def : InstRW<[A57Write_5cyc_2V], (instregex "^(FMAX|FMIN)(NM)?(v4f32|v2f64)")>; 468// ASIMD FP max/min, pairwise, D-form 469def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?P(v2f32|v2i32)")>; 470// ASIMD FP max/min, pairwise, Q-form 471def : InstRW<[A57Write_9cyc_3V], (instregex "^(FMAX|FMIN)(NM)?P(v4f32|v2f64|v2i64)")>; 472// ASIMD FP max/min, reduce 473def : InstRW<[A57Write_10cyc_3V], (instregex "^(FMAX|FMIN)(NM)?Vv")>; 474 475// ASIMD FP multiply, D-form, FZ 476def : InstRW<[A57Write_5cyc_1V], (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>; 477// ASIMD FP multiply, Q-form, FZ 478def : InstRW<[A57Write_5cyc_2V], (instregex "^FMULX?(v4f32|v2f64|v4i32|v2i64)")>; 479 480// ASIMD FP multiply accumulate, D-form, FZ 481// ASIMD FP multiply accumulate, Q-form, FZ 482def A57WriteFPVMAD : SchedWriteRes<[A57UnitV]> { let Latency = 9; } 483def A57WriteFPVMAQ : SchedWriteRes<[A57UnitV, A57UnitV]> { let Latency = 10; } 484def A57ReadFPVMA5 : SchedReadAdvance<5, [A57WriteFPVMAD, A57WriteFPVMAQ]>; 485def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>; 486def : InstRW<[A57WriteFPVMAQ, A57ReadFPVMA5], (instregex "^FML[AS](v4f32|v2f64|v4i32|v2i64)")>; 487 488// ASIMD FP round, D-form 489def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT[AIMNPXZ](v2f32)")>; 490// ASIMD FP round, Q-form 491def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>; 492 493 494// Vector - Miscellaneous 495// ----------------------------------------------------------------------------- 496 497// Reference for forms in this group 498// D form - v8i8, v4i16, v2i32 499// Q form - v16i8, v8i16, v4i32 500// D form - v1i8, v1i16, v1i32, v1i64 501// Q form - v16i8, v8i16, v4i32, v2i64 502 503// ASIMD bitwise insert, Q-form 504def : InstRW<[A57Write_3cyc_2V], (instregex "^(BIF|BIT|BSL)v16i8")>; 505 506// ASIMD duplicate, gen reg, D-form and Q-form 507def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^CPY")>; 508def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^DUPv.+gpr")>; 509 510// ASIMD move, saturating 511def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]QXTU?N")>; 512 513// ASIMD reciprocal estimate, D-form 514def : InstRW<[A57Write_5cyc_1V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f32|v1i32|v2i32|v1i64)")>; 515// ASIMD reciprocal estimate, Q-form 516def : InstRW<[A57Write_5cyc_2V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f64|v4f32|v4i32)")>; 517 518// ASIMD reciprocal step, D-form, FZ 519def : InstRW<[A57Write_9cyc_1V], (instregex "^F(RECP|RSQRT)S(v2f32|v1i32|v2i32|v1i64|32|64)")>; 520// ASIMD reciprocal step, Q-form, FZ 521def : InstRW<[A57Write_9cyc_2V], (instregex "^F(RECP|RSQRT)S(v2f64|v4f32|v4i32)")>; 522 523// ASIMD table lookup, D-form 524def : InstRW<[A57Write_3cyc_1V], (instregex "^TB[LX]v8i8One")>; 525def : InstRW<[A57Write_6cyc_2V], (instregex "^TB[LX]v8i8Two")>; 526def : InstRW<[A57Write_9cyc_3V], (instregex "^TB[LX]v8i8Three")>; 527def : InstRW<[A57Write_12cyc_4V], (instregex "^TB[LX]v8i8Four")>; 528// ASIMD table lookup, Q-form 529def : InstRW<[A57Write_6cyc_3V], (instregex "^TB[LX]v16i8One")>; 530def : InstRW<[A57Write_9cyc_5V], (instregex "^TB[LX]v16i8Two")>; 531def : InstRW<[A57Write_12cyc_7V], (instregex "^TB[LX]v16i8Three")>; 532def : InstRW<[A57Write_15cyc_9V], (instregex "^TB[LX]v16i8Four")>; 533 534// ASIMD transfer, element to gen reg 535def : InstRW<[A57Write_6cyc_1I_1L], (instregex "^[SU]MOVv")>; 536 537// ASIMD transfer, gen reg to element 538def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^INSv")>; 539 540// ASIMD unzip/zip, Q-form 541def : InstRW<[A57Write_6cyc_3V], (instregex "^(UZP|ZIP)(1|2)(v16i8|v8i16|v4i32|v2i64)")>; 542 543 544// Remainder 545// ----------------------------------------------------------------------------- 546 547def : InstRW<[A57Write_5cyc_1V], (instregex "^F(ADD|SUB)[DS]rr")>; 548 549def A57WriteFPMA : SchedWriteRes<[A57UnitV]> { let Latency = 9; } 550def A57ReadFPMA5 : SchedReadAdvance<5, [A57WriteFPMA]>; 551def A57ReadFPM : SchedReadAdvance<0>; 552def : InstRW<[A57WriteFPMA, A57ReadFPM, A57ReadFPM, A57ReadFPMA5], (instregex "^FN?M(ADD|SUB)[DS]rrr")>; 553 554def : InstRW<[A57Write_10cyc_1L_1V], (instregex "^[FSU]CVT[AMNPZ][SU](_Int)?[SU]?[XW]?[DS]?[rds]i?")>; 555def : InstRW<[A57Write_10cyc_1L_1V], (instregex "^[SU]CVTF")>; 556 557def : InstRW<[A57Write_32cyc_1W], (instrs FDIVDrr)>; 558def : InstRW<[A57Write_17cyc_1W], (instrs FDIVSrr)>; 559 560def : InstRW<[A57Write_5cyc_1V], (instregex "^F(MAX|MIN).+rr")>; 561 562def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT.+r")>; 563 564def : InstRW<[A57Write_32cyc_1W], (instrs FSQRTDr)>; 565def : InstRW<[A57Write_17cyc_1W], (instrs FSQRTSr)>; 566 567def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDNPDi)>; 568def : InstRW<[A57Write_6cyc_2L, WriteLDHi], (instrs LDNPQi)>; 569def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDNPSi)>; 570def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDPDi)>; 571def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPDpost)>; 572def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPDpre)>; 573def : InstRW<[A57Write_6cyc_2L, WriteLDHi], (instrs LDPQi)>; 574def : InstRW<[A57Write_6cyc_2L, WriteLDHi, WriteAdr], (instrs LDPQpost)>; 575def : InstRW<[A57Write_6cyc_2L, WriteLDHi, WriteAdr], (instrs LDPQpre)>; 576def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi], (instrs LDPSWi)>; 577def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi, WriteAdr], (instrs LDPSWpost)>; 578def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi, WriteAdr], (instrs LDPSWpre)>; 579def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDPSi)>; 580def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPSpost)>; 581def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPSpre)>; 582def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRBpost)>; 583def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRBpre)>; 584def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRBroW)>; 585def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRBroX)>; 586def : InstRW<[A57Write_5cyc_1L], (instrs LDRBui)>; 587def : InstRW<[A57Write_5cyc_1L], (instrs LDRDl)>; 588def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRDpost)>; 589def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRDpre)>; 590def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRDroW)>; 591def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRDroX)>; 592def : InstRW<[A57Write_5cyc_1L], (instrs LDRDui)>; 593def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRHHroW)>; 594def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRHHroX)>; 595def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRHpost)>; 596def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRHpre)>; 597def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRHroW)>; 598def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRHroX)>; 599def : InstRW<[A57Write_5cyc_1L], (instrs LDRHui)>; 600def : InstRW<[A57Write_5cyc_1L], (instrs LDRQl)>; 601def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRQpost)>; 602def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRQpre)>; 603def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRQroW)>; 604def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRQroX)>; 605def : InstRW<[A57Write_5cyc_1L], (instrs LDRQui)>; 606def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHWroW)>; 607def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHWroX)>; 608def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHXroW)>; 609def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHXroX)>; 610def : InstRW<[A57Write_5cyc_1L], (instrs LDRSl)>; 611def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRSpost)>; 612def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRSpre)>; 613def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRSroW)>; 614def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRSroX)>; 615def : InstRW<[A57Write_5cyc_1L], (instrs LDRSui)>; 616def : InstRW<[A57Write_5cyc_1L], (instrs LDURBi)>; 617def : InstRW<[A57Write_5cyc_1L], (instrs LDURDi)>; 618def : InstRW<[A57Write_5cyc_1L], (instrs LDURHi)>; 619def : InstRW<[A57Write_5cyc_1L], (instrs LDURQi)>; 620def : InstRW<[A57Write_5cyc_1L], (instrs LDURSi)>; 621 622def : InstRW<[A57Write_2cyc_2S], (instrs STNPDi)>; 623def : InstRW<[A57Write_4cyc_1I_4S], (instrs STNPQi)>; 624def : InstRW<[A57Write_2cyc_2S], (instrs STNPXi)>; 625def : InstRW<[A57Write_2cyc_2S], (instrs STPDi)>; 626def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPDpost)>; 627def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPDpre)>; 628def : InstRW<[A57Write_4cyc_1I_4S], (instrs STPQi)>; 629def : InstRW<[WriteAdr, A57Write_4cyc_1I_4S], (instrs STPQpost)>; 630def : InstRW<[WriteAdr, A57Write_4cyc_2I_4S], (instrs STPQpre)>; 631def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPSpost)>; 632def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPSpre)>; 633def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPWpost)>; 634def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPWpre)>; 635def : InstRW<[A57Write_2cyc_2S], (instrs STPXi)>; 636def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPXpost)>; 637def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPXpre)>; 638def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBBpost)>; 639def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBBpre)>; 640def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBpost)>; 641def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRBpre)>; 642def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRBroW)>; 643def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRBroX)>; 644def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRDpost)>; 645def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRDpre)>; 646def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHHpost)>; 647def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHHpre)>; 648def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHHroW)>; 649def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHHroX)>; 650def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHpost)>; 651def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRHpre)>; 652def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHroW)>; 653def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHroX)>; 654def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQpost)>; 655def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STRQpre)>; 656def : InstRW<[A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQroW)>; 657def : InstRW<[A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQroX)>; 658def : InstRW<[A57Write_2cyc_1I_2S], (instrs STRQui)>; 659def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRSpost)>; 660def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRSpre)>; 661def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRWpost)>; 662def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRWpre)>; 663def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRXpost)>; 664def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRXpre)>; 665def : InstRW<[A57Write_2cyc_2S], (instrs STURQi)>; 666 667} // SchedModel = CortexA57Model 668