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Searched refs:CRm (Results 1 – 25 of 39) sorted by relevance

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/external/arm-trusted-firmware/include/arch/aarch32/
Darch_helpers.h22 #define _DEFINE_COPROCR_WRITE_FUNC(_name, coproc, opc1, CRn, CRm, opc2) \ argument
25 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
28 #define _DEFINE_COPROCR_READ_FUNC(_name, coproc, opc1, CRn, CRm, opc2) \ argument
32 __asm__ volatile ("mrc "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : "=r" (v));\
41 #define _DEFINE_COPROCR_WRITE_FUNC_64(_name, coproc, opc1, CRm) \ argument
44 __asm__ volatile ("mcrr "#coproc","#opc1", %Q0, %R0,"#CRm : : "r" (v));\
47 #define _DEFINE_COPROCR_READ_FUNC_64(_name, coproc, opc1, CRm) \ argument
50 __asm__ volatile ("mrrc "#coproc","#opc1", %Q0, %R0,"#CRm : "=r" (v));\
109 #define _DEFINE_TLBIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \ argument
113 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
[all …]
Dasm_macros.S32 .macro ldcopr reg, coproc, opc1, CRn, CRm, opc2
33 mrc \coproc, \opc1, \reg, \CRn, \CRm, \opc2
36 .macro ldcopr16 reg1, reg2, coproc, opc1, CRm argument
37 mrrc \coproc, \opc1, \reg1, \reg2, \CRm
40 .macro stcopr reg, coproc, opc1, CRn, CRm, opc2
41 mcr \coproc, \opc1, \reg, \CRn, \CRm, \opc2
44 .macro stcopr16 reg1, reg2, coproc, opc1, CRm argument
45 mcrr \coproc, \opc1, \reg1, \reg2, \CRm
/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.cpp93 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
98 Ops[4].getAsInteger(10, CRm); in parseGenericRegister()
100 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in parseGenericRegister()
110 uint32_t CRm = (Bits >> 3) & 0xf; in genericRegisterString() local
114 utostr(CRm) + "_" + utostr(Op2); in genericRegisterString()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.cpp135 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
140 Ops[4].getAsInteger(10, CRm); in parseGenericRegister()
142 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in parseGenericRegister()
152 uint32_t CRm = (Bits >> 3) & 0xf; in genericRegisterString() local
156 utostr(CRm) + "_" + utostr(Op2); in genericRegisterString()
/external/llvm-project/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.cpp135 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
140 Ops[4].getAsInteger(10, CRm); in parseGenericRegister()
142 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in parseGenericRegister()
152 uint32_t CRm = (Bits >> 3) & 0xf; in genericRegisterString() local
156 utostr(CRm) + "_" + utostr(Op2); in genericRegisterString()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td443 // op1 CRn CRm op2
462 // op1 CRn CRm op2
558 // Op0 Op1 CRn CRm Op2
623 // Op0 Op1 CRn CRm Op2
662 // Op0 Op1 CRn CRm Op2
673 // Op0 Op1 CRn CRm Op2
679 // Op0 Op1 CRn CRm Op2
684 // Op0 Op1 CRn CRm Op2
691 // Op0 Op1 CRn CRm Op2
710 // Op0 Op1 CRn CRm Op2
[all …]
DAArch64InstrFormats.td1307 class TMBaseSystemI<bit L, bits<4> CRm, bits<3> op2, dag oops, dag iops,
1312 let Inst{11-8} = CRm;
1321 class TMSystemI<bits<4> CRm, string asm, list<dag> pattern>
1322 : TMBaseSystemI<0b1, CRm, 0b011,
1329 class TMSystemINoOperand<bits<4> CRm, string asm, list<dag> pattern>
1330 : TMBaseSystemI<0b0, CRm, 0b011, (outs), (ins), asm, "", pattern> {
1345 // Hint instructions that take both a CRm and a 3-bit immediate.
1359 // CRm. op2 differentiates the opcodes.
1370 : SimpleSystemI<0, (ins crmtype:$CRm), asm, "\t$CRm", pattern>,
1372 bits<4> CRm;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td438 // op1 CRn CRm op2
457 // op1 CRn CRm op2
553 // Op0 Op1 CRn CRm Op2
618 // Op0 Op1 CRn CRm Op2
657 // Op0 Op1 CRn CRm Op2
668 // Op0 Op1 CRn CRm Op2
674 // Op0 Op1 CRn CRm Op2
679 // Op0 Op1 CRn CRm Op2
686 // Op0 Op1 CRn CRm Op2
705 // Op0 Op1 CRn CRm Op2
[all …]
DAArch64InstrFormats.td1183 class TMBaseSystemI<bit L, bits<4> CRm, bits<3> op2, dag oops, dag iops,
1188 let Inst{11-8} = CRm;
1197 class TMSystemI<bits<4> CRm, string asm, list<dag> pattern>
1198 : TMBaseSystemI<0b1, CRm, 0b011,
1205 class TMSystemINoOperand<bits<4> CRm, string asm, list<dag> pattern>
1206 : TMBaseSystemI<0b0, CRm, 0b011, (outs), (ins), asm, "", pattern> {
1221 // Hint instructions that take both a CRm and a 3-bit immediate.
1235 // CRm. op2 differentiates the opcodes.
1246 : SimpleSystemI<0, (ins crmtype:$CRm), asm, "\t$CRm", pattern>,
1248 bits<4> CRm;
[all …]
/external/arm-trusted-firmware/lib/aarch32/
Dcache_helpers.S22 .macro do_dcache_maintenance_by_mva op, coproc, opc1, CRn, CRm, opc2
31 stcopr r0, \coproc, \opc1, \CRn, \CRm, \opc2
/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td311 // Op0 Op1 CRn CRm Op2
366 // Op0 Op1 CRn CRm Op2
405 // Op0 Op1 CRn CRm Op2
416 // Op0 Op1 CRn CRm Op2
421 // Op0 Op1 CRn CRm Op2
431 // Op0 Op1 CRn CRm Op2
437 // Op0 Op1 CRn CRm Op2
442 // Op0 Op1 CRn CRm Op2
454 // Op0 Op1 CRn CRm Op2
709 // Op0 Op1 CRn CRm Op2
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DAArch64InstrFormats.td856 // Hint instructions that take both a CRm and a 3-bit immediate.
870 // CRm. op2 differentiates the opcodes.
881 : SimpleSystemI<0, (ins crmtype:$CRm), asm, "\t$CRm", pattern>,
883 bits<4> CRm;
885 let Inst{11-8} = CRm;
896 // concatenation of op0, op1, CRn, CRm, op2. 16-bit immediate.
923 // "psb" is an alias to "hint" only for certain values of CRm:Op2 fields.
/external/capstone/arch/AArch64/
DAArch64BaseInfo.c633 uint32_t Op0, Op1, CRn, CRm, Op2; in A64SysRegMapper_toString() local
668 CRm = (Bits >> 3) & 0xf; in A64SysRegMapper_toString()
674 CRmS = utostr(CRm, false); in A64SysRegMapper_toString()
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td4151 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
4161 bits<4> CRm;
4168 let Inst{3-0} = CRm;
4174 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4183 bits<4> CRm;
4189 let Inst{3-0} = CRm;
4196 c_imm:$CRm, imm0_7:$opc2),
4198 imm:$CRm, imm:$opc2)]>,
4200 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4202 c_imm:$CRm, 0, pred:$p)>;
[all …]
DARMInstrInfo.td4813 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4814 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4816 imm:$CRm, imm:$opc2)]>,
4823 bits<4> CRm;
4825 let Inst{3-0} = CRm;
4835 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4836 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4838 imm:$CRm, imm:$opc2)]>,
4846 bits<4> CRm;
4848 let Inst{3-0} = CRm;
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrInfo.td5308 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
5309 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
5311 timm:$CRm, timm:$opc2)]>,
5318 bits<4> CRm;
5320 let Inst{3-0} = CRm;
5332 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
5333 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
5335 timm:$CRm, timm:$opc2)]>,
5343 bits<4> CRm;
5345 let Inst{3-0} = CRm;
[all …]
DARMInstrThumb2.td4454 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
4464 bits<4> CRm;
4471 let Inst{3-0} = CRm;
4479 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4488 bits<4> CRm;
4494 let Inst{3-0} = CRm;
4503 c_imm:$CRm, imm0_7:$opc2),
4505 timm:$CRm, timm:$opc2)]>,
4507 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4509 c_imm:$CRm, 0, pred:$p)>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrInfo.td5158 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
5159 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
5161 timm:$CRm, timm:$opc2)]>,
5168 bits<4> CRm;
5170 let Inst{3-0} = CRm;
5182 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
5183 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
5185 timm:$CRm, timm:$opc2)]>,
5193 bits<4> CRm;
5195 let Inst{3-0} = CRm;
[all …]
DARMInstrThumb2.td4385 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
4395 bits<4> CRm;
4402 let Inst{3-0} = CRm;
4410 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4419 bits<4> CRm;
4425 let Inst{3-0} = CRm;
4434 c_imm:$CRm, imm0_7:$opc2),
4436 timm:$CRm, timm:$opc2)]>,
4438 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4440 c_imm:$CRm, 0, pred:$p)>;
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenGlobalISel.inc30890 // MIs[0] CRm
30892 …] }):$CRm) => (MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, …
30898 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
30918 // MIs[0] CRm
30920 … }):$CRm) => (MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, …
30926 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
30944 // MIs[0] CRm
30946 …i32] }):$CRm) => (t2MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt,…
30952 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
30972 // MIs[0] CRm
[all …]
DARMGenMCCodeEmitter.inc7457 // op: CRm
7687 // op: CRm
7877 // op: CRm
7906 // op: CRm
12669 // op: CRm
15252 // op: CRm
15518 // op: CRm
15735 // op: CRm
15840 // op: CRm
15882 // op: CRm
/external/capstone/arch/ARM/
DARMGenAsmWriter.inc8929 // (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p)
8940 // (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0)
8984 // (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0, pred:$p)
8995 // (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0)
11000 // (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p)
11011 // (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p)
11031 // (t2MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0, pred:$p)
11042 // (t2MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0, pred:$p)
DARMDisassembler.c5181 unsigned CRm = fieldFromInstruction_4(Val, 0, 4); in DecodeMRRC2() local
5199 MCOperand_CreateImm0(Inst, CRm); in DecodeMRRC2()
/external/clang/lib/CodeGen/
DCGBuiltin.cpp4038 Value *CRm = EmitScalarExpr(E->getArg(3)); in EmitARMBuiltinExpr() local
4045 return Builder.CreateCall(F, {Coproc, Opc1, Rt, Rt2, CRm}); in EmitARMBuiltinExpr()
4064 Value *CRm = EmitScalarExpr(E->getArg(2)); in EmitARMBuiltinExpr() local
4065 Value *RtAndRt2 = Builder.CreateCall(F, {Coproc, Opc1, CRm}); in EmitARMBuiltinExpr()
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp5273 unsigned CRm = fieldFromInstruction(Val, 0, 4); in DecoderForMRRC2AndMCRR2() local
5309 Inst.addOperand(MCOperand::createImm(CRm)); in DecoderForMRRC2AndMCRR2()

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