| /external/arm-trusted-firmware/fdts/ |
| D | stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 7 * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs
8 * DDR type: DDR3 / DDR3L
9 * DDR width: 32bits
10 * DDR density: 8Gb
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| D | stm32mp15-ddr3-1x4Gb-1066-binG.dtsi | 7 * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs
8 * DDR type: DDR3 / DDR3L
9 * DDR width: 16bits
10 * DDR density: 4Gb
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| /external/arm-trusted-firmware/docs/plat/marvell/armada/ |
| D | build.rst | 151 For Armada37x0 only, the DDR topology map index/name, default is 0.
166 For Armada37x0 only, the clock tree configuration preset including CPU and DDR frequency,
169 - CPU_600_DDR_600 - CPU at 600 MHz, DDR at 600 MHz
170 - CPU_800_DDR_800 - CPU at 800 MHz, DDR at 800 MHz
171 - CPU_1000_DDR_800 - CPU at 1000 MHz, DDR at 800 MHz
172 - CPU_1200_DDR_750 - CPU at 1200 MHz, DDR at 750 MHz
219 binary and sys-init code from the WTP directory which sets DDR and CPU
257 the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR4 2CS,
306 In order to work in 32bit DDR, instead of the default 64bit ECC DDR,
358 (2) DDR initialization library sources (mv_ddr) available at the following repository
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| D | porting.rst | 80 DDR Porting (dram_port.c)
85 The DDR code is part of the BLE component, which is an extension of ARM Trusted
88 The DDR driver called mv_ddr is released separately apart from TF-A sources.
90 The BLE and consequently, the DDR init code is executed at the early stage of
93 Each supported platform of the TF-A has its own DDR porting file called
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| /external/arm-trusted-firmware/docs/plat/ |
| D | intel-stratix10.rst | 7 the hardware, then loads bl31 and bl33 (UEFI) into DDR and boots to bl33.
71 INFO: DDR: DRAM calibration success.
73 INFO: Init HPS NOC's DDR Scheduler.
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| D | intel-agilex.rst | 7 the hardware, then loads bl31 and bl33 (UEFI) into DDR and boots to bl33.
71 INFO: DDR: DRAM calibration success.
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| D | brcm-stingray.rst | 11 then loads bl31 and bl33 into DDR and boots to bl33.
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| D | rcar-gen3.rst | 59 DDR 4 GB LPDDR4
74 BL2 initializes DDR (and on some platforms i2c to interface to the
77 During suspend all CPUs are switched off and the DDR is put in backup
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| D | rz-g2.rst | 62 DDR 4 GB LPDDR4
74 BL2 initializes DDR before determining the boot reason (cold or warm).
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| /external/libavc/encoder/ |
| D | ih264e_time_stamp.c | 239 ALIGN_128_BYTE, PERSISTENT, DDR); in ih264e_frame_time_get_init_free_memtab()
429 ALIGN_128_BYTE, PERSISTENT, DDR); in ih264e_time_stamp_get_init_free_memtab()
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| D | irc_mem_req_and_acq.h | 82 DDR = 3 enumerator
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| D | ih264e_rc_mem_interface.h | 82 DDR = 3 enumerator
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| D | ih264e_modify_frm_rate.c | 120 ALIGN_128_BYTE, PERSISTENT, DDR); in ih264e_pd_frm_rate_get_init_free_memtab()
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| D | irc_mb_model_based.c | 65 ALIGN_128_BYTE, PERSISTENT, DDR); in irc_mbrc_num_fill_use_free_memtab()
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| D | irc_fixed_point_error_bits.c | 78 ALIGN_128_BYTE, PERSISTENT, DDR); in irc_error_bits_num_fill_use_free_memtab()
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| D | irc_est_sad.c | 73 ALIGN_128_BYTE, PERSISTENT, DDR); in irc_est_sad_num_fill_use_free_memtab()
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| D | ih264e_rc_mem_interface.c | 300 rc_memtab->e_mem_region = DDR; in ih264e_map_itt_mem_rec_to_rc_mem_rec()
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| /external/libhevc/encoder/ |
| D | mem_req_and_acq.h | 50 DDR = 3 enumerator
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| D | rc_sad_acc.c | 74 &ps_memtab[i4_mem_tab_idx], sizeof(sad_acc_t), MEM_TAB_ALIGNMENT, PERSISTENT, DDR); in sad_acc_num_fill_use_free_memtab()
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| D | mb_model_based.c | 73 DDR); in mbrc_num_fill_use_free_memtab()
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| D | init_qp.c | 72 &ps_memtab[i4_mem_tab_idx], sizeof(init_qp_t), MEM_TAB_ALIGNMENT, PERSISTENT, DDR); in init_qp_num_fill_use_free_memtab()
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| D | fixed_point_error_bits.c | 78 &ps_memtab[i4_mem_tab_idx], sizeof(error_bits_t), MEM_TAB_ALIGNMENT, PERSISTENT, DDR); in error_bits_num_fill_use_free_memtab()
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| D | est_sad.c | 72 &ps_memtab[i4_mem_tab_idx], sizeof(est_sad_t), MEM_TAB_ALIGNMENT, PERSISTENT, DDR); in est_sad_num_fill_use_free_memtab()
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| D | vbr_storage_vbv.c | 91 DDR); in vbr_vbv_num_fill_use_free_memtab()
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| /external/arm-trusted-firmware/plat/brcm/board/stingray/ |
| D | platform.mk | 68 $(info Using DDR)
261 ifeq (${ELOG_STORE_MEDIA},DDR)
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