1Renesas RZ/G 2============ 3 4The "RZ/G" Family of high-end 64-bit Arm®-based microprocessors (MPUs) 5enables the solutions required for the smart society of the future. 6Through a variety of Arm Cortex®-A53 and A57-based devices, engineers can 7easily implement high-resolution human machine interfaces (HMI), embedded 8vision, embedded artificial intelligence (e-AI) and real-time control and 9industrial ethernet connectivity. 10 11The scalable RZ/G hardware platform and flexible software platform 12cover the full product range, from the premium class to the entry 13level. Plug-ins are available for multiple open-source software tools. 14 15 16Renesas RZ/G2 reference platforms: 17---------------------------------- 18 19+--------------+----------------------------------------------------------------------------------+ 20| Board | Details | 21+==============+===============+==================================================================+ 22| hihope-rzg2h | "96 boards" compatible board from Hoperun equipped with Renesas RZ/G2H SoC | 23| +----------------------------------------------------------------------------------+ 24| | http://hihope.org/product/musashi | 25+--------------+----------------------------------------------------------------------------------+ 26| hihope-rzg2m | "96 boards" compatible board from Hoperun equipped with Renesas RZ/G2M SoC | 27| +----------------------------------------------------------------------------------+ 28| | http://hihope.org/product/musashi | 29+--------------+----------------------------------------------------------------------------------+ 30| hihope-rzg2n | "96 boards" compatible board from Hoperun equipped with Renesas RZ/G2N SoC | 31| +----------------------------------------------------------------------------------+ 32| | http://hihope.org/product/musashi | 33+--------------+----------------------------------------------------------------------------------+ 34| ek874 | "96 boards" compatible board from Silicon Linux equipped with Renesas RZ/G2E SoC | 35| +----------------------------------------------------------------------------------+ 36| | https://www.si-linux.co.jp/index.php?CAT%2FCAT874 | 37+--------------+----------------------------------------------------------------------------------+ 38 39`boards info <https://www.renesas.com/us/en/products/rzg-linux-platform/rzg-marcketplace/board-solutions.html#rzg2>`__ 40 41The current TF-A port has been tested on the HiHope RZ/G2M 42SoC_id r8a774a1 revision ES1.3. 43 44 45:: 46 47 ARM CA57 (ARMv8) 1.5 GHz dual core, with NEON/VFPv4, L1$ I/D 48K/32K, L2$ 1MB 48 ARM CA53 (ARMv8) 1.2 GHz quad core, with NEON/VFPv4, L1$ I/D 32K/32K, L2$ 512K 49 Memory controller for LPDDR4-3200 4GB in 2 channels(32-bit bus mode) 50 Two- and three-dimensional graphics engines, 51 Video processing units, 52 Display Output, 53 Video Input, 54 SD card host interface, 55 USB3.0 and USB2.0 interfaces, 56 CAN interfaces, 57 Ethernet AVB, 58 Wi-Fi + BT, 59 PCI Express Interfaces, 60 Memories 61 INTERNAL 384KB SYSTEM RAM 62 DDR 4 GB LPDDR4 63 QSPI FLASH 64MB 64 EMMC 32 GB EMMC (HS400 240 MBYTES/S) 65 MICROSD-CARD SLOT (SDR104 100 MBYTES/S) 66 67Overview 68-------- 69On RZ/G2 SoCs the BOOTROM starts the cpu at EL3; for this port BL2 70will therefore be entered at this exception level (the Renesas' ATF 71reference tree [1] resets into EL1 before entering BL2 - see its 72bl2.ld.S) 73 74BL2 initializes DDR before determining the boot reason (cold or warm). 75 76Once BL2 boots, it determines the boot reason, writes it to shared 77memory (BOOT_KIND_BASE) together with the BL31 parameters 78(PARAMS_BASE) and jumps to BL31. 79 80To all effects, BL31 is as if it is being entered in reset mode since 81it still needs to initialize the rest of the cores; this is the reason 82behind using direct shared memory access to BOOT_KIND_BASE _and_ 83PARAMS_BASE instead of using registers to get to those locations (see 84el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use 85case). 86 87[1] https://github.com/renesas-rz/meta-rzg2/tree/BSP-1.0.5/recipes-bsp/arm-trusted-firmware/files 88 89 90How to build 91------------ 92 93The TF-A build options depend on the target board so you will have to 94refer to those specific instructions. What follows is customized to 95the HiHope RZ/G2M development kit used in this port. 96 97Build Tested: 98~~~~~~~~~~~~~ 99 100.. code:: bash 101 102 make bl2 bl31 rzg LOG_LEVEL=40 PLAT=rzg LSI=G2M RCAR_DRAM_SPLIT=2\ 103 RCAR_LOSSY_ENABLE=1 SPD="none" MBEDTLS_DIR=$mbedtls 104 105System Tested: 106~~~~~~~~~~~~~~ 107* mbed_tls: 108 git@github.com:ARMmbed/mbedtls.git [devel] 109 110| commit 72ca39737f974db44723760623d1b29980c00a88 111| Merge: ef94c4fcf dd9ec1c57 112| Author: Janos Follath <janos.follath@arm.com> 113| Date: Wed Oct 7 09:21:01 2020 +0100 114 115* u-boot: 116 The port has beent tested using mainline uboot with HiHope RZ/G2M board 117 specific patches. 118 119| commit 46ce9e777c1314ccb78906992b94001194eaa87b 120| Author: Heiko Schocher <hs@denx.de> 121| Date: Tue Nov 3 15:22:36 2020 +0100 122 123* linux: 124 The port has beent tested using mainline kernel. 125 126| commit f8394f232b1eab649ce2df5c5f15b0e528c92091 127| Author: Linus Torvalds <torvalds@linux-foundation.org> 128| Date: Sun Nov 8 16:10:16 2020 -0800 129| Linux 5.10-rc3 130 131TF-A Build Procedure 132~~~~~~~~~~~~~~~~~~~~ 133 134- Fetch all the above 3 repositories. 135 136- Prepare the AARCH64 toolchain. 137 138- Build u-boot using hihope_rzg2_defconfig. 139 140 Result: u-boot-elf.srec 141 142.. code:: bash 143 144 make CROSS_COMPILE=aarch64-linux-gnu- 145 hihope_rzg2_defconfig 146 147 make CROSS_COMPILE=aarch64-linux-gnu- 148 149- Build TF-A 150 151 Result: bootparam_sa0.srec, cert_header_sa6.srec, bl2.srec, bl31.srec 152 153.. code:: bash 154 155 make bl2 bl31 rzg LOG_LEVEL=40 PLAT=rzg LSI=G2M RCAR_DRAM_SPLIT=2\ 156 RCAR_LOSSY_ENABLE=1 SPD="none" MBEDTLS_DIR=$mbedtls 157 158 159Install Procedure 160~~~~~~~~~~~~~~~~~ 161 162- Boot the board in Mini-monitor mode and enable access to the 163 QSPI flash. 164 165 166- Use the flash_writer utility[2] to flash all the SREC files. 167 168[2] https://github.com/renesas-rz/rzg2_flash_writer 169 170 171Boot trace 172---------- 173:: 174 175 INFO: ARM GICv2 driver initialized 176 NOTICE: BL2: RZ/G2 Initial Program Loader(CA57) Rev.2.0.6 177 NOTICE: BL2: PRR is RZ/G2M Ver.1.3 178 NOTICE: BL2: Board is HiHope RZ/G2M Rev.4.0 179 NOTICE: BL2: Boot device is QSPI Flash(40MHz) 180 NOTICE: BL2: LCM state is unknown 181 NOTICE: BL2: DDR3200(rev.0.40) 182 NOTICE: BL2: [COLD_BOOT] 183 NOTICE: BL2: DRAM Split is 2ch 184 NOTICE: BL2: QoS is default setting(rev.0.19) 185 NOTICE: BL2: DRAM refresh interval 1.95 usec 186 NOTICE: BL2: Periodic Write DQ Training 187 NOTICE: BL2: CH0: 400000000 - 47fffffff, 2 GiB 188 NOTICE: BL2: CH2: 600000000 - 67fffffff, 2 GiB 189 NOTICE: BL2: Lossy Decomp areas 190 NOTICE: Entry 0: DCMPAREACRAx:0x80000540 DCMPAREACRBx:0x570 191 NOTICE: Entry 1: DCMPAREACRAx:0x40000000 DCMPAREACRBx:0x0 192 NOTICE: Entry 2: DCMPAREACRAx:0x20000000 DCMPAREACRBx:0x0 193 NOTICE: BL2: FDT at 0xe631db30 194 NOTICE: BL2: v2.3(release):v2.4-rc0-2-g1433701e5 195 NOTICE: BL2: Built : 13:45:26, Nov 7 2020 196 NOTICE: BL2: Normal boot 197 INFO: BL2: Doing platform setup 198 INFO: BL2: Loading image id 3 199 NOTICE: BL2: dst=0xe631d200 src=0x8180000 len=512(0x200) 200 NOTICE: BL2: dst=0x43f00000 src=0x8180400 len=6144(0x1800) 201 WARNING: r-car ignoring the BL31 size from certificate,using RCAR_TRUSTED_SRAM_SIZE instead 202 INFO: Loading image id=3 at address 0x44000000 203 NOTICE: rcar_file_len: len: 0x0003e000 204 NOTICE: BL2: dst=0x44000000 src=0x81c0000 len=253952(0x3e000) 205 INFO: Image id=3 loaded: 0x44000000 - 0x4403e000 206 INFO: BL2: Loading image id 5 207 INFO: Loading image id=5 at address 0x50000000 208 NOTICE: rcar_file_len: len: 0x00100000 209 NOTICE: BL2: dst=0x50000000 src=0x8300000 len=1048576(0x100000) 210 INFO: Image id=5 loaded: 0x50000000 - 0x50100000 211 NOTICE: BL2: Booting BL31 212 INFO: Entry point address = 0x44000000 213 INFO: SPSR = 0x3cd 214 215 216 U-Boot 2021.01-rc1-00244-gac37e14fbd (Nov 04 2020 - 20:03:34 +0000) 217 218 CPU: Renesas Electronics R8A774A1 rev 1.3 219 Model: HopeRun HiHope RZ/G2M with sub board 220 DRAM: 3.9 GiB 221 MMC: mmc@ee100000: 0, mmc@ee160000: 1 222 Loading Environment from MMC... OK 223 In: serial@e6e88000 224 Out: serial@e6e88000 225 Err: serial@e6e88000 226 Net: eth0: ethernet@e6800000 227 Hit any key to stop autoboot: 0 228 => 229