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Searched refs:DIV_ROUND_UP (Results 1 – 25 of 179) sorted by relevance

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/external/mesa3d/src/freedreno/vulkan/
Dtu_util.c104 fb->tile0.width = util_align_npot(DIV_ROUND_UP(fb->width, 2), tile_align_w); in tu_tiling_config_update_tile_layout()
105 fb->tile0.height = align(DIV_ROUND_UP(fb->height, 2), tile_align_h); in tu_tiling_config_update_tile_layout()
112 util_align_npot(DIV_ROUND_UP(fb->width, fb->tile_count.width), tile_align_w); in tu_tiling_config_update_tile_layout()
126 util_align_npot(DIV_ROUND_UP(fb->width, fb->tile_count.width), tile_align_w); in tu_tiling_config_update_tile_layout()
132 align(DIV_ROUND_UP(fb->height, fb->tile_count.height), tile_align_h); in tu_tiling_config_update_tile_layout()
154 DIV_ROUND_UP(fb->tile_count.width, fb->pipe0.width); in tu_tiling_config_update_pipe_layout()
158 DIV_ROUND_UP(fb->tile_count.height, fb->pipe0.height); in tu_tiling_config_update_pipe_layout()
/external/mesa3d/src/intel/tools/
Dintel_noop_drm_shim.c211 DIV_ROUND_UP(i915.devinfo.num_slices, 8) + in query_write_topology()
212 i915.devinfo.num_slices * DIV_ROUND_UP(i915.devinfo.num_subslices[0], 8) + in query_write_topology()
214 DIV_ROUND_UP(i915.devinfo.num_eu_per_subslice, 8); in query_write_topology()
235 info->subslice_offset = DIV_ROUND_UP(i915.devinfo.num_slices, 8); in query_write_topology()
236 info->subslice_stride = DIV_ROUND_UP(i915.devinfo.num_subslices[0], 8); in query_write_topology()
254 for (uint32_t i = 0; i < DIV_ROUND_UP(info->max_eus_per_subslice, 8); i++) { in query_write_topology()
256 … (s * info->max_subslices + ss) * DIV_ROUND_UP(info->max_eus_per_subslice, 8) + i] = in query_write_topology()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_compute_blit.c125 unsigned size_12 = DIV_ROUND_UP(size, 12); in si_compute_clear_12bytes_buffer()
166 info.grid[0] = DIV_ROUND_UP(size_12, 64); in si_compute_clear_12bytes_buffer()
220 unsigned num_instructions = DIV_ROUND_UP(num_dwords, dwords_per_instruction); in si_compute_do_clear_or_copy()
226 info.grid[0] = DIV_ROUND_UP(num_dwords, dwords_per_wave); in si_compute_do_clear_or_copy()
564 info.grid[i] = DIV_ROUND_UP(dim[i], info.block[i]); in si_compute_copy_image()
574 info.grid[0] = DIV_ROUND_UP(width, 64); in si_compute_copy_image()
593 info.grid[0] = DIV_ROUND_UP(width, info.block[0]); in si_compute_copy_image()
594 info.grid[1] = DIV_ROUND_UP(height, info.block[1]); in si_compute_copy_image()
666 info.grid[0] = DIV_ROUND_UP(num_threads, 64); /* includes the partial block */ in si_retile_dcc()
731 info.grid[0] = DIV_ROUND_UP(tex->width0, 8); in si_compute_expand_fmask()
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Dcik_sdma.c32 return DIV_ROUND_UP(width, blk_w); in minify_as_blocks()
73 unsigned copy_width = DIV_ROUND_UP(src_box->width, ssrc->surface.blk_w); in si_sdma_v4_copy_texture()
74 unsigned copy_height = DIV_ROUND_UP(src_box->height, ssrc->surface.blk_h); in si_sdma_v4_copy_texture()
146 ? DIV_ROUND_UP(ssrc->buffer.b.b.width0, ssrc->surface.blk_w) in si_sdma_v4_copy_texture()
147 : DIV_ROUND_UP(sdst->buffer.b.b.width0, sdst->surface.blk_w); in si_sdma_v4_copy_texture()
149 ? DIV_ROUND_UP(ssrc->buffer.b.b.height0, ssrc->surface.blk_h) in si_sdma_v4_copy_texture()
150 : DIV_ROUND_UP(sdst->buffer.b.b.height0, sdst->surface.blk_h); in si_sdma_v4_copy_texture()
235 unsigned copy_width = DIV_ROUND_UP(src_box->width, ssrc->surface.blk_w); in cik_sdma_copy_texture()
236 unsigned copy_height = DIV_ROUND_UP(src_box->height, ssrc->surface.blk_h); in cik_sdma_copy_texture()
Dsi_dma_cs.c92 ncopy = DIV_ROUND_UP(size, SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE); in si_sdma_clear_buffer()
112 ncopy = DIV_ROUND_UP(size, max_size_per_packet); in si_sdma_clear_buffer()
165 ncopy = DIV_ROUND_UP(size, max_size); in si_sdma_copy_buffer()
187 ncopy = DIV_ROUND_UP(size, max_size_per_packet); in si_sdma_copy_buffer()
/external/mesa3d/src/intel/dev/
Dgen_device_info.c1014 devinfo->subslice_slice_stride = DIV_ROUND_UP(max_subslices, 8); in fill_masks()
1022 devinfo->eu_subslice_stride = DIV_ROUND_UP(devinfo->num_eu_per_subslice, 8); in fill_masks()
1058 devinfo->eu_subslice_stride = DIV_ROUND_UP(topology->max_eus_per_subslice, 8); in update_from_topology()
1061 assert(sizeof(devinfo->slice_masks) >= DIV_ROUND_UP(topology->max_slices, 8)); in update_from_topology()
1062 memcpy(&devinfo->slice_masks, topology->data, DIV_ROUND_UP(topology->max_slices, 8)); in update_from_topology()
1121 devinfo->num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices); in update_from_topology()
1141 topology->subslice_offset = DIV_ROUND_UP(topology->max_slices, 8); in update_from_masks()
1142 topology->subslice_stride = DIV_ROUND_UP(topology->max_subslices, 8); in update_from_masks()
1146 uint32_t num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices); in update_from_masks()
1150 DIV_ROUND_UP(topology->max_subslices, 8); in update_from_masks()
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Dgen_device_info.h159 DIV_ROUND_UP(GEN_DEVICE_MAX_SUBSLICES, 8)];
167 DIV_ROUND_UP(GEN_DEVICE_MAX_EUS_PER_SUBSLICE, 8)];
/external/mesa3d/src/gallium/drivers/freedreno/a5xx/
Dfd5_resource.c35 unsigned lrz_pitch = align(DIV_ROUND_UP(rsc->base.width0, 8), 64); in setup_lrz()
36 unsigned lrz_height = DIV_ROUND_UP(rsc->base.height0, 8); in setup_lrz()
/external/linux-kselftest/tools/testing/selftests/kvm/lib/
Dkvm_util_internal.h23 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) macro
24 #define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_LONG)
/external/minigbm/
Drockchip.c52 const uint32_t width_in_blocks = DIV_ROUND_UP(width, block_width); in afbc_bo_from_format()
53 const uint32_t height_in_blocks = DIV_ROUND_UP(height, block_height); in afbc_bo_from_format()
118 uint32_t w_mbs = DIV_ROUND_UP(width, 16); in rockchip_bo_create_with_modifiers()
119 uint32_t h_mbs = DIV_ROUND_UP(height, 16); in rockchip_bo_create_with_modifiers()
Dhelpers_array.c67 if ((DIV_ROUND_UP(array->allocations, 2) > array->size) && array->allocations > 2) { in drv_array_remove()
69 array->allocations = DIV_ROUND_UP(array->allocations, 2); in drv_array_remove()
Dhelpers.c205 return DIV_ROUND_UP(height, layout->vertical_subsampling[plane]); in drv_height_from_format()
234 uint32_t plane_width = DIV_ROUND_UP(width, layout->horizontal_subsampling[plane]); in drv_stride_from_format()
258 stride = DIV_ROUND_UP(stride, 2); in subsample_stride()
337 aligned_height = 3 * DIV_ROUND_UP(height, 2); in drv_dumb_bo_create_ex()
344 aligned_height = 3 * DIV_ROUND_UP(height, 2); in drv_dumb_bo_create_ex()
352 DIV_ROUND_UP(aligned_width * layout_from_format(format)->bytes_per_pixel[0], 4); in drv_dumb_bo_create_ex()
Dvirtgpu_virgl.c155 c_plane_height = DIV_ROUND_UP(original_height, 2); in virgl_get_emulated_metadata()
178 c_plane_height = DIV_ROUND_UP(original_height, 2); in virgl_get_emulated_metadata()
238 c_plane_height = DIV_ROUND_UP(bo->meta.height, 2); in virgl_get_emulated_transfers_params()
250 xfer_params->xfer_boxes[1].height = DIV_ROUND_UP(transfer_box->height, 2); in virgl_get_emulated_transfers_params()
259 c_plane_height = DIV_ROUND_UP(bo->meta.height, 2); in virgl_get_emulated_transfers_params()
270 xfer_params->xfer_boxes[1].width = DIV_ROUND_UP(transfer_box->width, 2); in virgl_get_emulated_transfers_params()
271 xfer_params->xfer_boxes[1].height = DIV_ROUND_UP(transfer_box->height, 2); in virgl_get_emulated_transfers_params()
276 xfer_params->xfer_boxes[2].width = DIV_ROUND_UP(transfer_box->width, 2); in virgl_get_emulated_transfers_params()
277 xfer_params->xfer_boxes[2].height = DIV_ROUND_UP(transfer_box->height, 2); in virgl_get_emulated_transfers_params()
Dmsm.c57 macrotile_width = DIV_ROUND_UP(width, tile_width); in get_ubwc_meta_size()
58 macrotile_height = DIV_ROUND_UP(height, tile_height); in get_ubwc_meta_size()
104 uv_scanline = ALIGN(DIV_ROUND_UP(height, 2), in msm_calculate_layout()
/external/mesa3d/src/intel/compiler/
Dbrw_vec4_dead_code_eliminate.cpp60 for (unsigned i = 0; i < DIV_ROUND_UP(inst->size_written, 16); i++) { in dead_code_eliminate()
142 for (unsigned i = 0; i < DIV_ROUND_UP(inst->size_written, 16); i++) { in dead_code_eliminate()
164 for (unsigned j = 0; j < DIV_ROUND_UP(inst->size_read(i), 16); j++) { in dead_code_eliminate()
Dbrw_vec4_live_variables.h116 const unsigned csize = DIV_ROUND_UP(type_sz(reg.type), 4);
130 const unsigned csize = DIV_ROUND_UP(type_sz(reg.type), 4);
Dbrw_fs_bank_conflicts.cpp286 DIV_ROUND_UP(u.size, vector_width) * sizeof(vector_type)); in weight_vector_type()
310 const unsigned size = DIV_ROUND_UP(n, vector_width) * sizeof(vector_type); in alloc()
660 const unsigned cycle_scale = block_scale * DIV_ROUND_UP(exec_size, in shader_conflict_weight_matrix()
708 const unsigned m = DIV_ROUND_UP(conflicts[r].size, vector_width); in have_any_conflicts()
738 const unsigned m = DIV_ROUND_UP(conflicts.size, vector_width); in delta_conflicts()
/external/mesa3d/src/panfrost/shared/
Dpan_tiling.c265 w = DIV_ROUND_UP(w, desc->block.width); in panfrost_access_tiled_image_generic()
266 h = DIV_ROUND_UP(h, desc->block.height); in panfrost_access_tiled_image_generic()
302 unsigned first_full_tile_x = DIV_ROUND_UP(x, TILE_WIDTH) * TILE_WIDTH; in panfrost_access_tiled_image()
303 unsigned first_full_tile_y = DIV_ROUND_UP(y, TILE_HEIGHT) * TILE_HEIGHT; in panfrost_access_tiled_image()
/external/mesa3d/src/gallium/drivers/svga/include/
Dsvga3d_surfacedefs.h970 block_size->width = DIV_ROUND_UP(pixel_size->width, in svga3dsurface_get_size_in_blocks()
972 block_size->height = DIV_ROUND_UP(pixel_size->height, in svga3dsurface_get_size_in_blocks()
974 block_size->depth = DIV_ROUND_UP(pixel_size->depth, in svga3dsurface_get_size_in_blocks()
1144 const uint32 rowstride = DIV_ROUND_UP(width, bw) * desc->bytes_per_block; in svga3dsurface_get_pixel_offset()
1145 const uint32 imgstride = DIV_ROUND_UP(height, bh) * rowstride; in svga3dsurface_get_pixel_offset()
/external/mesa3d/src/gallium/drivers/freedreno/a6xx/
Dfd6_const.c56 .num_unit = DIV_ROUND_UP(sizedwords, 4) in fd6_emit_const_user()
68 .num_unit = DIV_ROUND_UP(sizedwords, 4) in fd6_emit_const_user()
82 uint32_t num_unit = DIV_ROUND_UP(sizedwords, 4); in fd6_emit_const_bo()
268 int size_vec4s = DIV_ROUND_UP(cb->buffer_size, 16); in fd6_emit_ubos()
Dfd6_resource.c134 unsigned lrz_pitch = align(DIV_ROUND_UP(width0, 8), 32); in setup_lrz()
135 unsigned lrz_height = align(DIV_ROUND_UP(height0, 8), 16); in setup_lrz()
/external/mesa3d/src/intel/common/
Dgen_urb_config.c160 chunks[i] = DIV_ROUND_UP(min_entries[i] * entry_size_bytes[i], in gen_get_urb_config()
164 DIV_ROUND_UP(devinfo->urb.max_entries[i] * entry_size_bytes[i], in gen_get_urb_config()
/external/mesa3d/src/panfrost/lib/
Dpan_scratch.c70 return util_logbase2_ceil(DIV_ROUND_UP(stack_size, 16)); in panfrost_get_stack_shift()
/external/erofs-utils/include/erofs/
Ddefs.h93 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) macro
153 #define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
/external/mesa3d/src/intel/vulkan/
Danv_nir_compute_push_layout.c123 .length = DIV_ROUND_UP(push_end - push_start, 32), in anv_nir_compute_push_layout()
238 unsigned prog_data_push_size = DIV_ROUND_UP(prog_data->nr_params, 8); in anv_nir_validate_push_layout()

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